date:20210519

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

An SEV-SNP guest is required to perform the GHCB GPA registration. See
the GHCB specification for further details.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Liming Gao 
Reviewed-by: Erdem Aktas 
Signed-off-by: Brijesh Singh 
---
 MdePkg/Include/Register/Amd/Fam17Msr.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
b/MdePkg/Include/Register/Amd/Fam17Msr.h
index cdb8f588ccf8..542e4cdf4782 100644
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -53,6 +53,11 @@ typedef union {
 UINT64  Features:52;
   } GhcbHypervisorFeatures;
 
+  struct {
+UINT64  Function:12;
+UINT64  GuestFrameNumber:52;
+  } GhcbGpaRegister;
+
   VOID*Ghcb;
 
   UINT64  GhcbPhysicalAddress;
@@ -62,6 +67,8 @@ typedef union {
 #define GHCB_INFO_SEV_INFO_GET  2
 #define GHCB_INFO_CPUID_REQUEST 4
 #define GHCB_INFO_CPUID_RESPONSE5
+#define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST 18
+#define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE19
 #define GHCB_HYPERVISOR_FEATURES_REQUEST128
 #define GHCB_HYPERVISOR_FEATURES_RESPONSE   129
 #define GHCB_INFO_TERMINATE_REQUEST 256
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75393): https://edk2.groups.io/g/devel/message/75393
Mute This Topic: https://groups.io/mt/82943404/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 13/13] OvmfPkg/BaseMemEncryptSevLib: remove Flush parameter

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The Flush parameter is used to provide a hint whether the specified range
is Mmio address. Now that we have a dedicated helper to clear the
memory encryption mask for the Mmio address range, its safe to remove the
Flush parameter from MemEncryptSev{Set,Clear}PageEncMask().

Since the address specified in the MemEncryptSev{Set,Clear}PageEncMask()
points to a system RAM, thus a cache flush is required during the
encryption mask update.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Reviewed-by: Laszlo Ersek 
Signed-off-by: Brijesh Singh 
---
 OvmfPkg/Include/Library/MemEncryptSevLib.h   | 10 ++
 .../BaseMemEncryptSevLib/X64/VirtualMemory.h | 10 ++
 OvmfPkg/AmdSevDxe/AmdSevDxe.c|  3 +--
 OvmfPkg/IoMmuDxe/AmdSevIoMmu.c   |  6 ++
 .../BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c | 10 ++
 .../BaseMemEncryptSevLib/X64/MemEncryptSevLib.c  | 16 
 .../X64/PeiDxeVirtualMemory.c| 14 --
 .../BaseMemEncryptSevLib/X64/SecVirtualMemory.c  |  8 ++--
 .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c|  3 +--
 OvmfPkg/PlatformPei/AmdSev.c |  3 +--
 10 files changed, 21 insertions(+), 62 deletions(-)

diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h 
b/OvmfPkg/Include/Library/MemEncryptSevLib.h
index b91490d5d44d..76d06c206c8b 100644
--- a/OvmfPkg/Include/Library/MemEncryptSevLib.h
+++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h
@@ -100,8 +100,6 @@ MemEncryptSevIsEnabled (
   address of a memory region.
   @param[in]  NumPagesThe number of pages from start memory
   region.
-  @param[in]  Flush   Flush the caches before clearing the bit
-  (mostly TRUE except MMIO addresses)
 
   @retval RETURN_SUCCESS  The attributes were cleared for the
   memory region.
@@ -114,8 +112,7 @@ EFIAPI
 MemEncryptSevClearPageEncMask (
   IN PHYSICAL_ADDRESS Cr3BaseAddress,
   IN PHYSICAL_ADDRESS BaseAddress,
-  IN UINTNNumPages,
-  IN BOOLEAN  Flush
+  IN UINTNNumPages
   );
 
 /**
@@ -128,8 +125,6 @@ MemEncryptSevClearPageEncMask (
   address of a memory region.
   @param[in]  NumPagesThe number of pages from start memory
   region.
-  @param[in]  Flush   Flush the caches before setting the bit
-  (mostly TRUE except MMIO addresses)
 
   @retval RETURN_SUCCESS  The attributes were set for the memory
   region.
@@ -142,8 +137,7 @@ EFIAPI
 MemEncryptSevSetPageEncMask (
   IN PHYSICAL_ADDRESS Cr3BaseAddress,
   IN PHYSICAL_ADDRESS BaseAddress,
-  IN UINTNNumPages,
-  IN BOOLEAN  Flush
+  IN UINTNNumPages
   );
 
 
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h 
b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
index 8dc39e647b90..21bbbd1c4f9c 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
@@ -58,8 +58,6 @@ InternalGetMemEncryptionAddressMask (
   @param[in]  PhysicalAddress The physical address that is the start
   address of a memory region.
   @param[in]  Length  The length of memory region
-  @param[in]  Flush   Flush the caches before applying the
-  encryption mask
 
   @retval RETURN_SUCCESS  The attributes were cleared for the
   memory region.
@@ -72,8 +70,7 @@ EFIAPI
 InternalMemEncryptSevSetMemoryDecrypted (
   IN  PHYSICAL_ADDRESSCr3BaseAddress,
   IN  PHYSICAL_ADDRESSPhysicalAddress,
-  IN  UINTN   Length,
-  IN  BOOLEAN Flush
+  IN  UINTN   Length
   );
 
 /**
@@ -85,8 +82,6 @@ InternalMemEncryptSevSetMemoryDecrypted (
   @param[in]  PhysicalAddress The physical address that is the start
   address of a memory region.
   @param[in]  Length  The length of memory region
-  @param[in]  Flush   Flush the caches before applying the
-  encryption mask
 
   @retval RETURN_SUCCESS  The attributes were set for the memory
   region.
@@ -99,8 +94,7 @@ EFIAPI
 InternalMemEncryptSevSetMemoryEncrypted (
   IN  PHYSICAL_ADDRESS

[edk2-devel] [PATCH v3 10/13] OvmfPkg/AmdSevDxe: use MemEncryptSevClearMmioPageEncMask() to clear EncMask

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
for the Mmio and NonExistent address range.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Reviewed-by: Laszlo Ersek 
Signed-off-by: Brijesh Singh 
---
 OvmfPkg/AmdSevDxe/AmdSevDxe.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.c b/OvmfPkg/AmdSevDxe/AmdSevDxe.c
index 689bfb376d03..80831b81facf 100644
--- a/OvmfPkg/AmdSevDxe/AmdSevDxe.c
+++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.c
@@ -53,11 +53,10 @@ AmdSevDxeEntryPoint (
   Desc = [Index];
   if (Desc->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo ||
   Desc->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
-Status = MemEncryptSevClearPageEncMask (
+Status = MemEncryptSevClearMmioPageEncMask (
0,
Desc->BaseAddress,
-   EFI_SIZE_TO_PAGES (Desc->Length),
-   FALSE
+   EFI_SIZE_TO_PAGES (Desc->Length)
);
 ASSERT_EFI_ERROR (Status);
   }
@@ -73,11 +72,10 @@ AmdSevDxeEntryPoint (
   // the range.
   //
   if (PcdGet16 (PcdOvmfHostBridgePciDevId) == INTEL_Q35_MCH_DEVICE_ID) {
-Status = MemEncryptSevClearPageEncMask (
+Status = MemEncryptSevClearMmioPageEncMask (
0,
FixedPcdGet64 (PcdPciExpressBaseAddress),
-   EFI_SIZE_TO_PAGES (SIZE_256MB),
-   FALSE
+   EFI_SIZE_TO_PAGES (SIZE_256MB)
);
 
 ASSERT_EFI_ERROR (Status);
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75401): https://edk2.groups.io/g/devel/message/75401
Mute This Topic: https://groups.io/mt/82943412/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 09/13] OvmfPkg/BaseMemEncryptSevLib: introduce MemEncryptSevClearMmioPageEncMask()

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The MemEncryptSevClearMmioPageEncMask() helper can be used for clearing
the memory encryption mask for the Mmio region.

The MemEncryptSevClearMmioPageEncMask() is a simplified version of
MemEncryptSevClearPageEncMask() -- it does not flush the caches after
clearing the page encryption mask.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Reviewed-by: Laszlo Ersek 
Signed-off-by: Brijesh Singh 
---
 OvmfPkg/Include/Library/MemEncryptSevLib.h| 25 ++
 .../BaseMemEncryptSevLib/X64/VirtualMemory.h  | 23 +
 .../Ia32/MemEncryptSevLib.c   | 31 +
 .../X64/MemEncryptSevLib.c| 33 +++
 .../X64/PeiDxeVirtualMemory.c | 33 +++
 .../X64/SecVirtualMemory.c| 30 +
 6 files changed, 175 insertions(+)

diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h 
b/OvmfPkg/Include/Library/MemEncryptSevLib.h
index 99f15a7d1271..b91490d5d44d 100644
--- a/OvmfPkg/Include/Library/MemEncryptSevLib.h
+++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h
@@ -203,4 +203,29 @@ MemEncryptSevGetAddressRangeState (
   IN UINTNLength
   );
 
+/**
+  This function clears memory encryption bit for the MMIO region specified by
+  BaseAddress and NumPages.
+
+  @param[in]  Cr3BaseAddress  Cr3 Base Address (if zero then use
+  current CR3)
+  @param[in]  BaseAddress The physical address that is the start
+  address of a MMIO region.
+  @param[in]  NumPagesThe number of pages from start memory
+  region.
+
+  @retval RETURN_SUCCESS  The attributes were cleared for the
+  memory region.
+  @retval RETURN_INVALID_PARAMETERNumber of pages is zero.
+  @retval RETURN_UNSUPPORTED  Clearing the memory encryption attribute
+  is not supported
+**/
+RETURN_STATUS
+EFIAPI
+MemEncryptSevClearMmioPageEncMask (
+  IN PHYSICAL_ADDRESS Cr3BaseAddress,
+  IN PHYSICAL_ADDRESS BaseAddress,
+  IN UINTNNumPages
+  );
+
 #endif // _MEM_ENCRYPT_SEV_LIB_H_
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h 
b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
index fe2a0b2826cd..8dc39e647b90 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
@@ -126,4 +126,27 @@ InternalMemEncryptSevGetAddressRangeState (
   IN UINTNLength
   );
 
+/**
+  This function clears memory encryption bit for the MMIO region specified by
+  PhysicalAddress and Length.
+
+  @param[in]  Cr3BaseAddress  Cr3 Base Address (if zero then use
+  current CR3)
+  @param[in]  PhysicalAddress The physical address that is the start
+  address of a MMIO region.
+  @param[in]  Length  The length of memory region
+
+  @retval RETURN_SUCCESS  The attributes were cleared for the
+  memory region.
+  @retval RETURN_INVALID_PARAMETERLength is zero.
+  @retval RETURN_UNSUPPORTED  Clearing the memory encyrption attribute
+  is not supported
+**/
+RETURN_STATUS
+EFIAPI
+InternalMemEncryptSevClearMmioPageEncMask (
+  IN  PHYSICAL_ADDRESSCr3BaseAddress,
+  IN  PHYSICAL_ADDRESSPhysicalAddress,
+  IN  UINTN   Length
+  );
 #endif
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c 
b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c
index 12a5bf495bd7..169d3118e44f 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c
@@ -111,3 +111,34 @@ MemEncryptSevGetAddressRangeState (
   //
   return MemEncryptSevAddressRangeEncrypted;
 }
+
+/**
+  This function clears memory encryption bit for the MMIO region specified by
+  BaseAddress and NumPages.
+
+  @param[in]  Cr3BaseAddress  Cr3 Base Address (if zero then use
+  current CR3)
+  @param[in]  BaseAddress The physical address that is the start
+  address of a MMIO region.
+  @param[in]  NumPagesThe number of pages from start memory
+  region.
+
+  @retval RETURN_SUCCESS  The attributes were cleared for the
+  memory region.
+  @retval RETURN_INVALID_PARAMETERNumber of pages is zero.
+  @retval RETURN_UNSUPPORTED

[edk2-devel] [PATCH v3 12/13] OvmfPkg/TpmMmioSevDecryptPei: use MemEncryptSevClearMmioPageEncMask()

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
for the Mmio address range.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Reviewed-by: Laszlo Ersek 
Signed-off-by: Brijesh Singh 
---
 OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c 
b/OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c
index df2ad623308d..570c8467a673 100644
--- a/OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c
+++ b/OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c
@@ -62,11 +62,10 @@ TpmMmioSevDecryptPeimEntryPoint (
   "%a: mapping TPM MMIO address range unencrypted\n",
   __FUNCTION__));
 
-DecryptStatus = MemEncryptSevClearPageEncMask (
+DecryptStatus = MemEncryptSevClearMmioPageEncMask (
   0,
   FixedPcdGet64 (PcdTpmBaseAddress),
-  EFI_SIZE_TO_PAGES ((UINTN) 0x5000),
-  FALSE
+  EFI_SIZE_TO_PAGES ((UINTN) 0x5000)
   );
 
 if (RETURN_ERROR (DecryptStatus)) {
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75400): https://edk2.groups.io/g/devel/message/75400
Mute This Topic: https://groups.io/mt/82943411/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 08/13] MdePkg/BaseLib: add support for RMPADJUST instruction

From: Tom Lendacky 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The RMPADJUST instruction will be used by the SEV-SNP guest to modify the
RMP permissions for a guest page. See AMD APM volume 3 for further
details.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Liming Gao 
Signed-off-by: Tom Lendacky 
Signed-off-by: Brijesh Singh 
---
 MdePkg/Library/BaseLib/BaseLib.inf|  1 +
 MdePkg/Include/Library/BaseLib.h  | 35 
 MdePkg/Include/X64/Nasm.inc   |  8 +
 MdePkg/Library/BaseLib/X64/RmpAdjust.nasm | 40 +++
 4 files changed, 84 insertions(+)
 create mode 100644 MdePkg/Library/BaseLib/X64/RmpAdjust.nasm

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 89a52f72c08a..6ccb8997b7e8 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -319,6 +319,7 @@ [Sources.X64]
   X64/DisablePaging64.nasm
   X64/Pvalidate.nasm
   X64/RdRand.nasm
+  X64/RmpAdjust.nasm
   X64/XGetBv.nasm
   X64/XSetBv.nasm
   X64/VmgExit.nasm
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index a2cd134bea9a..2452c1d92e51 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -4861,6 +4861,41 @@ AsmPvalidate (
   IN   BOOLEAN Validate,
   IN   PHYSICAL_ADDRESSAddress
   );
+
+//
+// RDX settings for RMPADJUST
+//
+#define RMPADJUST_VMPL_MAX   3
+#define RMPADJUST_VMPL_MASK  0xFF
+#define RMPADJUST_VMPL_SHIFT 0
+#define RMPADJUST_PERMISSION_MASK_MASK   0xFF
+#define RMPADJUST_PERMISSION_MASK_SHIFT  8
+#define RMPADJUST_VMSA_PAGE_BIT  BIT16
+
+/**
+  Adjusts the permissions of an SEV-SNP guest page.
+
+  Executes a RMPADJUST instruction with the register state specified by Rax,
+  Rcx, and Rdx. Returns Eax. This function is only available on X64.
+
+  The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1.
+
+  @param[in]  Rax   The value to load into RAX before executing the RMPADJUST
+instruction.
+  @param[in]  Rcx   The value to load into RCX before executing the RMPADJUST
+instruction.
+  @param[in]  Rdx   The value to load into RDX before executing the RMPADJUST
+instruction.
+
+  @return Eax
+**/
+UINT32
+EFIAPI
+AsmRmpAdjust (
+  IN  UINT64 Rax,
+  IN  UINT64 Rcx,
+  IN  UINT64 Rdx
+  );
 #endif
 
 
diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
index 528bb3385609..cfb14edc9449 100644
--- a/MdePkg/Include/X64/Nasm.inc
+++ b/MdePkg/Include/X64/Nasm.inc
@@ -41,6 +41,14 @@
 DB 0xF2, 0x0F, 0x01, 0xFF
 %endmacro
 
+;
+; Macro for the RMPADJUST instruction, defined in AMD APM volume 3.
+; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392754
+;
+%macro RMPADJUST   0
+DB 0xF3, 0x0F, 0x01, 0xFE
+%endmacro
+
 ; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.
 ; For example, to define a structure called mytype containing a longword,
 ; a word, a byte and a string of bytes, you might code
diff --git a/MdePkg/Library/BaseLib/X64/RmpAdjust.nasm 
b/MdePkg/Library/BaseLib/X64/RmpAdjust.nasm
new file mode 100644
index ..c307f64b518a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/RmpAdjust.nasm
@@ -0,0 +1,40 @@
+;-
+;
+; Copyright (c) 2021, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   RmpAdjust.Asm
+;
+; Abstract:
+;
+;   AsmRmpAdjust function
+;
+; Notes:
+;
+;-
+
+%include "Nasm.inc"
+
+SECTION .text
+
+;-
+;  UINT32
+;  EFIAPI
+;  AsmRmpAdjust (
+;IN  UINT64  Rax,
+;IN  UINT64  Rcx,
+;IN  UINT64  Rdx
+;)
+;-
+global ASM_PFX(AsmRmpAdjust)
+ASM_PFX(AsmRmpAdjust):
+  mov rax, rcx   ; Input Rax is in RCX by calling convention
+  mov rcx, rdx   ; Input Rcx is in RDX by calling convention
+  mov rdx, r8; Input Rdx is in R8  by calling convention
+
+  RMPADJUST
+
+  ; RMPADJUST returns the status in the EAX register.
+  ret
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75397): https://edk2.groups.io/g/devel/message/75397
Mute This Topic: https://groups.io/mt/82943408/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe:

[edk2-devel] [PATCH v3 06/13] MdePkg/Register/Amd: define GHCB macros for SNP AP creation

From: Tom Lendacky 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=33275

Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is enabled
in the guest VM. See the GHCB specification, Table 5 "List of Supported
Non-Automatic Events" and sections 4.1.9 and 4.3.2, for further details.

While at it, define the VMSA state save area that is required for creating
the AP. The save area format is defined in AMD APM volume 2, Table B-4
(there is a mistake in the table that defines the size of the reserved
area at offset 0xc8 as a dword, when it is actually a word). The format of
the save area segment registers is further defined in AMD APM volume 2,
sections 10 and 15.5.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Reviewed-by: Liming Gao 
Reviewed-by: Laszlo Ersek 
Signed-off-by: Tom Lendacky 
Signed-off-by: Brijesh Singh 
---
 MdePkg/Include/Register/Amd/Ghcb.h | 84 ++
 1 file changed, 84 insertions(+)

diff --git a/MdePkg/Include/Register/Amd/Ghcb.h 
b/MdePkg/Include/Register/Amd/Ghcb.h
index 029904b1c63a..8c5f46e4bb53 100644
--- a/MdePkg/Include/Register/Amd/Ghcb.h
+++ b/MdePkg/Include/Register/Amd/Ghcb.h
@@ -55,6 +55,7 @@
 #define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
 #define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
 #define SVM_EXIT_SNP_PAGE_STATE_CHANGE  0x8010ULL
+#define SVM_EXIT_SNP_AP_CREATION0x8013ULL
 #define SVM_EXIT_HYPERVISOR_FEATURES0x8000FFFDULL
 #define SVM_EXIT_UNSUPPORTED0x8000ULL
 
@@ -83,6 +84,12 @@
 #define IOIO_SEG_ES 0
 #define IOIO_SEG_DS (BIT11 | BIT10)
 
+//
+// AP Creation Information
+//
+#define SVM_VMGEXIT_SNP_AP_CREATE_ON_INIT  0
+#define SVM_VMGEXIT_SNP_AP_CREATE  1
+#define SVM_VMGEXIT_SNP_AP_DESTROY 2
 
 typedef PACKED struct {
   UINT8  Reserved1[203];
@@ -195,4 +202,81 @@ typedef struct {
   SNP_PAGE_STATE_ENTRY   Entry[SNP_PAGE_STATE_MAX_ENTRY];
 } SNP_PAGE_STATE_CHANGE_INFO;
 
+//
+// SEV-ES save area mapping structures used for SEV-SNP AP Creation.
+// Only the fields required to be set to a non-zero value are defined.
+//
+// The segment register definition is defined for processor reset/real mode
+// (as when an INIT of the vCPU is requested). Should other modes (long mode,
+// etc.) be required, then the definitions can be enhanced.
+//
+
+//
+// Segment types at processor reset, See AMD APM Volume 2, Table 14-2.
+//
+#define SEV_ES_RESET_CODE_SEGMENT_TYPE  0xA
+#define SEV_ES_RESET_DATA_SEGMENT_TYPE  0x2
+
+#define SEV_ES_RESET_LDT_TYPE   0x2
+#define SEV_ES_RESET_TSS_TYPE   0x3
+
+#pragma pack (1)
+typedef union {
+struct {
+  UINT16  Type:4;
+  UINT16  Sbit:1;
+  UINT16  Dpl:2;
+  UINT16  Present:1;
+  UINT16  Avl:1;
+  UINT16  Reserved1:1;
+  UINT16  Db:1;
+  UINT16  Granularity:1;
+} Bits;
+UINT16  Uint16;
+} SEV_ES_SEGMENT_REGISTER_ATTRIBUTES;
+
+typedef struct {
+  UINT16Selector;
+  SEV_ES_SEGMENT_REGISTER_ATTRIBUTESAttributes;
+  UINT32Limit;
+  UINT64Base;
+} SEV_ES_SEGMENT_REGISTER;
+
+typedef struct {
+  SEV_ES_SEGMENT_REGISTER  Es;
+  SEV_ES_SEGMENT_REGISTER  Cs;
+  SEV_ES_SEGMENT_REGISTER  Ss;
+  SEV_ES_SEGMENT_REGISTER  Ds;
+  SEV_ES_SEGMENT_REGISTER  Fs;
+  SEV_ES_SEGMENT_REGISTER  Gs;
+  SEV_ES_SEGMENT_REGISTER  Gdtr;
+  SEV_ES_SEGMENT_REGISTER  Ldtr;
+  SEV_ES_SEGMENT_REGISTER  Idtr;
+  SEV_ES_SEGMENT_REGISTER  Tr;
+  UINT8Reserved1[42];
+  UINT8Vmpl;
+  UINT8Reserved2[5];
+  UINT64   Efer;
+  UINT8Reserved3[112];
+  UINT64   Cr4;
+  UINT8Reserved4[8];
+  UINT64   Cr0;
+  UINT64   Dr7;
+  UINT64   Dr6;
+  UINT64   Rflags;
+  UINT64   Rip;
+  UINT8Reserved5[232];
+  UINT64   GPat;
+  UINT8Reserved6[320];
+  UINT64   SevFeatures;
+  UINT8Reserved7[48];
+  UINT64   XCr0;
+  UINT8Reserved8[24];
+  UINT32   Mxcsr;
+  UINT16   X87Ftw;
+  UINT8Reserved9[2];
+  UINT16   X87Fcw;
+} SEV_ES_SAVE_AREA;
+#pragma pack ()
+
 #endif
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75396): https://edk2.groups.io/g/devel/message/75396
Mute This Topic: https://groups.io/mt/82943407/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]

[edk2-devel] [PATCH v3 11/13] OvmfPkg/QemuFlashFvbServicesRuntimeDxe: use Mmio helper to clear enc mask

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
for the Mmio address range.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Reviewed-by: Laszlo Ersek 
Signed-off-by: Brijesh Singh 
---
 OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c | 5 ++---
 OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c  | 5 ++---
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c 
b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c
index 1f285e008372..ab40087a8408 100644
--- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c
+++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c
@@ -205,11 +205,10 @@ MarkIoMemoryRangeForRuntimeAccess (
   // memory range.
   //
   if (MemEncryptSevIsEnabled ()) {
-Status = MemEncryptSevClearPageEncMask (
+Status = MemEncryptSevClearMmioPageEncMask (
0,
BaseAddress,
-   EFI_SIZE_TO_PAGES (Length),
-   FALSE
+   EFI_SIZE_TO_PAGES (Length)
);
 ASSERT_EFI_ERROR (Status);
   }
diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c 
b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c
index 7eb80bfeffae..ea75b489c7fd 100644
--- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c
+++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c
@@ -38,11 +38,10 @@ QemuFlashBeforeProbe (
   // C-bit on flash ranges from SMM page table.
   //
 
-  Status = MemEncryptSevClearPageEncMask (
+  Status = MemEncryptSevClearMmioPageEncMask (
  0,
  BaseAddress,
- EFI_SIZE_TO_PAGES (FdBlockSize * FdBlockCount),
- FALSE
+ EFI_SIZE_TO_PAGES (FdBlockSize * FdBlockCount)
  );
   ASSERT_EFI_ERROR (Status);
 }
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75398): https://edk2.groups.io/g/devel/message/75398
Mute This Topic: https://groups.io/mt/82943409/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 07/13] MdePkg/BaseLib: add support for PVALIDATE instruction

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The PVALIDATE instruction validates or rescinds validation of a guest
page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS
bits OF, ZF, AF, PF and SF are set based on this return code. If the
instruction completed succesfully, the rFLAGS bit CF indicates if the
contents of the RMP entry were changed or not.

For more information about the instruction see AMD APM volume 3.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Reviewed-by: Liming Gao 
Reviewed-by: Laszlo Ersek 
Signed-off-by: Brijesh Singh 
---
 MdePkg/Library/BaseLib/BaseLib.inf|  1 +
 MdePkg/Include/Library/BaseLib.h  | 50 +++
 MdePkg/Include/X64/Nasm.inc   |  8 
 MdePkg/Library/BaseLib/X64/Pvalidate.nasm | 42 +++
 4 files changed, 101 insertions(+)
 create mode 100644 MdePkg/Library/BaseLib/X64/Pvalidate.nasm

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index b76f3af380ea..89a52f72c08a 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -317,6 +317,7 @@ [Sources.X64]
   X64/GccInlinePriv.c | GCC
   X64/EnableDisableInterrupts.nasm
   X64/DisablePaging64.nasm
+  X64/Pvalidate.nasm
   X64/RdRand.nasm
   X64/XGetBv.nasm
   X64/XSetBv.nasm
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 7253997a6f8c..a2cd134bea9a 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -4813,6 +4813,56 @@ SpeculationBarrier (
   VOID
   );
 
+#if defined (MDE_CPU_X64)
+//
+// The page size for the PVALIDATE instruction
+//
+typedef enum {
+  PvalidatePageSize4K = 0,
+  PvalidatePageSize2MB,
+} PVALIDATE_PAGE_SIZE;
+
+//
+// PVALIDATE Return Code.
+//
+#define PVALIDATE_RET_SUCCESS 0
+#define PVALIDATE_RET_FAIL_INPUT  1
+#define PVALIDATE_RET_SIZE_MISMATCH   6
+
+//
+// The PVALIDATE instruction did not make any changes to the RMP entry.
+//
+#define PVALIDATE_RET_NO_RMPUPDATE255
+
+/**
+ Execute a PVALIDATE instruction to validate or to rescinds validation of a 
guest
+ page's RMP entry.
+
+ The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1.
+
+ The function is available on X64.
+
+ @param[in]PageSize The page size to use.
+ @param[in]Validate If TRUE, validate the guest virtual address
+otherwise invalidate the guest virtual address.
+ @param[in]Address  The guest virtual address.
+
+ @retval PVALIDATE_RET_SUCCESSThe PVALIDATE instruction succeeded, and
+  updated the RMP entry.
+ @retval PVALIDATE_RET_NO_RMPUPDATE   The PVALIDATE instruction succeeded, but
+  did not update the RMP entry.
+ @return  Failure code from the PVALIDATE
+  instruction.
+**/
+UINT32
+EFIAPI
+AsmPvalidate (
+  IN   PVALIDATE_PAGE_SIZE PageSize,
+  IN   BOOLEAN Validate,
+  IN   PHYSICAL_ADDRESSAddress
+  );
+#endif
+
 
 #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
 ///
diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
index 527f71e9eb4d..528bb3385609 100644
--- a/MdePkg/Include/X64/Nasm.inc
+++ b/MdePkg/Include/X64/Nasm.inc
@@ -33,6 +33,14 @@
 DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8
 %endmacro
 
+;
+; Macro for the PVALIDATE instruction, defined in AMD APM volume 3.
+; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392753
+;
+%macro PVALIDATE   0
+DB 0xF2, 0x0F, 0x01, 0xFF
+%endmacro
+
 ; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.
 ; For example, to define a structure called mytype containing a longword,
 ; a word, a byte and a string of bytes, you might code
diff --git a/MdePkg/Library/BaseLib/X64/Pvalidate.nasm 
b/MdePkg/Library/BaseLib/X64/Pvalidate.nasm
new file mode 100644
index ..a7d177913405
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/Pvalidate.nasm
@@ -0,0 +1,42 @@
+;-
+;
+; Copyright (c) 2021, AMD. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;-
+
+%include "Nasm.inc"
+
+SECTION .text
+
+;-
+;  UINT32
+;  EFIAPI
+;  AsmPvalidate (
+;IN   UINT32  PageSize
+;IN   UINT32  Validate,
+;IN   UINT64  Address
+;)
+;-
+global ASM_PFX(AsmPvalidate)
+ASM_PFX(AsmPvalidate):
+  mov rax, r8
+
+

[edk2-devel] [PATCH v3 05/13] MdePkg/Register/Amd: define GHCB macro for the Page State Change

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The Page State Change NAE exit will be used by the SEV-SNP guest to
request a page state change using the GHCB protocol. See the GHCB
spec section 4.1.6 and 2.3.1 for more detail on the structure
definitions.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Liming Gao 
Reviewed-by: Erdem Aktas 
Signed-off-by: Brijesh Singh 
---
 MdePkg/Include/Register/Amd/Fam17Msr.h | 15 
 MdePkg/Include/Register/Amd/Ghcb.h | 33 ++
 2 files changed, 48 insertions(+)

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
b/MdePkg/Include/Register/Amd/Fam17Msr.h
index 542e4cdf4782..62014854d9b7 100644
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -58,6 +58,19 @@ typedef union {
 UINT64  GuestFrameNumber:52;
   } GhcbGpaRegister;
 
+  struct {
+UINT64 Function:12;
+UINT64 GuestFrameNumber:40;
+UINT64 Operation:4;
+UINT64 Reserved:8;
+  } SnpPageStateChangeRequest;
+
+  struct {
+UINT32 Function:12;
+UINT32 Reserved:20;
+UINT32 ErrorCode;
+  } SnpPageStateChangeResponse;
+
   VOID*Ghcb;
 
   UINT64  GhcbPhysicalAddress;
@@ -69,6 +82,8 @@ typedef union {
 #define GHCB_INFO_CPUID_RESPONSE5
 #define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST 18
 #define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE19
+#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST 20
+#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE21
 #define GHCB_HYPERVISOR_FEATURES_REQUEST128
 #define GHCB_HYPERVISOR_FEATURES_RESPONSE   129
 #define GHCB_INFO_TERMINATE_REQUEST 256
diff --git a/MdePkg/Include/Register/Amd/Ghcb.h 
b/MdePkg/Include/Register/Amd/Ghcb.h
index ec232ebd3807..029904b1c63a 100644
--- a/MdePkg/Include/Register/Amd/Ghcb.h
+++ b/MdePkg/Include/Register/Amd/Ghcb.h
@@ -54,6 +54,7 @@
 #define SVM_EXIT_NMI_COMPLETE   0x8003ULL
 #define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
 #define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
+#define SVM_EXIT_SNP_PAGE_STATE_CHANGE  0x8010ULL
 #define SVM_EXIT_HYPERVISOR_FEATURES0x8000FFFDULL
 #define SVM_EXIT_UNSUPPORTED0x8000ULL
 
@@ -162,4 +163,36 @@ typedef union {
 #define GHCB_HV_FEATURES_SNP_AP_CREATE
(GHCB_HV_FEATURES_SNP | BIT1)
 #define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION 
(GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)
 #define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER   
(GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)
+
+//
+// SNP Page State Change.
+//
+// Note that the PSMASH and UNSMASH operations are not supported when using 
the MSR protocol.
+//
+#define SNP_PAGE_STATE_PRIVATE  1
+#define SNP_PAGE_STATE_SHARED   2
+#define SNP_PAGE_STATE_PSMASH   3
+#define SNP_PAGE_STATE_UNSMASH  4
+
+typedef struct {
+  UINT64  CurrentPage:12;
+  UINT64  GuestFrameNumber:40;
+  UINT64  Operation:4;
+  UINT64  PageSize:1;
+  UINT64  Reserved:7;
+} SNP_PAGE_STATE_ENTRY;
+
+typedef struct {
+  UINT16 CurrentEntry;
+  UINT16 EndEntry;
+  UINT32 Reserved;
+} SNP_PAGE_STATE_HEADER;
+
+#define SNP_PAGE_STATE_MAX_ENTRY253
+
+typedef struct {
+  SNP_PAGE_STATE_HEADER  Header;
+  SNP_PAGE_STATE_ENTRY   Entry[SNP_PAGE_STATE_MAX_ENTRY];
+} SNP_PAGE_STATE_CHANGE_INFO;
+
 #endif
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75394): https://edk2.groups.io/g/devel/message/75394
Mute This Topic: https://groups.io/mt/82943405/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 03/13] MdePkg/Register/Amd: define GHCB macros for hypervisor feature detection

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Version 2 of GHCB introduces advertisement of features that are supported
by the hypervisor. See the GHCB spec section 2.2 for an additional details.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Liming Gao 
Reviewed-by: Erdem Aktas 
Signed-off-by: Brijesh Singh 
---
 MdePkg/Include/Register/Amd/Fam17Msr.h | 7 +++
 MdePkg/Include/Register/Amd/Ghcb.h | 8 
 2 files changed, 15 insertions(+)

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
b/MdePkg/Include/Register/Amd/Fam17Msr.h
index 7368ce7af02a..cdb8f588ccf8 100644
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -48,6 +48,11 @@ typedef union {
 UINT32  Reserved2:32;
   } GhcbTerminate;
 
+  struct {
+UINT64  Function:12;
+UINT64  Features:52;
+  } GhcbHypervisorFeatures;
+
   VOID*Ghcb;
 
   UINT64  GhcbPhysicalAddress;
@@ -57,6 +62,8 @@ typedef union {
 #define GHCB_INFO_SEV_INFO_GET  2
 #define GHCB_INFO_CPUID_REQUEST 4
 #define GHCB_INFO_CPUID_RESPONSE5
+#define GHCB_HYPERVISOR_FEATURES_REQUEST128
+#define GHCB_HYPERVISOR_FEATURES_RESPONSE   129
 #define GHCB_INFO_TERMINATE_REQUEST 256
 
 #define GHCB_TERMINATE_GHCB0
diff --git a/MdePkg/Include/Register/Amd/Ghcb.h 
b/MdePkg/Include/Register/Amd/Ghcb.h
index 712dc8e769c0..ec232ebd3807 100644
--- a/MdePkg/Include/Register/Amd/Ghcb.h
+++ b/MdePkg/Include/Register/Amd/Ghcb.h
@@ -54,6 +54,7 @@
 #define SVM_EXIT_NMI_COMPLETE   0x8003ULL
 #define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
 #define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
+#define SVM_EXIT_HYPERVISOR_FEATURES0x8000FFFDULL
 #define SVM_EXIT_UNSUPPORTED0x8000ULL
 
 //
@@ -154,4 +155,11 @@ typedef union {
 #define GHCB_EVENT_INJECTION_TYPE_EXCEPTION  3
 #define GHCB_EVENT_INJECTION_TYPE_SOFT_INT   4
 
+//
+// Hypervisor features
+//
+#define GHCB_HV_FEATURES_SNP  BIT0
+#define GHCB_HV_FEATURES_SNP_AP_CREATE
(GHCB_HV_FEATURES_SNP | BIT1)
+#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION 
(GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)
+#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER   
(GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)
 #endif
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75392): https://edk2.groups.io/g/devel/message/75392
Mute This Topic: https://groups.io/mt/82943402/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 00/13] Add GHCBv2 macro and helpers

This series is taken from the SNP RFC. This series defines the GHCBv2
macros and NAE events. Additionally, it also introduces a helper to
clear the page encryption mask from the Mmio region.

The series is based on the commit:
 15ee7b76891a CryptoPkg/BaseCryptLib: Fix possible uninitialized use

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 

Change since v2:
 - fix commit message for typos and add R-b

Change since v1:
 - address the review comments
 - drop the Mmio specific changes from 'remove Flush .." patch

Brijesh Singh (11):
  MdePkg/Register/Amd: expand the SEV MSR to include the SNP definition
  MdePkg/Register/Amd: realign macros with more space for future
expansion
  MdePkg/Register/Amd: define GHCB macros for hypervisor feature
detection
  MdePkg/Register/Amd: define GHCB macro for Register GPA structure
  MdePkg/Register/Amd: define GHCB macro for the Page State Change
  MdePkg/BaseLib: add support for PVALIDATE instruction
  OvmfPkg/BaseMemEncryptSevLib: introduce
MemEncryptSevClearMmioPageEncMask()
  OvmfPkg/AmdSevDxe: use MemEncryptSevClearMmioPageEncMask() to clear
EncMask
  OvmfPkg/QemuFlashFvbServicesRuntimeDxe: use Mmio helper to clear enc
mask
  OvmfPkg/TpmMmioSevDecryptPei: use MemEncryptSevClearMmioPageEncMask()
  OvmfPkg/BaseMemEncryptSevLib: remove Flush parameter

Tom Lendacky (2):
  MdePkg/Register/Amd: define GHCB macros for SNP AP creation
  MdePkg/BaseLib: add support for RMPADJUST instruction

 MdePkg/Library/BaseLib/BaseLib.inf|   2 +
 MdePkg/Include/Library/BaseLib.h  |  85 +++
 MdePkg/Include/Register/Amd/Fam17Msr.h|  46 +-
 MdePkg/Include/Register/Amd/Ghcb.h| 137 +-
 OvmfPkg/Include/Library/MemEncryptSevLib.h|  35 -
 .../BaseMemEncryptSevLib/X64/VirtualMemory.h  |  33 -
 OvmfPkg/AmdSevDxe/AmdSevDxe.c |  13 +-
 OvmfPkg/IoMmuDxe/AmdSevIoMmu.c|   6 +-
 .../Ia32/MemEncryptSevLib.c   |  41 +-
 .../X64/MemEncryptSevLib.c|  49 +--
 .../X64/PeiDxeVirtualMemory.c |  47 --
 .../X64/SecVirtualMemory.c|  38 -
 .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c |   3 +-
 OvmfPkg/PlatformPei/AmdSev.c  |   3 +-
 .../FwBlockServiceDxe.c   |   5 +-
 .../QemuFlashSmm.c|   5 +-
 .../TpmMmioSevDecryptPeim.c   |   5 +-
 MdePkg/Include/X64/Nasm.inc   |  16 ++
 MdePkg/Library/BaseLib/X64/Pvalidate.nasm |  42 ++
 MdePkg/Library/BaseLib/X64/RmpAdjust.nasm |  40 +
 20 files changed, 562 insertions(+), 89 deletions(-)
 create mode 100644 MdePkg/Library/BaseLib/X64/Pvalidate.nasm
 create mode 100644 MdePkg/Library/BaseLib/X64/RmpAdjust.nasm

-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75389): https://edk2.groups.io/g/devel/message/75389
Mute This Topic: https://groups.io/mt/82943399/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 02/13] MdePkg/Register/Amd: realign macros with more space for future expansion

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Version 2 of the GHCB spec introduces several new SNP-specific NAEs.
Unfortunately, the names for those NAEs break the alignment. Add some
white spaces so that the SNP support patches do not break the alignment.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Liming Gao 
Signed-off-by: Brijesh Singh 
---
 MdePkg/Include/Register/Amd/Fam17Msr.h | 10 +-
 MdePkg/Include/Register/Amd/Ghcb.h | 12 ++--
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
b/MdePkg/Include/Register/Amd/Fam17Msr.h
index 716d52fd508d..7368ce7af02a 100644
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -53,11 +53,11 @@ typedef union {
   UINT64  GhcbPhysicalAddress;
 } MSR_SEV_ES_GHCB_REGISTER;
 
-#define GHCB_INFO_SEV_INFO 1
-#define GHCB_INFO_SEV_INFO_GET 2
-#define GHCB_INFO_CPUID_REQUEST4
-#define GHCB_INFO_CPUID_RESPONSE   5
-#define GHCB_INFO_TERMINATE_REQUEST256
+#define GHCB_INFO_SEV_INFO  1
+#define GHCB_INFO_SEV_INFO_GET  2
+#define GHCB_INFO_CPUID_REQUEST 4
+#define GHCB_INFO_CPUID_RESPONSE5
+#define GHCB_INFO_TERMINATE_REQUEST 256
 
 #define GHCB_TERMINATE_GHCB0
 #define GHCB_TERMINATE_GHCB_GENERAL0
diff --git a/MdePkg/Include/Register/Amd/Ghcb.h 
b/MdePkg/Include/Register/Amd/Ghcb.h
index ccdb662af7a7..712dc8e769c0 100644
--- a/MdePkg/Include/Register/Amd/Ghcb.h
+++ b/MdePkg/Include/Register/Amd/Ghcb.h
@@ -49,12 +49,12 @@
 //
 // VMG Special Exit Codes
 //
-#define SVM_EXIT_MMIO_READ  0x8001ULL
-#define SVM_EXIT_MMIO_WRITE 0x8002ULL
-#define SVM_EXIT_NMI_COMPLETE   0x8003ULL
-#define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
-#define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
-#define SVM_EXIT_UNSUPPORTED0x8000ULL
+#define SVM_EXIT_MMIO_READ  0x8001ULL
+#define SVM_EXIT_MMIO_WRITE 0x8002ULL
+#define SVM_EXIT_NMI_COMPLETE   0x8003ULL
+#define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
+#define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
+#define SVM_EXIT_UNSUPPORTED0x8000ULL
 
 //
 // IOIO Exit Information
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75391): https://edk2.groups.io/g/devel/message/75391
Mute This Topic: https://groups.io/mt/82943401/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 01/13] MdePkg/Register/Amd: expand the SEV MSR to include the SNP definition

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Define the SEV-SNP MSR bits.

Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Laszlo Ersek 
Cc: Erdem Aktas 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Liming Gao 
Signed-off-by: Brijesh Singh 
---
 MdePkg/Include/Register/Amd/Fam17Msr.h | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
b/MdePkg/Include/Register/Amd/Fam17Msr.h
index e4db09c5184c..716d52fd508d 100644
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -87,7 +87,12 @@ typedef union {
 ///
 UINT32  SevEsBit:1;
 
-UINT32  Reserved:30;
+///
+/// [Bit 2] Secure Nested Paging (SevSnp) is enabled
+///
+UINT32  SevSnpBit:1;
+
+UINT32  Reserved2:29;
   } Bits;
   ///
   /// All bit fields as a 32-bit value
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75390): https://edk2.groups.io/g/devel/message/75390
Mute This Topic: https://groups.io/mt/82943400/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: 回复: [edk2-devel] GSoC 2021 Qemu OpenBoardPkg Project

2021-05-19 Thread Michael Kubacki

Thanks Liming.

Hi Kaaira,

GENERIC RESOURCES

I'm sharing some general resources in case you are not already familiar
with them:

1. https://github.com/tianocore-training/Tianocore_Training_Contents/wiki

This one is good for topics like UEFI overview, EDK II concepts, and
Minimum Platform.

2.
https://software.intel.com/content/www/us/en/develop/articles/unified-extensible-firmware-interface.html

3. https://uefi.org/learning_center/presentationsandvideos/

PROJECT-SPECIFIC RESOURCES

Since your project involves creating QEMU board within the Minimum
Platform architecture, you can start looking into:

1. QEMU - https://www.qemu.org/

I suggest you start with the OvmfPkg README -
https://github.com/tianocore/edk2/blob/master/OvmfPkg/README

2. EDK II Minimum Platform Specification -
https://edk2-docs.gitbook.io/edk-ii-minimum-platform-specification/

3. Intel FSP -
https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html

For more information about Intel FSP check out the Intel FSP External
Architecture Specification in the link above. v2.2 is currently the
latest version.

There is an open source QEMU FSP available here
https://github.com/universalpayload/fspsdk/tree/qemu_fsp_x64. You will
find the existing Minimum Platform boards use Intel FSP while OvmfPkg
does not use FSP.

Firmware is really best learned hands on. Using the links and background
info above, I suggest:

1. Read the OvmfPkg readme.
2. Build a 32-bit PEI and 64-bit DXE OVMF FW and boot it to EFI shell
using QEMU.
3. Reading through

Re: [edk2-devel] GSoC 2021 Qemu OpenBoardPkg Project

2021-05-19 Thread Oram, Isaac W

There is a variety of good basics for edk2 development starting at 
https://www.tianocore.org/.  There is getting started and training things for 
basics.  Getting started and how to contribute are key I think.  They should 
have answers for your questions on development environment and such.  

There is a page for MinPlatform here:  
https://github.com/tianocore/tianocore.github.io/wiki/Minimum-Platform-Architecture--MinPlatform,
 including links to the document.
There was a talk at OSFC 2019 (https://www.youtube.com/watch?v=x3NFbUC3hkA).
There are also talks at OCP Summits.
Navigate to https://www.opencompute.org/summit/global-summit and then Events, 
Past Events, and find Global Summit 2020 and OCP Tech Week 2020.
For 2020 Virtual Summit, https://www.youtube.com/watch?v=Cg0NavUVT3g 
For Tech Week, look for "Intel Xeon Scalable Processors MinPlatform Porting" 
event on November 10.  You have to create an account and log in to the hosting 
platform unfortunately.  I don't believe direct links are possible at this time.

Regards,
Isaac

-Original Message-
From: devel@edk2.groups.io  On Behalf Of gaoliming
Sent: Tuesday, May 18, 2021 6:06 PM
To: devel@edk2.groups.io; kaaira7...@gmail.com; Ni, Ray 
Cc: mikub...@linux.microsoft.com
Subject: 回复: [edk2-devel] GSoC 2021 Qemu OpenBoardPkg Project

Include Michael Kubacki. 

Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io  代表 KAAIRA GUPTA
> 发送时间: 2021年5月18日 22:42
> 收件人: Ray Ni ; devel@edk2.groups.io
> 主题: Re: [edk2-devel] GSoC 2021 Qemu OpenBoardPkg Project
> 
> On Tue, May 18, 2021 at 08:01:57PM +0530, Kaaira Gupta wrote:
> > Hey everyone,
> >
> > I have been selected as a student developer for the project 
> > MinPlatform Qemu OpenBoardPkg under the mentors Ray Ni and Michael Kubacki.
> Thankyou
> > for this opportunity. I have been over the major chapters of Beyond 
> > BIOS as recommended by Nate DeSimone. I want to get familiar with 
> > the code now to help me undersatnd the community practices and get 
> > my hands dirty. Where should I start? What development environment do I 
> > need?
> > How can I use this community bonding period to give me a better 
> > start for the coding phase?
> >
> > How do the mentors want me to connect with them? Can we have a meet
> to
> > discuss this project's plan to add more details? This would be very 
> > helpful for me considering I don't have prior experience with EDK2.
> 
> I noticed that the mail-id that I have used of Michael Kubacki doesn't 
> exist anymore. Please let me know how I can contact him.
> 
> >
> > Thank you,
> > Kaaira
> 
> Thanks,
> Kaaira
> 
> 
> 
> 

-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75387): https://edk2.groups.io/g/devel/message/75387
Mute This Topic: https://groups.io/mt/82942027/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v1 1/1] BaseTools: build: Set ReturnCode on POSTBUILD fail

2021-05-19 Thread Kirkendall, Garrett

Any traction on this patch?  Thank you Liming Gao for your quick response.

GARRETT KIRKENDALL
SMTS Firmware Engineer
7171 Southwest Parkway, Austin, TX 78735 USA 
AMD   facebook  |  amd.com

> -Original Message-
> From: gaoliming 
> Sent: Sunday, May 16, 2021 3:10 AM
> To: Kirkendall, Garrett ;
> devel@edk2.groups.io
> Cc: 'Bob Feng' ; 'Yuwei Chen'
> 
> Subject: 回复: [PATCH v1 1/1] BaseTools: build: Set ReturnCode on
> POSTBUILD fail
> 
> [CAUTION: External Email]
> 
> Reviewed-by: Liming Gao 
> 
> > -邮件原件-
> > 发件人: Garrett Kirkendall 
> > 发送时间: 2021年5月14日 23:02
> > 收件人: devel@edk2.groups.io
> > 抄送: Bob Feng ; Liming Gao
> > ; Yuwei Chen ;
> Garrett
> > Kirkendall 
> > 主题: [PATCH v1 1/1] BaseTools: build: Set ReturnCode on POSTBUILD fail
> >
> > When build.by POSTBUILD handling section returns other than 0, set
> > ReturnCode to POSTBUILD_ERROR so build.py exits with return code other
> > than 0.
> >
> > Fix for
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> >
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D1977data=04%7C01%7Cg
> arre
> >
> tt.kirkendall%40amd.com%7C82d1c5d0ec074f97850808d918420023%7C3dd89
> 61fe
> >
> 4884e608e11a82d994e183d%7C0%7C0%7C637567494029885033%7CUnknown
> %7CTWFpb
> >
> GZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI
> 6Mn0
> >
> %3D%7C1000sdata=tJsVIW3rhrBZiovl6Q%2FnvLUtiJCM%2BDksqSZHU
> QGaskw%3
> > Dreserved=0
> >
> > Cc: Bob Feng 
> > Cc: Liming Gao 
> > Cc: Yuwei Chen 
> >
> > Signed-off-by: Garrett Kirkendall 
> > ---
> >  BaseTools/Source/Python/build/build.py | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/BaseTools/Source/Python/build/build.py
> > b/BaseTools/Source/Python/build/build.py
> > index 037493f0b02a..3e4d83409f49 100755
> > --- a/BaseTools/Source/Python/build/build.py
> > +++ b/BaseTools/Source/Python/build/build.py
> > @@ -2757,6 +2757,7 @@ def Main():
> >  Conclusion = "Done"
> >
> >  except:
> >
> >  Conclusion = "Failed"
> >
> > +ReturnCode = POSTBUILD_ERROR
> >
> >  elif ReturnCode == ABORT_ERROR:
> >
> >  Conclusion = "Aborted"
> >
> >  else:
> >
> > --
> > 2.30.1.windows.1
> 
> 



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75386): https://edk2.groups.io/g/devel/message/75386
Mute This Topic: https://groups.io/mt/82941328/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] A plea for help

2021-05-19 Thread Bret Barkelew via groups.io

Yup, I was tired. Read the Python version all wrong.

- Bret

From: Hernandez Miramontes, Jose Miguel 

Sent: Wednesday, May 19, 2021 7:15:30 AM
To: devel@edk2.groups.io ; Bret Barkelew 
; fowler_e...@ne.bah.com 
Subject: [EXTERNAL] RE: [edk2-devel] A plea for help


So, the problem is here.

File "C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\Common\Misc.py", 
line 1638, in __init__

if ByteArray.tostring() != b'PE\0\0':



see:

https://docs.python.org/3/whatsnew/3.9.html



array.array: tostring() and fromstring() methods have been removed. They were 
aliases to tobytes() and frombytes(), deprecated since Python 3.2. (Contributed 
by Victor Stinner in bpo-38916.)



you could try python 3.8 or cherry pick this change.

https://github.com/tianocore/edk2/commit/43bec9ea3d56f3662ede78023baa2a791b66acac







Jose Miguel Hernandez Miramontes

BIOS  Engineer

jose.miguel.hernandez.miramon...@intel.com

Intel Corporation



From: devel@edk2.groups.io  On Behalf Of Bret Barkelew 
via groups.io
Sent: Wednesday, May 19, 2021 3:12 AM
To: devel@edk2.groups.io; fowler_e...@ne.bah.com
Subject: Re: [edk2-devel] A plea for help



Have you tried the latest Python 3.x?



- Bret



From: Fowler, Eric (Mondo International, LLC) via 
groups.io
Sent: Wednesday, May 19, 2021 12:41 AM
To: devel@edk2.groups.io
Subject: [EXTERNAL] [edk2-devel] A plea for help



build.py...

: error C0DE: Unknown fatal error when processing 
[c:\edk2020\district-defend\edk2\MdeModulePkg\Universal\Console\GraphicsConsoleDxe\GraphicsConsoleDxe.inf]



(Please send email to devel@edk2.groups.io for 
help, attaching following call stack trace!)



(Python 3.9.5 on win32) Traceback (most recent call last):

  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2596, in Main

MyBuild.Launch()

  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2391, in Launch

self._MultiThreadBuildPlatform()

  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2271, in _MultiThreadBuildPlatform

self.CreateAsBuiltInf()

  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2401, in CreateAsBuiltInf

Module.CreateAsBuiltInf()

  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\AutoGen\ModuleAutoGen.py",
 line 1503, in CreateAsBuiltInf

PatchList = parsePcdInfoFromMapFile(

  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\GenPatchPcdTable\GenPatchPcdTable.py",
 line 59, in parsePcdInfoFromMapFile

return _parseGeneral(lines, efifilepath)

  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\GenPatchPcdTable\GenPatchPcdTable.py",
 line 174, in _parseGeneral

efisecs = PeImageClass(efifilepath).SectionHeaderList

  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\Common\Misc.py", line 
1638, in __init__

if ByteArray.tostring() != b'PE\0\0':

AttributeError: 'array.array' object has no attribute 'tostring'





- Failed -

Build end time: 21:15:31, May.18 2021

Build total time: 00:07:11






-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75385): https://edk2.groups.io/g/devel/message/75385
Mute This Topic: https://groups.io/mt/82931279/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v1 1/1] EmbeddedPkg/libfdt: Add strmp and strncpy to libfdt_env.h

2021-05-19 Thread Abner Chang

Reviewed-by: Abner Chang 

> -Original Message-
> From: Schaefer, Daniel
> Sent: Wednesday, May 19, 2021 10:58 PM
> To: devel@edk2.groups.io
> Cc: Chang, Abner (HPS SW/FW Technologist) ; Leif
> Lindholm ; Ard Biesheuvel ;
> Anup Patel 
> Subject: [PATCH v1 1/1] EmbeddedPkg/libfdt: Add strmp and strncpy to
> libfdt_env.h
> 
> OpenSBI has started using those in v0.9. See:
> https://github.com/riscv/opensbi/blob/v0.9/lib/utils/fdt/fdt_domain.c
> 
> Cc: Abner Chang 
> Cc: Leif Lindholm 
> Cc: Ard Biesheuvel 
> Cc: Daniel Schaefer 
> Cc: Anup Patel 
> Signed-off-by: Daniel Schaefer 
> ---
>  EmbeddedPkg/Include/libfdt_env.h | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/EmbeddedPkg/Include/libfdt_env.h
> b/EmbeddedPkg/Include/libfdt_env.h
> index 7feff52bc0fb..c35ac739703c 100644
> --- a/EmbeddedPkg/Include/libfdt_env.h
> +++ b/EmbeddedPkg/Include/libfdt_env.h
> @@ -76,8 +76,16 @@ static inline size_t strnlen (const char* str, size_t 
> strsz ) {
>return AsciiStrnLenS (str, strsz);
> 
>  }
> 
> 
> 
> +static inline size_t strcmp (const char* str1, const char* str2) {
> 
> +  return AsciiStrCmp (str1, str2);
> 
> +}
> 
> +
> 
>  static inline size_t strncmp (const char* str1, const char* str2, size_t 
> strsz ) {
> 
>return AsciiStrnCmp (str1, str2, strsz);
> 
>  }
> 
> 
> 
> +static inline size_t strncpy (char* dest, const char* source, size_t 
> dest_max) {
> 
> +  return AsciiStrCpyS (dest, dest_max, source);
> 
> +}
> 
> +
> 
>  #endif /* _LIBFDT_ENV_H */
> 
> --
> 2.30.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75384): https://edk2.groups.io/g/devel/message/75384
Mute This Topic: https://groups.io/mt/82938220/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/1] EmbeddedPkg/libfdt: Add strmp and strncpy to libfdt_env.h

2021-05-19 Thread Daniel Schaefer

OpenSBI has started using those in v0.9. See:
https://github.com/riscv/opensbi/blob/v0.9/lib/utils/fdt/fdt_domain.c

Cc: Abner Chang 
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Daniel Schaefer 
Cc: Anup Patel 
Signed-off-by: Daniel Schaefer 
---
 EmbeddedPkg/Include/libfdt_env.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/EmbeddedPkg/Include/libfdt_env.h b/EmbeddedPkg/Include/libfdt_env.h
index 7feff52bc0fb..c35ac739703c 100644
--- a/EmbeddedPkg/Include/libfdt_env.h
+++ b/EmbeddedPkg/Include/libfdt_env.h
@@ -76,8 +76,16 @@ static inline size_t strnlen (const char* str, size_t strsz 
) {
   return AsciiStrnLenS (str, strsz);

 }

 

+static inline size_t strcmp (const char* str1, const char* str2) {

+  return AsciiStrCmp (str1, str2);

+}

+

 static inline size_t strncmp (const char* str1, const char* str2, size_t strsz 
) {

   return AsciiStrnCmp (str1, str2, strsz);

 }

 

+static inline size_t strncpy (char* dest, const char* source, size_t dest_max) 
{

+  return AsciiStrCpyS (dest, dest_max, source);

+}

+

 #endif /* _LIBFDT_ENV_H */

-- 
2.30.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75383): https://edk2.groups.io/g/devel/message/75383
Mute This Topic: https://groups.io/mt/82938220/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] A plea for help

2021-05-19 Thread Hernandez Miramontes, Jose Miguel

So, the problem is here.
File "C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\Common\Misc.py", 
line 1638, in __init__
if ByteArray.tostring() != b'PE\0\0':

see:
https://docs.python.org/3/whatsnew/3.9.html

array.array: tostring() and fromstring() methods have been removed. They were 
aliases to tobytes() and frombytes(), deprecated since Python 3.2. (Contributed 
by Victor Stinner in bpo-38916.)

you could try python 3.8 or cherry pick this change.
https://github.com/tianocore/edk2/commit/43bec9ea3d56f3662ede78023baa2a791b66acac



Jose Miguel Hernandez Miramontes
BIOS  Engineer
jose.miguel.hernandez.miramon...@intel.com
Intel Corporation

From: devel@edk2.groups.io  On Behalf Of Bret Barkelew 
via groups.io
Sent: Wednesday, May 19, 2021 3:12 AM
To: devel@edk2.groups.io; fowler_e...@ne.bah.com
Subject: Re: [edk2-devel] A plea for help

Have you tried the latest Python 3.x?

- Bret

From: Fowler, Eric (Mondo International, LLC) via 
groups.io
Sent: Wednesday, May 19, 2021 12:41 AM
To: devel@edk2.groups.io
Subject: [EXTERNAL] [edk2-devel] A plea for help

build.py...
: error C0DE: Unknown fatal error when processing 
[c:\edk2020\district-defend\edk2\MdeModulePkg\Universal\Console\GraphicsConsoleDxe\GraphicsConsoleDxe.inf]

(Please send email to devel@edk2.groups.io for 
help, attaching following call stack trace!)

(Python 3.9.5 on win32) Traceback (most recent call last):
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2596, in Main
MyBuild.Launch()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2391, in Launch
self._MultiThreadBuildPlatform()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2271, in _MultiThreadBuildPlatform
self.CreateAsBuiltInf()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2401, in CreateAsBuiltInf
Module.CreateAsBuiltInf()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\AutoGen\ModuleAutoGen.py",
 line 1503, in CreateAsBuiltInf
PatchList = parsePcdInfoFromMapFile(
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\GenPatchPcdTable\GenPatchPcdTable.py",
 line 59, in parsePcdInfoFromMapFile
return _parseGeneral(lines, efifilepath)
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\GenPatchPcdTable\GenPatchPcdTable.py",
 line 174, in _parseGeneral
efisecs = PeImageClass(efifilepath).SectionHeaderList
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\Common\Misc.py", line 
1638, in __init__
if ByteArray.tostring() != b'PE\0\0':
AttributeError: 'array.array' object has no attribute 'tostring'


- Failed -
Build end time: 21:15:31, May.18 2021
Build total time: 00:07:11




-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75382): https://edk2.groups.io/g/devel/message/75382
Mute This Topic: https://groups.io/mt/82931279/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH] Platform/ARM/Morello: Correct the private resources in PPTT

2021-05-19 Thread chandni cherukuri

As per ACPI specification, only the head of the list needs to be
listed as a resources by a processore node, as cache node itself
contains a link to the next level of cache.

Signed-off-by: Chandni Cherukuri 
---
 
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
 | 3 +--
 
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
 | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git 
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
 
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index 89fadbcb03..7c949812ec 100644
--- 
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ 
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -389,8 +389,7 @@ EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo = {
   // Resources private to each individual 'core instance in Cluster
   {
 { REFERENCE_TOKEN (CacheInfo[1]) }, // -> 'core's L1 I-cache in Cluster
-{ REFERENCE_TOKEN (CacheInfo[2]) }, // -> 'core's L1 D-cache in Cluster
-{ REFERENCE_TOKEN (CacheInfo[3]) }  // -> 'core's L2 cache in Cluster
+{ REFERENCE_TOKEN (CacheInfo[2]) }  // -> 'core's L1 D-cache in Cluster
   },
 
   // Resources private to the SoC
diff --git 
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
 
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
index fea4a0efd2..09ebc9a842 100644
--- 
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
+++ 
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
@@ -205,9 +205,8 @@ HandleCmObjectRefByToken (
 /** The number of resources private to 'core instance
 - L1 data cache
 - L1 instruction cache
-- L2 cache
 */
-#define CORE_RESOURCE_COUNT  3
+#define CORE_RESOURCE_COUNT  2
 
 /** The number of resources private to SoC
 - slc cache
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75381): https://edk2.groups.io/g/devel/message/75381
Mute This Topic: https://groups.io/mt/82936146/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform

2021-05-19 Thread Thomas Abraham

On 5/19/21 1:52 PM, Pranav Madhu via groups.io wrote: 
> RD-N2-Cfg1 platform is a variant of the RD-N2 platform. The platform
> is based on 8xMP1 Neoverse N2 CPUs, CMN-700 interconnect 3x3 mesh,
> multiple AXI expansion ports for I/O Coherent PCIe, Ethernet, offload
> and Arm Cortex-M7 for System Control Processor (SCP) and Manageability
> Control Processor (MCP).
> 
> The first patch in this series add Edk2 build system files and minimum
> acpi changes required to boot the platform. The second patch add ACPI
> PPTT table to describe the CPU and cache topology. The third patch in
> this series enable idle state support (ACPI LPI) and the fourth patch
> enables ACPI CPPC support to support the OS to scale CPU performance.
> The last patch in this series adds SMBIOS support.
> 
> This patch series should be applied on top of the patch series
> https://edk2.groups.io/g/devel/message/75277
> 
> Link to github branch with the patches in this series -
> https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rdn2cfg1-initial-
> support
> 
> Aditya Angadi (1):
>   Platform/Sgi: Add initial support for RD-N2-Cfg1 platform
> 
> Pranav Madhu (5):
>   Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform
>   Platform/Sgi: Low Power Idle states for RD-N2-Cfg1
>   Platform/Sgi: ACPI CPPC support for RD-N2-Cfg1
>   Platform/Sgi: Define RD-N2-Cfg1 platform id values
>   Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1

For this series:
Reviewed-by: Thomas Abraham 

[...]


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75380): https://edk2.groups.io/g/devel/message/75380
Mute This Topic: https://groups.io/mt/82931741/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [edk2-platforms][PATCH V3 00/11] Add SMBIOS tables for Arm's Reference Design platforms

2021-05-19 Thread Thomas Abraham

On 5/18/21 10:03 PM, Pranav Madhu via groups.io wrote:
> Changes since V2:
> - Addressed comments from Sami
> - Picked up Sami's reviewed-by tags.
>
> Changes since V1:
> - Rebase the patches on top of latest master branch
>
> SMBIOS provides basic hardware and firmware configuration information
> through table-driven data structure. This patch series adds SMBIOS
> support for Arm's SGI/RD platforms.
>
> The first patch in this series defines platform-id values for the
> RD-N2 platform library header. The second patch add SgiGetProductId API,
> which is used by the SMBIOS driver to distinguish between the platforms,
> and install the right table. The third patch in this series adds SMBIOS
> driver support that allows for installation of multiple SMBIOS tables.
> And subsequent patches in this series add SMBIOS tables, which are
> mandatory as per Arm serverready SBBR specification.
>
> Link to github branch with the patches in this series -
> https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_smbios
>
> Pranav Madhu (11):
>   Platform/Sgi: Define RD-N2 platform id values
>   Platform/Sgi: Add GetProductId API for SGI/RD Platforms
>   Platform/Sgi: Add Initial SMBIOS support
>   Platform/Sgi: Add SMBIOS Type1 Table
>   Platform/Sgi: Add SMBIOS Type3 Table
>   Platform/Sgi: Add SMBIOS Type4 Table
>   Platform/Sgi: Add SMBIOS Type7 Table
>   Platform/Sgi: Add SMBIOS Type16 Table
>   Platform/Sgi: Add SMBIOS Type17 Table
>   Platform/Sgi: Add SMBIOS Type19 Table
>   Platform/Sgi: Add SMBIOS Type32 Table

For this series:
Reviewed-by: Thomas Abraham 

[...]
IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75379): https://edk2.groups.io/g/devel/message/75379
Mute This Topic: https://groups.io/mt/82916150/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for 32bit arm machines

2021-05-19 Thread Sami Mujawar


Hi Etienn,

This patch looks good to me.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar

On 19/05/2021 08:14 AM, Etienne Carriere wrote:

This change allows to build StandaloneMmPkg components for 32bit Arm
StandaloneMm firmware.

This change mainly moves AArch64/ source files to Arm/ side directory
for several components:  StandaloneMmCpu, StandaloneMmCoreEntryPoint
and StandaloneMmMemLib. The source file is built for both 32b and 64b
Arm targets.

Signed-off-by: Etienne Carriere 
---
Changes since v3:
- Fix BuildOptions.ARM in StandaloneMmPkg.
- Remove Cc tags.

No change since v2

Changes since v1:
- ARM_SMC_ID_MM_COMMUNICATE 32b/64b agnostic helper ID is defined
   in ArmStdSmc.h (see 1st commit in this series) instead of being
   local to EventHandle.c.
- Fix void occurrence to VOID.
- Fix path in StandaloneMmPkg/StandaloneMmPkg.dsc
---
  StandaloneMmPkg/Core/StandaloneMmCore.inf 
   |  2 +-
  StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/EventHandle.c   
   |  5 +++--
  StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.c   
   |  2 +-
  StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.h   
   |  0
  StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.inf 
   |  0
  StandaloneMmPkg/Include/Library/{AArch64 => Arm}/StandaloneMmCoreEntryPoint.h 
   |  0
  StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => 
Arm}/CreateHobList.c  |  2 +-
  StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => 
Arm}/SetPermissions.c |  2 +-
  StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => 
Arm}/StandaloneMmCoreEntryPoint.c | 16 
  
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
| 14 +++---
  StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => 
Arm}/StandaloneMmCoreHobLib.c |  0
  StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => 
Arm}/StandaloneMmCoreHobLibInternal.c |  0
  StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf 
   |  8 
  StandaloneMmPkg/Library/StandaloneMmMemLib/{AArch64/StandaloneMmMemLibInternal.c 
=> ArmStandaloneMmMemLibInternal.c} |  9 -
  StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf 
   |  6 +++---
  StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf 
   |  2 +-
  StandaloneMmPkg/StandaloneMmPkg.dsc   
   | 12 
  17 files changed, 46 insertions(+), 34 deletions(-)

diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf 
b/StandaloneMmPkg/Core/StandaloneMmCore.inf
index 87bf6e9440..56042b7b39 100644
--- a/StandaloneMmPkg/Core/StandaloneMmCore.inf
+++ b/StandaloneMmPkg/Core/StandaloneMmCore.inf
@@ -17,7 +17,7 @@
PI_SPECIFICATION_VERSION   = 0x00010032
ENTRY_POINT= StandaloneMmMain
  
-#  VALID_ARCHITECTURES   = IA32 X64 AARCH64

+#  VALID_ARCHITECTURES   = IA32 X64 AARCH64 ARM
  
  [Sources]

StandaloneMmCore.c
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c 
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
similarity index 95%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 63fbe26642..165d696f99 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -2,6 +2,7 @@
  
Copyright (c) 2016 HP Development Company, L.P.

Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+  Copyright (c) 2021, Linaro Limited
  
SPDX-License-Identifier: BSD-2-Clause-Patent
  
@@ -92,8 +93,8 @@ PiMmStandaloneArmTfCpuDriverEntry (

// receipt of a synchronous MM request. Use the Event ID to distinguish
// between synchronous and asynchronous events.
//
-  if ((ARM_SMC_ID_MM_COMMUNICATE_AARCH64 != EventId) &&
-  (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 != EventId)) {
+  if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
+  (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId)) {
  DEBUG ((DEBUG_INFO, "UnRecognized Event - 0x%x\n", EventId));
  return EFI_INVALID_PARAMETER;
}
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c 
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c

Re: [edk2-devel] [edk2-platforms][PATCH v2 03/35] CometlakeOpenBoardPkg/PeiPolicyUpdateLib: Add missing GUID to INF

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: mikub...@linux.microsoft.com 
> Sent: Wednesday, May 19, 2021 11:59 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Chaganty, Rangasai V
> ; Kethi Reddy, Deepika
> ; Esakkithevar, Kathappan
> 
> Subject: [edk2-platforms][PATCH v2 03/35]
> CometlakeOpenBoardPkg/PeiPolicyUpdateLib: Add missing GUID to INF
> 
> From: Michael Kubacki 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
> 
> gEfiMemoryTypeInformationGuid is used in PeiSaPolicyUpdatePreMem.c but not
> in the [Guids] section in PeiPolicyUpdateLib.inf.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Rangasai V Chaganty 
> Cc: Deepika Kethi Reddy 
> Cc: Kathappan Esakkithevar 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/Pei
> PolicyUpdateLib.inf | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P
> eiPolicyUpdateLib.inf
> b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P
> eiPolicyUpdateLib.inf
> index fd51e2b8c40b..5213253f7313 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P
> eiPolicyUpdateLib.inf
> +++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdat
> +++ eLib/PeiPolicyUpdateLib.inf
> @@ -270,3 +270,4 @@ [Ppis]
>  [Guids]
>gTianoLogoGuid## CONSUMES
>gSiConfigGuid ## CONSUMES
> +  gEfiMemoryTypeInformationGuid ## PRODUCES
> --
> 2.28.0.windows.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75377): https://edk2.groups.io/g/devel/message/75377
Mute This Topic: https://groups.io/mt/82929213/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [edk2-platforms][PATCH v2 01/35] CometlakeOpenBoardPkg: Remove redundant IntelSiliconPkg.dec entry

Reviewed-by: Chasel Chiu 

> -Original Message-
> From: mikub...@linux.microsoft.com 
> Sent: Wednesday, May 19, 2021 11:59 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Chaganty, Rangasai V
> ; Kethi Reddy, Deepika
> ; Esakkithevar, Kathappan
> 
> Subject: [edk2-platforms][PATCH v2 01/35] CometlakeOpenBoardPkg: Remove
> redundant IntelSiliconPkg.dec entry
> 
> From: Michael Kubacki 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
> 
> Removes extra IntelSiliconPkg.dec entry in PeiPolicyUpdateLib.inf.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Rangasai V Chaganty 
> Cc: Deepika Kethi Reddy 
> Cc: Kathappan Esakkithevar 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/Pei
> PolicyUpdateLib.inf | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P
> eiPolicyUpdateLib.inf
> b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P
> eiPolicyUpdateLib.inf
> index 014967c7f65a..fd51e2b8c40b 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P
> eiPolicyUpdateLib.inf
> +++
> b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P
> eiPolicyUpdateLib.inf
> @@ -52,7 +52,6 @@ [Packages]
>SecurityPkg/SecurityPkg.dec
>IntelSiliconPkg/IntelSiliconPkg.dec
>MinPlatformPkg/MinPlatformPkg.dec
> -  IntelSiliconPkg/IntelSiliconPkg.dec
> 
>  [FixedPcd]
>gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
> --
> 2.28.0.windows.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75376): https://edk2.groups.io/g/devel/message/75376
Mute This Topic: https://groups.io/mt/82929204/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [edk2-platforms][PATCH v2 20/35] CometlakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib



Reviewed-by: Chasel Chiu 


> -Original Message-
> From: mikub...@linux.microsoft.com 
> Sent: Wednesday, May 19, 2021 12:00 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Chaganty, Rangasai V
> ; Kethi Reddy, Deepika
> ; Esakkithevar, Kathappan
> 
> Subject: [edk2-platforms][PATCH v2 20/35] CometlakeOpenBoardPkg: Update
> SpiFvbService & SpiFlashCommonLib
> 
> From: Michael Kubacki 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
> 
> Updates CometlakeOpenBoardPkg to use the SmmSpiFlashCommonLib instance
> in IntelSiliconPkg and the SpiFvbServiceSmm driver in IntelSiliconPkg.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Rangasai V Chaganty 
> Cc: Deepika Kethi Reddy 
> Cc: Kathappan Esakkithevar 
> Signed-off-by: Michael Kubacki 
> ---
>  Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc |
> 7 +--
> Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf |
> 2 +-
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
> index 44a1bd54d6e9..316100e9a599 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.ds
> +++ c
> @@ -254,7 +254,7 @@ [LibraryClasses.X64.DXE_SMM_DRIVER]
>###
># Silicon Initialization Package
>###
> -
> SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCom
> monLib/SmmSpiFlashCommonLib.inf
> +
> +
> SpiFlashCommonLib|IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiF
> + lashCommonLib.inf
> 
>###
># Platform Package
> @@ -401,6 +401,10 @@ [Components.X64]
>$(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
>$(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
> 
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +  IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +!endif
> +
>###
># Platform Package
>###
> @@ -421,7 +425,6 @@ [Components.X64]
> 
>  !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> 
> -  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
>$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> 
>$(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
> index 6397d80d3895..e341285f4b1a 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
> +++
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fd
> +++ f
> @@ -407,7 +407,7 @@ [FV.FvOsBootUncompact]  !if
> gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE  INF
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
>  INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> -INF  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +INF  IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> 
>  INF  $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
>  INF  $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
> --
> 2.28.0.windows.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75375): https://edk2.groups.io/g/devel/message/75375
Mute This Topic: https://groups.io/mt/82929229/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [edk2-platforms][PATCH v2 24/35] WhiskeylakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib



Reviewed-by: Chasel Chiu 

> -Original Message-
> From: mikub...@linux.microsoft.com 
> Sent: Wednesday, May 19, 2021 12:00 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> 
> Subject: [edk2-platforms][PATCH v2 24/35] WhiskeylakeOpenBoardPkg: Update
> SpiFvbService & SpiFlashCommonLib
> 
> From: Michael Kubacki 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
> 
> Updates WhiskeylakeOpenBoardPkg to use the SmmSpiFlashCommonLib
> instance in IntelSiliconPkg and the SpiFvbServiceSmm driver in 
> IntelSiliconPkg.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Signed-off-by: Michael Kubacki 
> ---
>  Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc|
> 7 +--
>  Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf|
> 2 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.ds
> c | 7 +--
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fd
> f | 2 +-
>  4 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> index ee2aedd978e0..e9c1751df9ba 100644
> --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> @@ -254,7 +254,7 @@ [LibraryClasses.X64.DXE_SMM_DRIVER]
>###
># Silicon Initialization Package
>###
> -
> SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCom
> monLib/SmmSpiFlashCommonLib.inf
> +
> +
> SpiFlashCommonLib|IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiF
> + lashCommonLib.inf
> 
>###
># Platform Package
> @@ -395,6 +395,10 @@ [Components.X64]
>$(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
>$(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
> 
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +  IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +!endif
> +
>###
># Platform Package
>###
> @@ -415,7 +419,6 @@ [Components.X64]
> 
>  !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> 
> -  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
>$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> 
>$(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> index 8aea5aa475a0..ae0ba27c1f34 100644
> --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> @@ -413,7 +413,7 @@ [FV.FvOsBootUncompact]  !if
> gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE  INF
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
>  INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> -INF  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +INF  IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> 
>  INF  $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
>  INF  $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> dsc
> index b69cc8deb0a0..e3cf99639620 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk
> +++ g.dsc
> @@ -254,7 +254,7 @@ [LibraryClasses.X64.DXE_SMM_DRIVER]
>###
># Silicon Initialization Package
>###
> -
> SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCom
> monLib/SmmSpiFlashCommonLib.inf
> +
> +
> SpiFlashCommonLib|IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiF
> + lashCommonLib.inf
> 
>###
># Platform Package
> @@ -401,6 +401,10 @@ [Components.X64]
>$(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
>$(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
> 
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +  IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +!endif
> +
>###
># Platform Package
>###
> @@ -421,7 +425,6 @@ [Components.X64]
> 
>  !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> 
> -  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
>$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> 
>

Re: [edk2-devel] [edk2-platforms][PATCH v2 25/35] MinPlatformPkg: Remove SpiFvbService modules



Reviewed-by: Chasel Chiu 

> -Original Message-
> From: mikub...@linux.microsoft.com 
> Sent: Wednesday, May 19, 2021 12:00 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Liming Gao ;
> Dong, Eric 
> Subject: [edk2-platforms][PATCH v2 25/35] MinPlatformPkg: Remove
> SpiFvbService modules
> 
> From: Michael Kubacki 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
> 
> SpiFvbServiceSmm and SpiFvbServiceStandaloneMm have moved to
> IntelSiliconPkg.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Eric Dong 
> Signed-off-by: Michael Kubacki 
> ---
>  Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/FvbInfo.c  
>|  94 -
> -
>  Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceCommon.c
> | 903 
>  Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceMm.c
> | 271 --
> 
> Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceStandaloneM
> m.c   |  32 -
> 
> Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceTraditionalM
> m.c  |  32 -
>  Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceCommon.h
> | 158 
>  Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceMm.h
> |  22 -
>  Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> |  68 --
> 
> Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceStandaloneM
> m.inf |  67 --
>  Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc 
>|   2 -
>  10 files changed, 1649 deletions(-)
> 
> diff --git a/Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/FvbInfo.c
> b/Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/FvbInfo.c
> deleted file mode 100644
> index 7f2678fa9e5a..
> --- a/Platform/Intel/MinPlatformPkg/Flash/SpiFvbService/FvbInfo.c
> +++ /dev/null
> @@ -1,94 +0,0 @@
> -/**@file
> -  Defines data structure that is the volume header found.
> -  These data is intent to decouple FVB driver with FV header.
> -
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "SpiFvbServiceCommon.h"
> -
> -#define FIRMWARE_BLOCK_SIZE 0x1
> -#define FVB_MEDIA_BLOCK_SIZEFIRMWARE_BLOCK_SIZE
> -
> -#define NV_STORAGE_BASE_ADDRESS
> FixedPcdGet32(PcdFlashNvStorageVariableBase)
> -#define SYSTEM_NV_BLOCK_NUM
> ((FixedPcdGet32(PcdFlashNvStorageVariableSize)+
> FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) +
> FixedPcdGet32(PcdFlashNvStorageFtwSpareSize))/ FVB_MEDIA_BLOCK_SIZE)
> -
> -typedef struct {
> -  EFI_PHYSICAL_ADDRESSBaseAddress;
> -  EFI_FIRMWARE_VOLUME_HEADER  FvbInfo;
> -  EFI_FV_BLOCK_MAP_ENTRY  End[1];
> -} EFI_FVB2_MEDIA_INFO;
> -
> -//
> -// This data structure contains a template of all correct FV headers, which 
> is
> used to restore
> -// Fv header if it's corrupted.
> -//
> -EFI_FVB2_MEDIA_INFO mPlatformFvbMediaInfo[] = {
> -  //
> -  // Systen NvStorage FVB
> -  //
> -  {
> -NV_STORAGE_BASE_ADDRESS,
> -{
> -  {0,}, //ZeroVector[16]
> -  EFI_SYSTEM_NV_DATA_FV_GUID,
> -  FVB_MEDIA_BLOCK_SIZE * SYSTEM_NV_BLOCK_NUM,
> -  EFI_FVH_SIGNATURE,
> -  0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details 
> on
> EFI_FVB_ATTRIBUTES_2
> -  sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof
> (EFI_FV_BLOCK_MAP_ENTRY),
> -  0,//CheckSum which will be calucated dynamically.
> -  0,//ExtHeaderOffset
> -  {0,}, //Reserved[1]
> -  2,//Revision
> -  {
> -{
> -  SYSTEM_NV_BLOCK_NUM,
> -  FVB_MEDIA_BLOCK_SIZE,
> -}
> -  }
> -},
> -{
> -  {
> -0,
> -0
> -  }
> -}
> -  }
> -};
> -
> -EFI_STATUS
> -GetFvbInfo (
> -  IN  EFI_PHYSICAL_ADDRESS FvBaseAddress,
> -  OUT EFI_FIRMWARE_VOLUME_HEADER   **FvbInfo
> -  )
> -{
> -  UINTN   Index;
> -  EFI_FIRMWARE_VOLUME_HEADER  *FvHeader;
> -
> -  for (Index = 0; Index < sizeof (mPlatformFvbMediaInfo) / sizeof
> (EFI_FVB2_MEDIA_INFO); Index++) {
> -if (mPlatformFvbMediaInfo[Index].BaseAddress == FvBaseAddress) {
> -  FvHeader = [Index].FvbInfo;
> -
> -  //
> -  // Update the checksum value of FV header.
> -  //
> -  FvHeader->Checksum = CalculateCheckSum16 ( (UINT16 *) FvHeader,
> FvHeader->HeaderLength);
> -
> -  *FvbInfo = FvHeader;
> -
> -  DEBUG ((DEBUG_INFO, "BaseAddr: 0x%lx \n", FvBaseAddress));
> -  DEBUG ((DEBUG_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength));
> -  DEBUG ((DEBUG_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)-
> >HeaderLength));
> -  DEBUG ((DEBUG_INFO, "Header Checksum: 0x%X\n", (*FvbInfo)-
> >Checksum));
> -  DEBUG ((DEBUG_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n", (*FvbInfo)-
> >BlockMap[0].NumBlocks));
> -  DEBUG ((DEBUG_INFO, "FvBlockMap[0].BlockLength: 0x%x \n", (*FvbInfo)-
> >BlockMap[0].Length));
> -  DEBUG ((DEBUG_INFO,

Re: [edk2-devel] [edk2-platforms][PATCH v2 21/35] KabylakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib



Reviewed-by: Chasel Chiu 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Michael
> Kubacki
> Sent: Wednesday, May 19, 2021 12:00 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Jeremy Soller 
> Subject: [edk2-devel] [edk2-platforms][PATCH v2 21/35]
> KabylakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib
> 
> From: Michael Kubacki 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
> 
> Updates KabylakeOpenBoardPkg to use the SmmSpiFlashCommonLib instance in
> IntelSiliconPkg and the SpiFvbServiceSmm driver in IntelSiliconPkg.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Jeremy Soller 
> Signed-off-by: Michael Kubacki 
> ---
>  Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc   | 7
> +--
>  Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf   | 2 +-
>  Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 7
> +--
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 2 +-
>  4 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> index 302cb679b5eb..89be744a9038 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> @@ -228,7 +228,7 @@ [LibraryClasses.X64.DXE_SMM_DRIVER]
>###
># Silicon Initialization Package
>###
> -
> SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCom
> monLib/SmmSpiFlashCommonLib.inf
> +
> +
> SpiFlashCommonLib|IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiF
> + lashCommonLib.inf
> 
>###
># Platform Package
> @@ -377,6 +377,10 @@ [Components.X64]
>IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
>$(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
> 
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +  IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +!endif
> +
>###
># Platform Package
>###
> @@ -393,7 +397,6 @@ [Components.X64]
> 
>  !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> 
> -  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
>$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> 
>$(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> index 39432d21b8b5..239b6b720a6a 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> @@ -401,7 +401,7 @@ [FV.FvOsBootUncompact]  !if
> gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE  INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
>  INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> -INF  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +INF  IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> 
>  INF  $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
>  INF  $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> index 8523ab3f4fc1..f29393579c06 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> @@ -268,7 +268,7 @@ [LibraryClasses.X64.DXE_SMM_DRIVER]
>###
># Silicon Initialization Package
>###
> -
> SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCom
> monLib/SmmSpiFlashCommonLib.inf
> +
> +
> SpiFlashCommonLib|IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiF
> + lashCommonLib.inf
> 
>###
># Platform Package
> @@ -456,6 +456,10 @@ [Components.X64]
>IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
>$(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
> 
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +  IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +!endif
> +
>###
># Platform Package
>###
> @@ -472,7 +476,6 @@ [Components.X64]
> 
>  !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> 
> -  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
>$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> 
>

Re: [edk2-devel] [edk2-platforms][PATCH v2 30/35] MinPlatformPkg: Remove SpiFlashCommonLibNull



Reviewed-by: Chasel Chiu 


> -Original Message-
> From: mikub...@linux.microsoft.com 
> Sent: Wednesday, May 19, 2021 12:00 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Liming Gao ;
> Dong, Eric 
> Subject: [edk2-platforms][PATCH v2 30/35] MinPlatformPkg: Remove
> SpiFlashCommonLibNull
> 
> From: Michael Kubacki 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
> 
> The library instance has moved to IntelSiliconPkg.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Eric Dong 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFlashC
> ommonLibNull.c   | 101 
> 
> Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFlashC
> ommonLibNull.inf |  29 --
>  Platform/Intel/MinPlatformPkg/Include/Library/SpiFlashCommonLib.h
> |  98 ---
>  Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec 
>|
> 2 -
>  Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc 
>|
> 4 -
>  5 files changed, 234 deletions(-)
> 
> diff --git
> a/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFlas
> hCommonLibNull.c
> b/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFlas
> hCommonLibNull.c
> deleted file mode 100644
> index 403b16a1b421..
> ---
> a/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFlas
> hCommonLibNull.c
> +++ /dev/null
> @@ -1,101 +0,0 @@
> -/** @file
> -  Null Library instance of SPI Flash Common Library Class
> -
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include 
> -#include 
> -
> -/**
> -  Enable block protection on the Serial Flash device.
> -
> -  @retval EFI_SUCCESS   Opertion is successful.
> -  @retval EFI_DEVICE_ERROR  If there is any device errors.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SpiFlashLock (
> -  VOID
> -  )
> -{
> -  return EFI_SUCCESS;
> -}
> -
> -/**
> -  Read NumBytes bytes of data from the address specified by
> -  PAddress into Buffer.
> -
> -  @param[in]  Address   The starting physical address of the read.
> -  @param[in,out]  NumBytes  On input, the number of bytes to read. On
> output, the number
> -of bytes actually read.
> -  @param[out] BufferThe destination data buffer for the read.
> -
> -  @retval EFI_SUCCESS   Opertion is successful.
> -  @retval EFI_DEVICE_ERROR  If there is any device errors.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SpiFlashRead (
> -  IN UINTNAddress,
> -  IN OUT UINT32   *NumBytes,
> - OUT UINT8*Buffer
> -  )
> -{
> -  ASSERT(FALSE);
> -  return EFI_SUCCESS;
> -}
> -
> -/**
> -  Write NumBytes bytes of data from Buffer to the address specified by
> -  PAddresss.
> -
> -  @param[in]  Address The starting physical address of the write.
> -  @param[in,out]  NumBytesOn input, the number of bytes to write. On
> output,
> -  the actual number of bytes written.
> -  @param[in]  Buffer  The source data buffer for the write.
> -
> -  @retval EFI_SUCCESS   Opertion is successful.
> -  @retval EFI_DEVICE_ERROR  If there is any device errors.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SpiFlashWrite (
> -  IN UINTN  Address,
> -  IN OUT UINT32 *NumBytes,
> -  IN UINT8  *Buffer
> -  )
> -{
> -  ASSERT(FALSE);
> -  return EFI_SUCCESS;
> -}
> -
> -/**
> -  Erase the block starting at Address.
> -
> -  @param[in]  Address The starting physical address of the block to 
> be
> erased.
> -  This library assume that caller garantee that 
> the PAddress
> -  is at the starting address of this block.
> -  @param[in]  NumBytesOn input, the number of bytes of the logical 
> block
> to be erased.
> -  On output, the actual number of bytes erased.
> -
> -  @retval EFI_SUCCESS.  Opertion is successful.
> -  @retval EFI_DEVICE_ERROR  If there is any device errors.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SpiFlashBlockErase (
> -  INUINTN Address,
> -  INUINTN *NumBytes
> -  )
> -{
> -  ASSERT(FALSE);
> -  return EFI_SUCCESS;
> -}
> -
> diff --git
> a/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFlas
> hCommonLibNull.inf
> b/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFlas
> hCommonLibNull.inf
> deleted file mode 100644
> index 75ef1cb921df..
> ---
> a/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFlas
> hCommonLibNull.inf
> +++

Re: [edk2-devel] [edk2-platforms][PATCH v2 31/35] KabylakeOpenBoardPkg/PeiSerialPortLibSpiFlash: Add IntelSiliconPkg.dec



Reviewed-by: Chasel Chiu 

> -Original Message-
> From: mikub...@linux.microsoft.com 
> Sent: Wednesday, May 19, 2021 12:00 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> 
> Subject: [edk2-platforms][PATCH v2 31/35]
> KabylakeOpenBoardPkg/PeiSerialPortLibSpiFlash: Add IntelSiliconPkg.dec
> 
> From: Michael Kubacki 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
> 
> This library now uses gPchSpiPpiGuid from IntelSiliconPkg.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSeria
> lPortLibSpiFlash.inf | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSe
> rialPortLibSpiFlash.inf
> b/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSe
> rialPortLibSpiFlash.inf
> index 31518fb40ba7..b959cd1f4612 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSe
> rialPortLibSpiFlash.inf
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSe
> rialPortLibSpiFlash.inf
> @@ -32,6 +32,7 @@ [Packages]
>MdePkg/MdePkg.dec
>MdeModulePkg/MdeModulePkg.dec
>MinPlatformPkg/MinPlatformPkg.dec
> +  IntelSiliconPkg/IntelSiliconPkg.dec
>KabylakeSiliconPkg/SiPkg.dec
>KabylakeOpenBoardPkg/OpenBoardPkg.dec
> 
> --
> 2.28.0.windows.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75370): https://edk2.groups.io/g/devel/message/75370
Mute This Topic: https://groups.io/mt/82929241/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [edk2-platforms][PATCH v2 33/35] KabylakeSiliconPkg: Remove PCH SPI PPI and Protocol from package



Reviewed-by: Chasel Chiu 

> -Original Message-
> From: mikub...@linux.microsoft.com 
> Sent: Wednesday, May 19, 2021 12:00 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Chaganty, Rangasai V
> 
> Subject: [edk2-platforms][PATCH v2 33/35] KabylakeSiliconPkg: Remove PCH SPI
> PPI and Protocol from package
> 
> From: Michael Kubacki 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
> 
> The following PPI and Protocols have moved to IntelSiliconPkg. The remaining
> definitions in KabylakeSiliconPkg are removed and libs modules that need to
> reference IntelSiliconPkg are updated.
> 
> 1. gPchSpiProtocolGuid
> 2. gPchSmmSpiProtocolGuid
> 3. gPchSpiPpiGuid
> 
> Cc: Chasel Chiu 
> Cc: Sai Chaganty 
> Signed-off-by: Michael Kubacki 
> Reviewed-by: Chasel Chiu 
> ---
>  Silicon/Intel/KabylakeSiliconPkg/Hsti/Dxe/HstiSiliconDxe.inf |   3 +-
>  Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h   |  26 --
>  Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h  | 293 
> --
> --
>  Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf |   1 +
>  Silicon/Intel/KabylakeSiliconPkg/Pch/Spi/Smm/PchSpiSmm.inf   |   1 +
>  Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec   |   3 -
>  6 files changed, 4 insertions(+), 323 deletions(-)
> 
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Hsti/Dxe/HstiSiliconDxe.inf
> b/Silicon/Intel/KabylakeSiliconPkg/Hsti/Dxe/HstiSiliconDxe.inf
> index 52e3b6ceba3e..bd12fa691d40 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Hsti/Dxe/HstiSiliconDxe.inf
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Hsti/Dxe/HstiSiliconDxe.inf
> @@ -46,6 +46,7 @@ [Sources]
>  [Packages]
>MdePkg/MdePkg.dec
>UefiCpuPkg/UefiCpuPkg.dec
> +  IntelSiliconPkg/IntelSiliconPkg.dec
>KabylakeSiliconPkg/SiPkg.dec
>SecurityPkg/SecurityPkg.dec
> 
> @@ -92,7 +93,7 @@ [Protocols]
>gEfiMpServiceProtocolGuid  ## CONSUMES
>gDxeSiPolicyProtocolGuid   ## CONSUMES
>gHstiPublishCompleteProtocolGuid   ## PRODUCES
> -
> +
>  [FixedPcd]
>gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1
>gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h
> deleted file mode 100644
> index e11f82edcaea..
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -/** @file
> -  This file defines the PCH SPI PPI which implements the
> -  Intel(R) PCH SPI Host Controller Compatibility Interface.
> -
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _PCH_SPI_PPI_H_
> -#define _PCH_SPI_PPI_H_
> -
> -#include 
> -
> -//
> -// Extern the GUID for PPI users.
> -//
> -extern EFI_GUID   gPchSpiPpiGuid;
> -
> -/**
> -  Reuse the PCH_SPI_PROTOCOL definitions
> -  This is possible becaues the PPI implementation does not rely on a 
> PeiService
> pointer,
> -  as it uses EDKII Glue Lib to do IO accesses -**/ -typedef PCH_SPI_PROTOCOL
> PCH_SPI_PPI;
> -
> -#endif
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h
> deleted file mode 100644
> index 8c66e5063fa9..
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h
> +++ /dev/null
> @@ -1,293 +0,0 @@
> -/** @file
> -  This file defines the PCH SPI Protocol which implements the
> -  Intel(R) PCH SPI Host Controller Compatibility Interface.
> -
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> -SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef _PCH_SPI_PROTOCOL_H_
> -#define _PCH_SPI_PROTOCOL_H_
> -
> -//
> -// Extern the GUID for protocol users.
> -//
> -extern EFI_GUID   gPchSpiProtocolGuid;
> -extern EFI_GUID   gPchSmmSpiProtocolGuid;
> -
> -//
> -// Forward reference for ANSI C compatibility -// -typedef struct
> _PCH_SPI_PROTOCOL  PCH_SPI_PROTOCOL;
> -
> -//
> -// SPI protocol data structures and definitions -//
> -
> -/**
> -  Flash Region Type
> -**/
> -typedef enum {
> -  FlashRegionDescriptor,
> -  FlashRegionBios,
> -  FlashRegionMe,
> -  FlashRegionGbE,
> -  FlashRegionPlatformData,
> -  FlashRegionDer,
> -  FlashRegionAll,
> -  FlashRegionMax
> -} FLASH_REGION_TYPE;
> -
> -//
> -// Protocol member functions
> -//
> -
> -/**
> -  Read data from the flash part.
> -
> -  @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
> -  @param[in] FlashRegionType  The Flash Region type for flash cycle 
> which is
> listed in the Descriptor.
> -  @param[in] Address  The Flash Linear Address must fall within 
> a region
> for which BIOS has access permissions.
> -  @param[in] ByteCountNumber of bytes in the data portion of the 
> SPI
> cycle.
> -  @param[out] Buffer  The

[edk2-devel] [edk2-platforms][PATCH V1 6/6] Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1

Extend the SMBIOS support for RD-N2-Cfg1 platform. RD-N2-Cfg1 platform
is a derivative of the RD-N2 platform and so most of the table values
for RD-N2 platform is reused.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c|  7 
+--
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c |  7 
+--
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 18 
++
 3 files changed, 28 insertions(+), 4 deletions(-)

diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index 367587c07673..e8326cc6ef14 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -31,7 +31,8 @@
   "RdE1Edge\0"  \
   "RdV1\0"  \
   "RdV1Mc\0"\
-  "RdN2\0"
+  "RdN2\0"  \
+  "RdN2Cfg1\0"
 
 typedef enum {
   ManufacturerName = 1,
@@ -64,7 +65,9 @@ STATIC GUID mSmbiosUid[] = {
   /* Rd-V1Mc   */
   {0x1f3a0806, 0x18b5, 0x4eca, {0xad, 0xcd, 0xba, 0x9b, 0x07, 0xb1, 0x0a, 
0xcf}},
   /* Rd-N2 */
-  {0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20, 
0x49}}
+  {0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20, 
0x49}},
+  /* Rd-N2-Cfg1*/
+  {0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e, 
0xda}},
 };
 
 /* System information */
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index 9ecaea3603de..b554ee6dea58 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -27,7 +27,7 @@
 #define SOCKET_TYPE_BASE3
 #define SOCKET_TYPE_NUM 1
 #define PROCESSOR_VERSION_BASE  (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM   8
+#define PROCESSOR_VERSION_NUM   9
 #define SERIAL_NUMBER_BASE  (PROCESSOR_VERSION_BASE + 
PROCESSOR_VERSION_NUM)
 #define TYPE4_STRINGS   \
   "0x000\0" /* Part Number */   \
@@ -41,6 +41,7 @@
   "Neoverse-V1\0"   \
   "Neoverse-V1\0"   \
   "Neoverse-N2\0"   \
+  "Neoverse-N2\0"   \
   "000-0\0" /* Serial number */ \
   "783-3\0" \
   "786-1\0" \
@@ -48,7 +49,8 @@
   "786-2\0" \
   "78A-1\0" \
   "78A-2\0" \
-  "7B7-1\0"
+  "7B7-1\0" \
+  "7B6-1\0"
 
 typedef enum {
   PartNumber = 1,
@@ -173,6 +175,7 @@ InstallType4ProcessorInformation (
 mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
 break;
   case RdN2:
+  case RdN2Cfg1:
 mArmRdSmbiosType4.Base.CoreCount = CoreCount;
 mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
 mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index 6be62900bd71..aec7c1b585fc 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -315,6 +315,24 @@ InstallType7CacheInformation (
 mArmRdSmbiosType7[4].Base.InstalledSize2 = 32768;// 32MB SLC
 mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
 break;
+  case RdN2Cfg1:
+/* L1 instruction cache */
+mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;// 64KB
+mArmRdSmbiosType7[0].Base.InstalledSize2 = 64;   // 64KB
+mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
+/* L1 data cache */
+mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64;// 64KB
+mArmRdSmbiosType7[1].Base.InstalledSize2 = 64;   // 64KB
+mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
+/* L2 cache */
+mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 1024;  // 1MB
+mArmRdSmbiosType7[2].Base.InstalledSize2 = 1024; // 1MB
+mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
+/* System level cache */
+mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 8192;  // 8MB SLC
+mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192; // 8MB SLC
+

[edk2-devel] [edk2-platforms][PATCH V1 5/6] Platform/Sgi: Define RD-N2-Cfg1 platform id values

Add the RD-N2-Cfg1 platform identification values including the part
number and configuration number. This information will be used in
populating the SMBIOS tables.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ++-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +++-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h 
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 4999c9870b49..dddb58832d73 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -39,6 +39,10 @@
 #define RD_V1_CONF_ID 0x1
 #define RD_V1_MC_CONF_ID  0x2
 
+// RD-N2-Cfg1 Platform Identification values
+#define RD_N2_CFG1_PART_NUM   0x7B6
+#define RD_N2_CFG1_CONF_ID0x1
+
 // RD-N2 Platform Identification values
 #define RD_N2_PART_NUM0x7B7
 #define RD_N2_CONF_ID 0x1
@@ -77,7 +81,8 @@ typedef enum {
   RdE1Edge,
   RdV1,
   RdV1Mc,
-  RdN2
+  RdN2,
+  RdN2Cfg1
 } ARM_RD_PRODUCT_ID;
 
 // Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c 
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index f27c949dbc24..a982e3d403fa 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -66,7 +66,13 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
 RD_N2_PART_NUM,
 RD_N2_CONF_ID,
 0
-  }
+  },
+  {
+RdN2Cfg1,
+RD_N2_CFG1_PART_NUM,
+RD_N2_CFG1_CONF_ID,
+0
+  },
 };
 
 EFI_BOOT_MODE
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75367): https://edk2.groups.io/g/devel/message/75367
Mute This Topic: https://groups.io/mt/82931746/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [edk2-platforms][PATCH V1 1/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform

From: Aditya Angadi 

Arm's RD-N2-Cfg1 platform is a variant of the RD-N2 platform. Compared
to RD-N2 platform, RD-N2-Cfg1 has a reduced core count of eight Neoverse
N2 CPUs and a smaller interconnect mesh. As part of the initial platform
support for RD-N2-Cfg1 platform, add the corresponding ACPI tables,
platform and flash description files.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc |  57 ++
 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf |  68 
 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl  | 110 

 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 109 +++
 Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc |  12 +++
 5 files changed, 356 insertions(+)

diff --git a/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc 
b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
new file mode 100644
index ..0bd149bf56ab
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
@@ -0,0 +1,57 @@
+## @file
+#  Platform Description file for RD-N2-Cfg1 platform.
+#
+#  Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME  = RdN2Cfg1
+  PLATFORM_GUID  = aca676d8-3acb-43d0-9e05-95e1ce6bf5d3
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 0x0001001B
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= AARCH64|ARM
+  BUILD_TARGETS  = NOOPT|DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = Platform/ARM/SgiPkg/SgiPlatform.fdf
+  BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
+  BUILD_NUMBER   = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+
+# include common/basic libraries from MdePkg.
+!include MdePkg/MdeLibs.dsc.inc
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+
+[PcdsFixedAtBuild.common]
+  # GIC Base Addresses
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x3000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x3010
+  gArmSgiTokenSpaceGuid.PcdGicSize|0x20
+
+  # ARM Cores and Clusters
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|1
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|8
+
+
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+
+
+[Components.common]
+  Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
new file mode 100644
index ..8c8ce462c9d3
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -0,0 +1,68 @@
+## @file
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2021, Arm Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = RdN2Cfg1AcpiTables
+  FILE_GUID  = c712719a-0aaf-438c-9cdd-35ab4d60207d  # 
gArmSgiAcpiTablesGuid
+  MODULE_TYPE= USER_DEFINED
+  VERSION_STRING = 1.0
+
+[Sources]
+  Dbg2.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  Iort.aslc
+  Mcfg.aslc
+  RdN2Cfg1/Dsdt.asl
+  RdN2Cfg1/Madt.aslc
+  Spcr.aslc
+  Ssdt.asl
+  SsdtRos.asl
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmPlatformTokenSpaceGuid.PcdClusterCount
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+  gArmTokenSpaceGuid.PcdPciBusMin
+  gArmTokenSpaceGuid.PcdPciBusMax
+
+

[edk2-devel] [edk2-platforms][PATCH V1 4/6] Platform/Sgi: ACPI CPPC support for RD-N2-Cfg1

Enable ACPI CPPC mechanism for RD-N2-Cfg1 as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-N2-Cfg1 platform does not support CPPC
revision 1 and below. So update the _OSC method to let OSPM know about
this fact.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 78 
 1 file changed, 78 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
index 55f51cc26aff..411eff84334a 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -35,6 +35,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
 Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
   }
+
+  If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+/* CPPC revision 1 and below not supported */
+And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
 } Else {
   And (STS0, Not (OSC_STS_MASK), STS0)
   Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -133,6 +139,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 0)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (0)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -151,6 +166,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 1)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (1)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -169,6 +193,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 2)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (2)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -187,6 +220,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 3)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (3)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -205,6 +247,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 4)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000560, 0x06000564, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (4)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -223,6 +274,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 5)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000578, 0x0600057C, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (5)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -241,6 +301,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 6)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000590, 0x06000594, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (6)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -259,6 +328,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 7)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x060005A8, 0x060005AC, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (7)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
-- 
2.17.1

[edk2-devel] [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Low Power Idle states for RD-N2-Cfg1

RD-N2-Cfg1 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 158 
 1 file changed, 158 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
index d68523bc43ed..55f51cc26aff 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -19,91 +19,249 @@
 DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
  EFI_ACPI_ARM_OEM_REVISION) {
   Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (CLPI, Package () {  /* LPI for Cluster, support 1 LPI state */
+  0,  // Version
+  0,  // Level Index
+  1,  // Count
+  Package () {// Power Gating state for Cluster
+2500, // Min residency (uS)
+1150, // Wake latency (uS)
+1,// Flags
+1,// Arch Context Flags
+100,  // Residency Counter Frequency
+0,// No Parent State
+0x0020,   // Integer Entry method
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI2-Cluster"
+  },
+})
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  1,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+100,  // Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+100,  // Residency Counter Frequency
+1,// Parent node can be in any shallower state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x4002,   // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI3-Core"
+  },
+})
+
 Device (CL00) {   // Cluster 0
   Name (_HID, "ACPI0010")
   Name (_UID, 0)
+  Method (_LPI, 0, NotSerialized) {
+Return (\_SB.CLPI)
+  }

[edk2-devel] [edk2-platforms][PATCH V1 2/6] Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform

The RD-N2-Cfg1 platform includes eight single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 8MB. Add PPTT
table for RD-N2-Cfg1 platform with this information.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf |   1 +
 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 166 

 2 files changed, 167 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
index 8c8ce462c9d3..59e9dfceec76 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -22,6 +22,7 @@
   Mcfg.aslc
   RdN2Cfg1/Dsdt.asl
   RdN2Cfg1/Madt.aslc
+  RdN2Cfg1/Pptt.aslc
   Spcr.aslc
   Ssdt.asl
   SsdtRos.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc 
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
new file mode 100644
index ..5890544c0b92
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
@@ -0,0 +1,166 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2-Cfg1
+* platform includes eight single-thread CPUS. Each of the CPUs include 64KB
+* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also
+* includes system level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+*   - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include 
+#include 
+#include 
+#include 
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+/** Define helper macro for populating processor core information.
+
+  @param [in] PackageId Package instance number.
+  @param [in] ClusterId Cluster instance number.
+  @param [in] CpuId CPU instance number.
+**/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId)
\
+  {
\
+/* Parameters for CPU Core */  
\
+EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (   
\
+  OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */   
\
+  PPTT_PROCESSOR_CORE_FLAGS,/* Flag */ 
\
+  OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, 
\
+Package.Cluster[ClusterId]),/* Parent */   
\
+  ((PackageId << 4) | ClusterId),   /* ACPI Id */  
\
+  2 /* Num of private resource */  
\
+), 
\
+   
\
+/* Offsets of the private resources */ 
\
+{  
\
+  OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, 
\
+Package.Cluster[ClusterId].Core[CpuId].DCache),
\
+  OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, 
\
+Package.Cluster[ClusterId].Core[CpuId].ICache) 
\
+}, 
\
+   
\
+/* L1 data cache parameters */ 
\
+EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (   
\
+  PPTT_CACHE_STRUCTURE_FLAGS,   /* Flag */ 
\
+  OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, 
\
+Package.Cluster[ClusterId].Core[CpuId].L2Cache),   
\
+/* Next level of cache */  
\
+  SIZE_64KB,/* Size */ 
\
+  256,  /* Num of sets */  
\
+  4,/* Associativity */
\
+  PPTT_DATA_CACHE_ATTR, /* Attributes */   
\
+  64/* Line size */
\
+), 
\
+   
\
+/* L1 instruction cache parameters */  
\
+

[edk2-devel] [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform

2021-05-19 Thread Fowler, Eric (Mondo International, LLC) via groups.io

RD-N2-Cfg1 platform is a variant of the RD-N2 platform. The platform
is based on 8xMP1 Neoverse N2 CPUs, CMN-700 interconnect 3x3 mesh,
multiple AXI expansion ports for I/O Coherent PCIe, Ethernet, offload
and Arm Cortex-M7 for System Control Processor (SCP) and Manageability
Control Processor (MCP).

The first patch in this series add Edk2 build system files and minimum
acpi changes required to boot the platform. The second patch add ACPI
PPTT table to describe the CPU and cache topology. The third patch in
this series enable idle state support (ACPI LPI) and the fourth patch
enables ACPI CPPC support to support the OS to scale CPU performance.
The last patch in this series adds SMBIOS support.

This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/75277

Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rdn2cfg1-initial-support

Aditya Angadi (1):
  Platform/Sgi: Add initial support for RD-N2-Cfg1 platform

Pranav Madhu (5):
  Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform
  Platform/Sgi: Low Power Idle states for RD-N2-Cfg1
  Platform/Sgi: ACPI CPPC support for RD-N2-Cfg1
  Platform/Sgi: Define RD-N2-Cfg1 platform id values
  Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1

 Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc |  57 +++
 .../SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf  |  69 
 Platform/ARM/SgiPkg/Include/SgiPlatform.h |   7 +-
 .../Type1SystemInformation.c  |   7 +-
 .../Type4ProcessorInformation.c   |   7 +-
 .../SmbiosPlatformDxe/Type7CacheInformation.c |  18 +
 .../SgiPkg/Library/PlatformLib/PlatformLib.c  |   8 +-
 .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl   | 346 ++
 .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc  | 109 ++
 .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc  | 166 +
 Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc |  12 +
 11 files changed, 800 insertions(+), 6 deletions(-)
 create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
 create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc

-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75363): https://edk2.groups.io/g/devel/message/75363
Mute This Topic: https://groups.io/mt/82931741/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] A plea for help

2021-05-19 Thread Bret Barkelew via groups.io

Have you tried the latest Python 3.x?

- Bret

From: Fowler, Eric (Mondo International, LLC) via 
groups.io
Sent: Wednesday, May 19, 2021 12:41 AM
To: devel@edk2.groups.io
Subject: [EXTERNAL] [edk2-devel] A plea for help

build.py...
: error C0DE: Unknown fatal error when processing 
[c:\edk2020\district-defend\edk2\MdeModulePkg\Universal\Console\GraphicsConsoleDxe\GraphicsConsoleDxe.inf]

(Please send email to devel@edk2.groups.io for help, attaching following call 
stack trace!)

(Python 3.9.5 on win32) Traceback (most recent call last):
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2596, in Main
MyBuild.Launch()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2391, in Launch
self._MultiThreadBuildPlatform()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2271, in _MultiThreadBuildPlatform
self.CreateAsBuiltInf()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2401, in CreateAsBuiltInf
Module.CreateAsBuiltInf()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\AutoGen\ModuleAutoGen.py",
 line 1503, in CreateAsBuiltInf
PatchList = parsePcdInfoFromMapFile(
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\GenPatchPcdTable\GenPatchPcdTable.py",
 line 59, in parsePcdInfoFromMapFile
return _parseGeneral(lines, efifilepath)
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\GenPatchPcdTable\GenPatchPcdTable.py",
 line 174, in _parseGeneral
efisecs = PeImageClass(efifilepath).SectionHeaderList
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\Common\Misc.py", line 
1638, in __init__
if ByteArray.tostring() != b'PE\0\0':
AttributeError: 'array.array' object has no attribute 'tostring'


- Failed -
Build end time: 21:15:31, May.18 2021
Build total time: 00:07:11




-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75361): https://edk2.groups.io/g/devel/message/75361
Mute This Topic: https://groups.io/mt/82931279/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] A plea for help

build.py...
: error C0DE: Unknown fatal error when processing 
[c:\edk2020\district-defend\edk2\MdeModulePkg\Universal\Console\GraphicsConsoleDxe\GraphicsConsoleDxe.inf]

(Please send email to devel@edk2.groups.io for help, attaching following call 
stack trace!)

(Python 3.9.5 on win32) Traceback (most recent call last):
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2596, in Main
MyBuild.Launch()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2391, in Launch
self._MultiThreadBuildPlatform()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2271, in _MultiThreadBuildPlatform
self.CreateAsBuiltInf()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\build\build.py", line 
2401, in CreateAsBuiltInf
Module.CreateAsBuiltInf()
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\AutoGen\ModuleAutoGen.py",
 line 1503, in CreateAsBuiltInf
PatchList = parsePcdInfoFromMapFile(
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\GenPatchPcdTable\GenPatchPcdTable.py",
 line 59, in parsePcdInfoFromMapFile
return _parseGeneral(lines, efifilepath)
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\GenPatchPcdTable\GenPatchPcdTable.py",
 line 174, in _parseGeneral
efisecs = PeImageClass(efifilepath).SectionHeaderList
  File 
"C:\EDK2020\district-defend\edk2\BaseTools\Source\Python\Common\Misc.py", line 
1638, in __init__
if ByteArray.tostring() != b'PE\0\0':
AttributeError: 'array.array' object has no attribute 'tostring'


- Failed -
Build end time: 21:15:31, May.18 2021
Build total time: 00:07:11


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75360): https://edk2.groups.io/g/devel/message/75360
Mute This Topic: https://groups.io/mt/82931279/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v2] UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area

On 05/17/21 17:03, Lendacky, Thomas wrote:
> On 5/16/21 11:22 PM, Laszlo Ersek wrote:

>> But now, with SEV-ES enabled, we'll have a separate, discontiguous area
>> -- and neither BackupAndPrepareWakeupBuffer(), nor its counterpart
>> RestoreWakeupBuffer() take that into account.
>>
>> Therefore I think, while this patch is regression-free for the SEV-ES
>> *disabled* case, it may corrupt memory (through not restoring the AP
>> stack area's original contents) with SEV-ES enabled.
> 
> This is the current behavior for SEV-ES. The wakeup buffer memory is
> marked as reserved, at least in the DXE phase.

Another question that occurred to me later: where does this reservation
happen? If we have a separate allocation for the AP stacks now, do we
need to reserve that too, separately?

What about PEI in general? Why is there no risk of corruption there?

(Sorry if these are lame questions!)

Thanks,
Laszlo



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75359): https://edk2.groups.io/g/devel/message/75359
Mute This Topic: https://groups.io/mt/82833645/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH] BaseTools: Add -ffat-lto-objects option in GCC5 tool chain

Hi Liming,

On 05/19/21 04:27, gaoliming wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3403
> 
> This option can trig the uninitialized warning when lto is enabled.
> The image size data is also collected for OVMF. There is no impact.
> 
> Cc: Sergei Dmitrouk 
> Cc: Bob Feng 
> Cc: Ard Biesheuvel 
> Signed-off-by: Liming Gao 
> ---
>  BaseTools/Conf/tools_def.template | 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)

I've now read the documentation on "-ffat-lto-objects", and I agree that
it should not affect the final module executable sizes.

However, I don't understand how this option *helps*. You mention
"uninitialized warning". I find nothing related to that in the
documentation.

According to the documentation, "fat" LTO objects include both object
code and intermediate language (GIMPLE) bytecode. Such objects can then
be linked with, or without, link-time (= interprocedural) optimization.
As I understand the documentation, "fat" LTO objects only make a
difference if there are parts of the toolchain that are themselves
unaware of LTO, and so need the GIMPLE bytecode to be present in the
object files.

I *guess* that this is the situation that we have in edk2 -- is there
perhaps something in our toolchain(s) that does not "notice" LTO without
"fat" LTO objects, and therefore we fail to emit a warning? Because,
without LTO, we don't notice that an initialization is missing?

This is too speculative. The commit message should please include more
details. I'd like to understand what code in edk2 is affected, what the
specific warning is, what the problematic component in the toolchain is
(i.e., what tool requires GIMPLE bytecode to be present in the object file).

Thanks,
Laszlo



> 
> diff --git a/BaseTools/Conf/tools_def.template 
> b/BaseTools/Conf/tools_def.template
> index 498696e583..aad5297385 100755
> --- a/BaseTools/Conf/tools_def.template
> +++ b/BaseTools/Conf/tools_def.template
> @@ -2315,10 +2315,10 @@ RELEASE_GCC49_AARCH64_DLINK_XIPFLAGS = -z 
> common-page-size=0x20
>  *_GCC5_IA32_OBJCOPY_FLAGS=
>  *_GCC5_IA32_NASM_FLAGS   = -f elf32
>  
> -  DEBUG_GCC5_IA32_CC_FLAGS   = DEF(GCC5_IA32_CC_FLAGS) -flto -Os
> +  DEBUG_GCC5_IA32_CC_FLAGS   = DEF(GCC5_IA32_CC_FLAGS) -ffat-lto-objects 
> -flto -Os
>DEBUG_GCC5_IA32_DLINK_FLAGS= DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os 
> -Wl,-m,elf_i386,--oformat=elf32-i386
>  
> -RELEASE_GCC5_IA32_CC_FLAGS   = DEF(GCC5_IA32_CC_FLAGS) -flto -Os 
> -Wno-unused-but-set-variable -Wno-unused-const-variable
> +RELEASE_GCC5_IA32_CC_FLAGS   = DEF(GCC5_IA32_CC_FLAGS) -ffat-lto-objects 
> -flto -Os -Wno-unused-but-set-variable -Wno-unused-const-variable
>  RELEASE_GCC5_IA32_DLINK_FLAGS= DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os 
> -Wl,-m,elf_i386,--oformat=elf32-i386
>  
>NOOPT_GCC5_IA32_CC_FLAGS   = DEF(GCC5_IA32_CC_FLAGS) -O0
> @@ -2347,10 +2347,10 @@ RELEASE_GCC5_IA32_DLINK_FLAGS= 
> DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,
>  *_GCC5_X64_OBJCOPY_FLAGS =
>  *_GCC5_X64_NASM_FLAGS= -f elf64
>  
> -  DEBUG_GCC5_X64_CC_FLAGS= DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO 
> -Os
> +  DEBUG_GCC5_X64_CC_FLAGS= DEF(GCC5_X64_CC_FLAGS) -ffat-lto-objects 
> -flto -DUSING_LTO -Os
>DEBUG_GCC5_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os
>  
> -RELEASE_GCC5_X64_CC_FLAGS= DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO 
> -Os -Wno-unused-but-set-variable -Wno-unused-const-variable
> +RELEASE_GCC5_X64_CC_FLAGS= DEF(GCC5_X64_CC_FLAGS) -ffat-lto-objects 
> -flto -DUSING_LTO -Os -Wno-unused-but-set-variable -Wno-unused-const-variable
>  RELEASE_GCC5_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os
>  
>NOOPT_GCC5_X64_CC_FLAGS= DEF(GCC5_X64_CC_FLAGS) -O0
> @@ -2382,10 +2382,10 @@ RELEASE_GCC5_X64_DLINK_FLAGS = 
> DEF(GCC5_X64_DLINK_FLAGS) -flto -Os
>  *_GCC5_ARM_VFRPP_FLAGS   = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) 
> DEF(GCC_VFRPP_FLAGS)
>  *_GCC5_ARM_CC_XIPFLAGS   = DEF(GCC5_ARM_CC_XIPFLAGS)
>  
> -  DEBUG_GCC5_ARM_CC_FLAGS= DEF(GCC5_ARM_CC_FLAGS) -flto 
> -Wno-unused-but-set-variable -Wno-unused-const-variable
> +  DEBUG_GCC5_ARM_CC_FLAGS= DEF(GCC5_ARM_CC_FLAGS) -ffat-lto-objects 
> -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
>DEBUG_GCC5_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os 
> -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm 
> -Wl,-plugin-opt=-pass-through=-llto-arm
>  
> -RELEASE_GCC5_ARM_CC_FLAGS= DEF(GCC5_ARM_CC_FLAGS) -flto 
> -Wno-unused-but-set-variable -Wno-unused-const-variable
> +RELEASE_GCC5_ARM_CC_FLAGS= DEF(GCC5_ARM_CC_FLAGS) -ffat-lto-objects 
> -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
>  RELEASE_GCC5_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os 
> -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm 
> -Wl,-plugin-opt=-pass-through=-llto-arm
>  
>NOOPT_GCC5_ARM_CC_FLAGS=

[edk2-devel] [PATCH v4 3/5] GenFv: Arm: support images entered in Thumb mode

Change GenFv for Arm architecture to generate a specific jump
instruction as image entry instruction, when the target entry label
is assembled with Thumb instruction set. This is possible since
SecCoreEntryAddress value fetched from the PE32 has its LSBit set when
the entry instruction executes in Thumb mode.

Signed-off-by: Etienne Carriere 
Acked-by: Liming Gao 
Reviewed-by: Sami Mujawar 

---
Changes since v3:
- Removed Cc tags and apply review tags.

Changes since v2:
- Fix missing parentheses in expression.

Changes since v1:
- Fix typos in commit log and inline comments
- Change if() test operand to be an explicit boolean
---
 BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++-
 1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c 
b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 6e296b8ad6..6cf9c84e73 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include "FvLib.h"
 #include "PeCoffLib.h"
 
-#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION   0xEB00
 #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION  0x1400
 
+/*
+ * Arm instruction to jump to Fv entry instruction in Arm or Thumb mode.
+ * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX (immediate)
+ * BLX (encoding A2) branches to offset in Thumb instruction set mode.
+ * BL (encoding A1) branches to offset in Arm instruction set mode.
+ */
+#define ARM_JUMP_OFFSET_MAX0xff
+#define ARM_JUMP_TO_ARM(Offset)(0xeb00 | ((Offset - 8) >> 2))
+
+#define _ARM_JUMP_TO_THUMB(Imm32)  (0xfa00 | \
+(((Imm32) & (1 << 1)) << (24 - 1)) | \
+(((Imm32) >> 2) & 0x7f))
+#define ARM_JUMP_TO_THUMB(Offset)  _ARM_JUMP_TO_THUMB((Offset) - 8)
+
+/*
+ * Arm instruction to retrun from exception (MOVS PC, LR)
+ */
+#define ARM_RETURN_FROM_EXCEPTION  0xE1B0F07E
+
 BOOLEAN mArm = FALSE;
 BOOLEAN mRiscV = FALSE;
 STATIC UINT32   MaxFfsAlignment = 0;
@@ -2203,23 +2221,25 @@ Returns:
 // if we found an SEC core entry point then generate a branch instruction
 // to it and populate a debugger SWI entry as well
 if (UpdateVectorSec) {
+  UINT32EntryOffset;
 
   VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC vector");
 
-  // B SecEntryPoint - signed_immed_24 part +/-32MB offset
-  // on ARM, the PC is always 8 ahead, so we're not really jumping from 
the base address, but from base address + 8
-  ResetVector[0] = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress - 8) 
>> 2;
+  EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress);
 
-  if (ResetVector[0] > 0x00FF) {
-Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB 
of the start of the FV");
+  if (EntryOffset > ARM_JUMP_OFFSET_MAX) {
+  Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above 1MB of 
the start of the FV");
 return EFI_ABORTED;
   }
 
-  // Add opcode for an unconditional branch with no link. i.e.: " B 
SecEntryPoint"
-  ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION;
+  if ((SecCoreEntryAddress & 1) != 0) {
+ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset);
+  } else {
+ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset);
+  }
 
   // SWI handler movs   pc,lr. Just in case a debugger uses SWI
-  ResetVector[2] = 0xE1B0F07E;
+  ResetVector[2] = ARM_RETURN_FROM_EXCEPTION;
 
   // Place holder to support a common interrupt handler from ROM.
   // Currently not supported. For this to be used the reset vector would 
not be in this FV
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75355): https://edk2.groups.io/g/devel/message/75355
Mute This Topic: https://groups.io/mt/82931045/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v4 1/5] ArmPkg/IndustryStandard: 32b/64b agnostic FF-A, Mm SVC and Std SMC IDs

Defines ARM_SVC_ID_FFA_* and ARM_SVC_ID_SP_* identifiers for 32bit
function IDs as per SMCCC specification. Defines also generic ARM
SVC identifier macros to wrap 32bit or 64bit identifiers upon target
built architecture.

Signed-off-by: Etienne Carriere 
Reviewed-by: Sami Mujawar 

---
Changes since v3:
- Remove Cc tags and apply review tag.

No change since v2

Changes since v1:
- Define ARM_SMC_ID_MM_COMMUNICATE 32b/64b agnostic helper ID in
  ArmStdSmc.h, as expected by few following commits in this series.
---
 ArmPkg/Include/IndustryStandard/ArmFfaSvc.h | 12 
 ArmPkg/Include/IndustryStandard/ArmMmSvc.h  | 15 +++
 ArmPkg/Include/IndustryStandard/ArmStdSmc.h |  8 
 3 files changed, 35 insertions(+)

diff --git a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h 
b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
index 65b8343ade..ebcb54b28b 100644
--- a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
@@ -17,9 +17,21 @@
 #define ARM_FFA_SVC_H_
 
 #define ARM_SVC_ID_FFA_VERSION_AARCH32  0x8463
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32  0x846F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x8470
 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64  0xC46F
 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC470
 
+/* Generic IDs when using AArch32 or AArch64 execution state */
+#ifdef MDE_CPU_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ 
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ 
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
+#endif
+
 #define SPM_MAJOR_VERSION_FFA   1
 #define SPM_MINOR_VERSION_FFA   0
 
diff --git a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h 
b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
index 33d60ccf17..deb3bc99d2 100644
--- a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
@@ -15,10 +15,25 @@
  * privileged operations on its behalf.
  */
 #define ARM_SVC_ID_SPM_VERSION_AARCH32 0x8460
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32   0x8461
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32   0x8464
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32   0x8465
 #define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64   0xC461
 #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64   0xC464
 #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64   0xC465
 
+/* Generic IDs when using AArch32 or AArch64 execution state */
+#ifdef MDE_CPU_AARCH64
+#define ARM_SVC_ID_SP_EVENT_COMPLETE   
ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES   
ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES   
ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SVC_ID_SP_EVENT_COMPLETE   
ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES   
ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES   
ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
+#endif
+
 #define SET_MEM_ATTR_DATA_PERM_MASK   0x3
 #define SET_MEM_ATTR_DATA_PERM_SHIFT0
 #define SET_MEM_ATTR_DATA_PERM_NO_ACCESS0
diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h 
b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
index 67afb0ea2d..9116a291da 100644
--- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
@@ -49,6 +49,14 @@
 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH32  0x8441
 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH64  0xC441
 
+/* Generic ID when using AArch32 or AArch64 execution state */
+#ifdef MDE_CPU_AARCH64
+#define ARM_SMC_ID_MM_COMMUNICATE   ARM_SMC_ID_MM_COMMUNICATE_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SMC_ID_MM_COMMUNICATE   ARM_SMC_ID_MM_COMMUNICATE_AARCH32
+#endif
+
 /* MM return error codes */
 #define ARM_SMC_MM_RET_SUCCESS  0
 #define ARM_SMC_MM_RET_NOT_SUPPORTED   -1
-- 
2.17.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75353): https://edk2.groups.io/g/devel/message/75353
Mute This Topic: https://groups.io/mt/82931043/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v4 2/5] ArmPkg: prepare 32bit ARM build of StandaloneMmPkg

Changes in ArmPkg to prepare building StandaloneMm firmware for
32bit Arm architectures.

Adds MmCommunicationDxe driver and ArmMmuPeiLib and
ArmmmuStandaloneMmLib libraries to the list of the standard
components build for ArmPkg on when ARM architectures.

Changes path of source file AArch64/ArmMmuStandaloneMmLib.c
and compile it for both 32bit and 64bit architectures.

Signed-off-by: Etienne Carriere 
Reviewed-by: Sami Mujawar 

---
Changes since v3:
- Remove Cc tags and apply review tag.

No change since v2
No change since v1
---
 ArmPkg/ArmPkg.dec   |  2 +-
 ArmPkg/ArmPkg.dsc   |  2 +-
 ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c |  2 +-
 ArmPkg/Library/StandaloneMmMmuLib/{AArch64 => }/ArmMmuStandaloneMmLib.c | 15 
---
 ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf |  6 
+++---
 5 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 214b2f5892..6ed51edd03 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -137,7 +137,7 @@
   # hardware coherency (i.e., no virtualization or cache coherent DMA)
   
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x0043
 
-[PcdsFeatureFlag.AARCH64]
+[PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
   ## Used to select method for requesting services from S-EL1.
   #   TRUE  - Selects FF-A calls for communication between S-EL0 and SPMC.
   #   FALSE - Selects SVC calls for communication between S-EL0 and SPMC.
diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
index 926986cf7f..4c79dadf9e 100644
--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -158,7 +158,7 @@
   ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
   ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
 
-[Components.AARCH64]
+[Components.AARCH64, Components.ARM]
   ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
   ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
   ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
diff --git a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c 
b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
index b1e3095809..4ae38a9f22 100644
--- a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
+++ b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
@@ -125,7 +125,7 @@ MmCommunication2Communicate (
   }
 
   // SMC Function ID
-  CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE_AARCH64;
+  CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE;
 
   // Cookie
   CommunicateSmcArgs.Arg1 = 0;
diff --git a/ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c 
b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
similarity index 92%
rename from ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c
rename to ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
index dd014beec8..20f873e680 100644
--- a/ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c
+++ b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
@@ -2,6 +2,7 @@
   File managing the MMU for ARMv8 architecture in S-EL0
 
   Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.
+  Copyright (c) 2021, Linaro Limited
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Reference(s):
@@ -62,7 +63,7 @@ SendMemoryPermissionRequest (
 // for other Direct Request calls which are not atomic
 // We therefore check only for Direct Response by the
 // callee.
-if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64) {
+if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP) {
   // A Direct Response means FF-A success
   // Now check the payload for errors
   // The callee sends back the return value
@@ -164,13 +165,13 @@ GetMemoryPermissions (
   ZeroMem (, sizeof (ARM_SVC_ARGS));
   if (FeaturePcdGet (PcdFfaEnable)) {
 // See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
-SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
+SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ;
 SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
 SvcArgs.Arg2 = 0;
-SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
+SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
 SvcArgs.Arg4 = BaseAddress;
   } else {
-SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
+SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
 SvcArgs.Arg1 = BaseAddress;
 SvcArgs.Arg2 = 0;
 SvcArgs.Arg3 = 0;
@@ -219,15 +220,15 @@ RequestMemoryPermissionChange (
   ZeroMem (, sizeof (ARM_SVC_ARGS));
   if (FeaturePcdGet (PcdFfaEnable)) {
 // See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
-SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
+SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ;
 SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
 SvcArgs.Arg2 = 0;
-SvcArgs.Arg3 =

[edk2-devel] [PATCH v4 4/5] StandaloneMmPkg: fix pointer/int casts against 32bit architectures

Use intermediate (UINTN) cast when casting int from/to pointer. This
is needed as UINT64 values cast from/to 32bit pointer for 32bit
architectures.

Signed-off-by: Etienne Carriere 
Acked-by: Jiewen Yao 
Reviewed-by: Sami Mujawar 
---
Changes since v3:
- Remove Cc tags and apply review tags.

No change since v2
No change since v1
---
 StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c  
 |  8 
 StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c 
 | 14 +++---
 
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
 |  2 +-
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c 
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
index 6884095c49..d4590bcd19 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
@@ -164,8 +164,8 @@ StandaloneMmCpuInitialize (
 
   // Share the entry point of the CPU driver
   DEBUG ((DEBUG_INFO, "Sharing Cpu Driver EP *0x%lx = 0x%lx\n",
-  (UINT64) CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr,
-  (UINT64) PiMmStandaloneArmTfCpuDriverEntry));
+  (UINTN) CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr,
+  (UINTN) PiMmStandaloneArmTfCpuDriverEntry));
   *(CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr) = 
PiMmStandaloneArmTfCpuDriverEntry;
 
   // Find the descriptor that contains the whereabouts of the buffer for
@@ -180,8 +180,8 @@ StandaloneMmCpuInitialize (
 return Status;
   }
 
-  DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalStart - 0x%lx\n", (UINT64) 
NsCommBufMmramRange->PhysicalStart));
-  DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalSize - 0x%lx\n", (UINT64) 
NsCommBufMmramRange->PhysicalSize));
+  DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalStart - 0x%lx\n", (UINTN) 
NsCommBufMmramRange->PhysicalStart));
+  DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalSize - 0x%lx\n", (UINTN) 
NsCommBufMmramRange->PhysicalSize));
 
   CopyMem (, NsCommBufMmramRange, sizeof(EFI_MMRAM_DESCRIPTOR));
   DEBUG ((DEBUG_INFO, "mNsCommBuffer: 0x%016lx - 0x%lx\n", 
mNsCommBuffer.CpuStart, mNsCommBuffer.PhysicalSize));
diff --git 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
index e8fb96bd6e..4d4cf3d5ff 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
@@ -72,14 +72,14 @@ CreateHobListFromBootInfo (
 
   // Create a hoblist with a PHIT and EOH
   HobStart = HobConstructor (
-   (VOID *) PayloadBootInfo->SpMemBase,
+   (VOID *) (UINTN) PayloadBootInfo->SpMemBase,
(UINTN)  PayloadBootInfo->SpMemLimit - 
PayloadBootInfo->SpMemBase,
-   (VOID *) PayloadBootInfo->SpHeapBase,
-   (VOID *) (PayloadBootInfo->SpHeapBase + 
PayloadBootInfo->SpHeapSize)
+   (VOID *) (UINTN) PayloadBootInfo->SpHeapBase,
+   (VOID *) (UINTN) (PayloadBootInfo->SpHeapBase + 
PayloadBootInfo->SpHeapSize)
);
 
   // Check that the Hoblist starts at the bottom of the Heap
-  ASSERT (HobStart == (VOID *) PayloadBootInfo->SpHeapBase);
+  ASSERT (HobStart == (VOID *) (UINTN) PayloadBootInfo->SpHeapBase);
 
   // Build a Boot Firmware Volume HOB
   BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);
@@ -190,9 +190,9 @@ CreateHobListFromBootInfo (
   MmramRanges[3].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;
 
   // Base and size of heap memory shared by all cpus
-  MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) HobStart;
-  MmramRanges[4].CpuStart  = (EFI_PHYSICAL_ADDRESS) HobStart;
-  MmramRanges[4].PhysicalSize  = HobStart->EfiFreeMemoryBottom - 
(EFI_PHYSICAL_ADDRESS) HobStart;
+  MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
+  MmramRanges[4].CpuStart  = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
+  MmramRanges[4].PhysicalSize  = HobStart->EfiFreeMemoryBottom - 
(EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
   MmramRanges[4].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;
 
   // Base and size of heap memory shared by all cpus
diff --git 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
index 6c50f470aa..b445d6942e 100644
--- 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
+++ 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
@@ -328,7 +328,7 @@ _ModuleEntryPoint (
 
   // Locate PE/COFF File information for the Standalone MM core module
   Status = LocateStandaloneMmCorePeCoffData (
-

[edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for 32bit arm machines

This change allows to build StandaloneMmPkg components for 32bit Arm
StandaloneMm firmware.

This change mainly moves AArch64/ source files to Arm/ side directory
for several components:  StandaloneMmCpu, StandaloneMmCoreEntryPoint
and StandaloneMmMemLib. The source file is built for both 32b and 64b
Arm targets.

Signed-off-by: Etienne Carriere 
---
Changes since v3:
- Fix BuildOptions.ARM in StandaloneMmPkg.
- Remove Cc tags.

No change since v2

Changes since v1:
- ARM_SMC_ID_MM_COMMUNICATE 32b/64b agnostic helper ID is defined
  in ArmStdSmc.h (see 1st commit in this series) instead of being
  local to EventHandle.c.
- Fix void occurrence to VOID.
- Fix path in StandaloneMmPkg/StandaloneMmPkg.dsc
---
 StandaloneMmPkg/Core/StandaloneMmCore.inf  
  |  2 +-
 StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/EventHandle.c
  |  5 +++--
 StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.c
  |  2 +-
 StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.h
  |  0
 StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.inf  
  |  0
 StandaloneMmPkg/Include/Library/{AArch64 => Arm}/StandaloneMmCoreEntryPoint.h  
  |  0
 StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => 
Arm}/CreateHobList.c  |  2 +-
 StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => 
Arm}/SetPermissions.c |  2 +-
 StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => 
Arm}/StandaloneMmCoreEntryPoint.c | 16 
 
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
| 14 +++---
 StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => 
Arm}/StandaloneMmCoreHobLib.c |  0
 StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => 
Arm}/StandaloneMmCoreHobLibInternal.c |  0
 StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf  
  |  8 
 
StandaloneMmPkg/Library/StandaloneMmMemLib/{AArch64/StandaloneMmMemLibInternal.c
 => ArmStandaloneMmMemLibInternal.c} |  9 -
 StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf  
  |  6 +++---
 StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf  
  |  2 +-
 StandaloneMmPkg/StandaloneMmPkg.dsc
  | 12 
 17 files changed, 46 insertions(+), 34 deletions(-)

diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf 
b/StandaloneMmPkg/Core/StandaloneMmCore.inf
index 87bf6e9440..56042b7b39 100644
--- a/StandaloneMmPkg/Core/StandaloneMmCore.inf
+++ b/StandaloneMmPkg/Core/StandaloneMmCore.inf
@@ -17,7 +17,7 @@
   PI_SPECIFICATION_VERSION   = 0x00010032
   ENTRY_POINT= StandaloneMmMain
 
-#  VALID_ARCHITECTURES   = IA32 X64 AARCH64
+#  VALID_ARCHITECTURES   = IA32 X64 AARCH64 ARM
 
 [Sources]
   StandaloneMmCore.c
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c 
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
similarity index 95%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 63fbe26642..165d696f99 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -2,6 +2,7 @@
 
   Copyright (c) 2016 HP Development Company, L.P.
   Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+  Copyright (c) 2021, Linaro Limited
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -92,8 +93,8 @@ PiMmStandaloneArmTfCpuDriverEntry (
   // receipt of a synchronous MM request. Use the Event ID to distinguish
   // between synchronous and asynchronous events.
   //
-  if ((ARM_SMC_ID_MM_COMMUNICATE_AARCH64 != EventId) &&
-  (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 != EventId)) {
+  if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
+  (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId)) {
 DEBUG ((DEBUG_INFO, "UnRecognized Event - 0x%x\n", EventId));
 return EFI_INVALID_PARAMETER;
   }
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c 
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
similarity index 96%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
index

Re: [edk2-devel] [PATCH v2] IntelFsp2WrapperPkg: Remove microcode related PCDs

2021-05-19 Thread Jason Lou

Hi Chasel & Star,

So far, the PCD usage has been removed from all of these platforms:
1. Server platforms("ServerGen2")
2. Client platforms("ClientMaster")
3. Edk2-platform opensource

Thanks
Jason Lou


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75352): https://edk2.groups.io/g/devel/message/75352
Mute This Topic: https://groups.io/mt/82111237/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v2 5/5] Maintainers: update Maintainers file as new files/folders created

Hi Sami,

On 05/18/21 22:26, Sami Mujawar wrote:
> Hi Jianyon,
> 
> Thank you for including this patch in the series. There is a patch on
> the mailing list to add me as a reviewer for ArmVirtPkg at package level.
> Therefore, this patch would no longer be needed. Apologies for not
> communicating this to you earlier.

thank you for reviewing this patch series -- I'm really happy about your
careful review! I did my own (superficial) review as first thing this
morning, before looking at my new mail, and I highly appreciate that you
provided an in-depth review before I asked!

Kudos!
Laszlo


> 
> Regards,
> 
> Sami Mujawar
> 
> 
> On 17/05/2021 07:50 AM, Jianyong Wu wrote:
>> Create new entry for Cloud Hypervisor and assign reviewer to Sami
>> Mujawar.
>>
>> Cc: Sami Mujawar 
>> Signed-off-by: Jianyong Wu 
>> ---
>>   Maintainers.txt | 7 +++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/Maintainers.txt b/Maintainers.txt
>> index cafe6b1ab85d..f8fae067c656 100644
>> --- a/Maintainers.txt
>> +++ b/Maintainers.txt
>> @@ -167,6 +167,13 @@ F: ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/
>>   F: ArmVirtPkg/Library/NorFlashKvmtoolLib/
>>   R: Sami Mujawar 
>>   +ArmVirtPkg: Cloud Hypervisor emulated platform support
>> +F: ArmVirtPkg/ArmVirtCloudHv*
>> +F: ArmVirtPkg/CloudHvAcpiPlatformDxe/
>> +F: ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/
>> +F: ArmVirtPkg/Library/CloudHvVirtMemInfoLib/
>> +R: Sami Mujawar 
>> +
>>   BaseTools
>>   F: BaseTools/
>>   W: https://github.com/tianocore/tianocore.github.io/wiki/BaseTools
> 



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75351): https://edk2.groups.io/g/devel/message/75351
Mute This Topic: https://groups.io/mt/82880905/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v2 5/5] Maintainers: update Maintainers file as new files/folders created

On 05/17/21 08:50, Jianyong Wu wrote:
> Create new entry for Cloud Hypervisor and assign reviewer to Sami
> Mujawar.
> 
> Cc: Sami Mujawar 
> Signed-off-by: Jianyong Wu 
> ---
>  Maintainers.txt | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Maintainers.txt b/Maintainers.txt
> index cafe6b1ab85d..f8fae067c656 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -167,6 +167,13 @@ F: ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/
>  F: ArmVirtPkg/Library/NorFlashKvmtoolLib/
>  R: Sami Mujawar 
>  
> +ArmVirtPkg: Cloud Hypervisor emulated platform support
> +F: ArmVirtPkg/ArmVirtCloudHv*
> +F: ArmVirtPkg/CloudHvAcpiPlatformDxe/
> +F: ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/
> +F: ArmVirtPkg/Library/CloudHvVirtMemInfoLib/
> +R: Sami Mujawar 
> +
>  BaseTools
>  F: BaseTools/
>  W: https://github.com/tianocore/tianocore.github.io/wiki/BaseTools
> 

This patch is obsolete due to:

  [edk2-devel] [PATCH] Maintainers.txt: add Sami Mujawar as top-level 
ArmVirtPkg reviewer

  https://edk2.groups.io/g/devel/message/75116
  https://listman.redhat.com/archives/edk2-devel-archive/2021-May/msg00432.html
  msgid: <20210514114857.12286-1-ler...@redhat.com>

so please drop it.

Thanks
Laszlo



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75350): https://edk2.groups.io/g/devel/message/75350
Mute This Topic: https://groups.io/mt/82880905/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v2 4/5] ArmVirtPkg: Introduce Cloud Hypervisor to edk2 family

On 05/17/21 08:50, Jianyong Wu wrote:
> Cloud Hypervisor is kvm based VMM and is implemented in rust. Just like
> other VMMs it need UEFI support to let ACPI work. That's why
> Cloud Hypervisor is introduced here.
> 
> Cc: Laszlo Ersek 
> Cc: Leif Lindholm 
> Cc: 

(1) Empty CC?

> Signed-off-by: Jianyong Wu 
> ---
>  ArmVirtPkg/ArmVirtCloudHv.dsc   | 455 
>  ArmVirtPkg/ArmVirtCloudHv.fdf   | 292 +++
>  ArmVirtPkg/ArmVirtCloudHvFvMain.fdf.inc | 169 +
>  3 files changed, 916 insertions(+)
>  create mode 100644 ArmVirtPkg/ArmVirtCloudHv.dsc
>  create mode 100644 ArmVirtPkg/ArmVirtCloudHv.fdf
>  create mode 100644 ArmVirtPkg/ArmVirtCloudHvFvMain.fdf.inc
> 
> diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc
> new file mode 100644
> index ..bf1f8c5a75ae
> --- /dev/null
> +++ b/ArmVirtPkg/ArmVirtCloudHv.dsc
> @@ -0,0 +1,455 @@
> +#
> +#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.

(2) Please update the end year on the ARM (C).

> +#  Copyright (c) 2014, Linaro Limited. All rights reserved.
> +#  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +
> +[Defines]
> +  PLATFORM_NAME  = ArmVirtCloudHv
> +  PLATFORM_GUID  = DFFED32B-DFFE-D32B-DFFE-D32BDFFED32B
> +  PLATFORM_VERSION   = 0.1
> +  DSC_SPECIFICATION  = 0x00010005
> +  OUTPUT_DIRECTORY   = Build/ArmVirtCloudHv-$(ARCH)
> +  SUPPORTED_ARCHITECTURES= AARCH64|ARM
> +  BUILD_TARGETS  = DEBUG|RELEASE|NOOPT
> +  SKUID_IDENTIFIER   = DEFAULT
> +  FLASH_DEFINITION   = ArmVirtPkg/ArmVirtCloudHv.fdf
> +
> +  #
> +  # Defines for default states.  These can be changed on the command line.
> +  # -D FLAG=VALUE
> +  #
> +  DEFINE TTY_TERMINAL= FALSE
> +  DEFINE SECURE_BOOT_ENABLE  = FALSE
> +  DEFINE TPM2_ENABLE = FALSE
> +  DEFINE TPM2_CONFIG_ENABLE  = FALSE
> +
> +!include ArmVirtPkg/ArmVirt.dsc.inc
> +
> +[LibraryClasses.common]
> +  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> +  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
> +
> +  # Virtio Support
> +  VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
> +  
> VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf
> +  QemuFwCfgLib|ArmVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
> +  QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/BaseQemuFwCfgS3LibNull.inf
> +  
> QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFwCfgSimpleParserLib.inf
> +  
> QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf
> +
> +  
> ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
> +
> +  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> +  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> +  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> +  
> PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> +  
> PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
> +  
> CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> +  
> FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
> +  QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf
> +  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> +  
> PciPcdProducerLib|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
> +  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
> +  
> PciHostBridgeLib|ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
> +  
> PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf
> +
> +!if $(TPM2_ENABLE) == TRUE
> +  Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf
> +  
> Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeTcg2PhysicalPresenceLib.inf
> +  
> TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
> +!else
> +  
> TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
> +!endif
> +
> +!include MdePkg/MdeLibs.dsc.inc
> +
> +[LibraryClasses.common.PEIM]
> +  
> ArmVirtMemInfoLib|ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf
> +
> +!if $(TPM2_ENABLE) == TRUE
> +  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
> +  ResetSystemLib|MdeModulePkg/Library/PeiResetSystemLib/PeiResetSystemLib.inf
> +

Re: [edk2-devel] [PATCH v2 3/5] ArmVirtPkg: enable ACPI for cloud hypervisor

On 05/17/21 08:50, Jianyong Wu wrote:
> The current implementation of PlatformHasAcpiDt is not a common
> library and is on behalf of qemu. So give a specific version for
> Cloud Hypervisor here.
> 
> There is no device like Fw-cfg in qemu in Cloud Hypervisor, so a specific
> Acpi handler is introduced here.
> 
> The handler implemented here is in a very simple way:
> firstly, aquire the Rsdp address from the PCD varaible in the top
> ".dsc";
> secondly, get the Xsdp address from Rsdp structure;
> thirdly, get the Acpi tables following the Xsdp structrue and install it

(1) Please consider running a spell checker on the commit message
("aquire" should be "acquire", "varaible" should be "variable",
"structrue" should be "structure"). Having this many typos in a short
commit message gives the patch a rushed vibe.

> one by one.
> 
> Signed-off-by: Jianyong Wu 
> ---
>  .../CloudHvAcpiPlatformDxe.inf| 51 +
>  .../CloudHvHasAcpiDtDxe.inf   | 43 +++
>  .../CloudHvAcpiPlatformDxe/CloudHvAcpi.c  | 73 +++
>  .../CloudHvHasAcpiDtDxe.c | 69 ++
>  4 files changed, 236 insertions(+)
>  create mode 100644 
> ArmVirtPkg/CloudHvAcpiPlatformDxe/CloudHvAcpiPlatformDxe.inf
>  create mode 100644 
> ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf
>  create mode 100644 ArmVirtPkg/CloudHvAcpiPlatformDxe/CloudHvAcpi.c
>  create mode 100644 
> ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.c

(2) Unless there is a specific reason for adding both drivers in the
same patch, please split them to separate patches.

> 
> diff --git a/ArmVirtPkg/CloudHvAcpiPlatformDxe/CloudHvAcpiPlatformDxe.inf 
> b/ArmVirtPkg/CloudHvAcpiPlatformDxe/CloudHvAcpiPlatformDxe.inf
> new file mode 100644
> index ..63c74e84eb27
> --- /dev/null
> +++ b/ArmVirtPkg/CloudHvAcpiPlatformDxe/CloudHvAcpiPlatformDxe.inf
> @@ -0,0 +1,51 @@
> +## @file
> +#  OVMF ACPI Platform Driver for Cloud Hypervisor
> +#
> +#  Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.

(3) Missing ARM (C).

> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION= 0x00010005
> +  BASE_NAME  = ClhFwCfgAcpiPlatform

(4) This should be "CloudHvAcpiPlatformDxe", matching the basename of
the INF file.

> +  FILE_GUID  = 6c76e407-73f2-dc1c-938f-5d6c4691ea93
> +  MODULE_TYPE= DXE_DRIVER
> +  VERSION_STRING = 1.0
> +  ENTRY_POINT= CloudHvAcpiPlatformEntryPoint
> +
> +#
> +# The following information is for reference only and not required by the 
> build tools.
> +#
> +#  VALID_ARCHITECTURES   = IA32 X64 ARM AARCH64

(5) Do you really want this driver to be used on, say, IA32?

> +#
> +
> +[Sources]
> +  CloudHvAcpi.c
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  OvmfPkg/OvmfPkg.dec
> +
> +[LibraryClasses]
> +  BaseLib
> +  DebugLib
> +  MemoryAllocationLib
> +  OrderedCollectionLib
> +  UefiBootServicesTableLib
> +  UefiDriverEntryPoint
> +
> +[Protocols]
> +  gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
> +  gEfiPciIoProtocolGuid # PROTOCOL SOMETIMES_CONSUMED
> +
> +[Guids]
> +  gRootBridgesConnectedEventGroupGuid
> +
> +[Pcd]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiRsdpBaseAddress
> +
> +[Depex]
> +  gEfiAcpiTableProtocolGuid
> diff --git a/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf 
> b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf
> new file mode 100644
> index ..f511a4f5064c
> --- /dev/null
> +++ b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf
> @@ -0,0 +1,43 @@
> +## @file
> +# Decide whether the firmware should expose an ACPI- and/or a Device 
> Tree-based
> +# hardware description to the operating system.
> +#
> +# Copyright (c) 2017, Red Hat, Inc.

(6) ARM (C) missing.

> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +[Defines]
> +  INF_VERSION= 1.25
> +  BASE_NAME  = ClhPlatformHasAcpiDtDxe

(7) Should be "CloudHvHasAcpiDtDxe".

> +  FILE_GUID  = 71fe72f9-6dc1-199d-5054-13b4200ee88d
> +  MODULE_TYPE= DXE_DRIVER
> +  VERSION_STRING = 1.0
> +  ENTRY_POINT= PlatformHasAcpiDt
> +
> +[Sources]
> +  CloudHvHasAcpiDtDxe.c
> +
> +[Packages]
> +  ArmVirtPkg/ArmVirtPkg.dec
> +  EmbeddedPkg/EmbeddedPkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  MdePkg/MdePkg.dec
> +  OvmfPkg/OvmfPkg.dec
> +
> +[LibraryClasses]
> +  BaseLib
> +  DebugLib
> +  PcdLib
> +  UefiBootServicesTableLib
> +  UefiDriverEntryPoint
> +
> +[Guids]
> +  gEdkiiPlatformHasAcpiGuid   ## SOMETIMES_PRODUCES ## PROTOCOL
> +  gEdkiiPlatformHasDeviceTreeGuid ##

Re: [edk2-devel] [PATCH v3 5/5] StandaloneMmPkg: build for 32bit arm machines

Hello Sami,

Thanks for the catch. I missed that. My comment below.

On Tue, 18 May 2021 at 13:07, Sami Mujawar  wrote:
>
> Hi Etienne,
>
> Please find my response inline marked [SAMI].
>
> Regards,
>
> Sami Mujawar
>
> On 17/05/2021 08:40 AM, Etienne Carriere wrote:
> > This change allows to build StandaloneMmPkg components for 32bit Arm
> > StandaloneMm firmware.
> >
> > This change mainly moves AArch64/ source files to Arm/ side directory
> > for several components:  StandaloneMmCpu, StandaloneMmCoreEntryPoint
> > and StandaloneMmMemLib. The source file is built for both 32b and 64b
> > Arm targets.
> > (snip)
> > --- a/StandaloneMmPkg/StandaloneMmPkg.dsc
> > +++ b/StandaloneMmPkg/StandaloneMmPkg.dsc
> > (snip)
> > @@ -131,7 +131,7 @@
> >   #module style (EDK or EDKII) specified in 
> > [Components] section.
> >   #
> >   
> > ###
> > -[BuildOptions.AARCH64]
> > +[BuildOptions.AARCH64, BuildOptions.ARM]
> >   GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -march=armv8-a+nofp 
> > -mstrict-align
> [SAMI] Looks like I missed this in my previous review, sorry.
> Is '-march=armv8-axxx' correct here? or we need another ARM section with
> -march=armv7-a?
> Can you also check if '-mstrict-align' is right and if
> '-fno-stack-protector' is needed instead, please?
>
> I used the following setting from your edk2-platforms patch v1 4/4, file
> Platform/StandaloneMm/PlatformStandaloneMmPkg/PlatformStandaloneMmRpmb.dsc
> and was able to build on a Windows host PC using
> gcc-arm-9.2-2019.12-mingw-w64-i686-arm-none-eabi compiler.
>  [BuildOptions.ARM]
>  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -march=armv7-a
>  GCC:*_*_*_CC_FLAGS = -fno-stack-protector
> [/SAMI]

You are right.
I saw that I build with these same directive but inherited from my
edk2-platforms platform that override these.
Indeed BuildOptions.ARM must be updated.
I am preparing a patch v4 series.

Regards,
Etienne


> >   GCC:*_*_*_CC_FLAGS = -mstrict-align
> >
>


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75347): https://edk2.groups.io/g/devel/message/75347
Mute This Topic: https://groups.io/mt/82881519/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v2 2/5] MdeMoudlePkg: introduce new PCD for Acpi/rsdp

On 05/17/21 08:50, Jianyong Wu wrote:
> As there is lack of a machnism in Cloud Hypervisor to pass the base
> address of Rsdp in Acpi, so a PCD varialbe is introduced here to
> feed it.
> 
> Cc: Hao A Wu 
> Cc: Jian J Wang 
> Signed-off-by: Jianyong Wu 
> ---
>  MdeModulePkg/MdeModulePkg.dec | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
> index 148395511034..4c8baac35a9e 100644
> --- a/MdeModulePkg/MdeModulePkg.dec
> +++ b/MdeModulePkg/MdeModulePkg.dec
> @@ -910,6 +910,13 @@ [PcdsFixedAtBuild]
># @Expression 0x8001 | 
> (gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable == 
> 0x || 
> gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable <= 
> 0x0FFF)
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0|UINT64|0x30001015
>  
> +  ##
> +  # This is the physical address of rsdp which is the core struct of Acpi.
> +  # Some hypervisor may has no way to pass rsdp address to the guest, so a 
> PCD
> +  # is worth for those.
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiRsdpBaseAddress|0x0|UINT64|0x30001056
> +
>## Progress Code for OS Loader LoadImage start.
>#  PROGRESS_CODE_OS_LOADER_LOAD   = (EFI_SOFTWARE_DXE_BS_DRIVER | 
> (EFI_OEM_SPECIFIC | 0x)) = 0x03058000
># @Prompt Progress Code for OS Loader LoadImage start.
> 

This PCD is not useful enough to be placed in MdeModulePkg -- it is only
used in the next two patches, which are for ArmVirtPkg.

(1) Therefore, please add the PCD to the "ArmVirtPkg.dec" file.

(2) The PCD should arguably refer to "CloudHv" in the name.

(3) In my opinion, this patch (once reimplemented for ArmVirtPkg.dec)
should be squashed into the CloudHvAcpiPlatformDxe patch. The PCD is
being introduced *for* CloudHvAcpiPlatformDxe, and *only* for that
driver. In such cases, we usually keep the DEC modifications in the same
patch as the driver addition, assuming the PCD goes in the same package
as the driver.

(4) "some hypervisor" in the DEC comment is bogus. Please be as explicit
about the use case as possible.

Thanks
Laszlo



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75346): https://edk2.groups.io/g/devel/message/75346
Mute This Topic: https://groups.io/mt/82880900/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v2 1/5] ArmVirtPkg: Library: Memory initialization for Cloud Hypervisor

Sorry, just noticed:

On 05/19/21 08:07, Laszlo Ersek wrote:
> On 05/17/21 08:50, Jianyong Wu wrote:
>> Cloud Hypervisor is kvm based VMM implemented in rust.
>>
>> This library populates the system memory map for the
>> Cloud Hypervisor virtual platform.
>>
>> Cc: Laszlo Ersek 
>> Cc: Ard Biesheuvel 
>> Cc: Leif Lindholm 
>> Signed-off-by: Jianyong Wu 
>> ---
>>  .../CloudHvVirtMemInfoPeiLib.inf  |  47 
>>  .../CloudHvVirtMemInfoLib.c   |  94 
>>  .../CloudHvVirtMemInfoPeiLibConstructor.c | 100 ++
>>  3 files changed, 241 insertions(+)
>>  create mode 100644 
>> ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf
>>  create mode 100644 
>> ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c
>>  create mode 100644 
>> ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLibConstructor.c
>>
>> diff --git 
>> a/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf 
>> b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf
>> new file mode 100644
>> index ..71dbf9c06ccc
>> --- /dev/null
>> +++ b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.inf
>> @@ -0,0 +1,47 @@
>> +#/* @file
>> +#
>> +#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> 
> (1) New file, please refresh the end year in the (C) notice.
> 
>> +#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
>> +#
>> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
>> +#
>> +#*/
>> +
>> +[Defines]
>> +  INF_VERSION= 0x0001001A
>> +  BASE_NAME  = ClhVirtMemInfoPeiLib

(4) s/Clh/CloudHv/

Thanks
Laszlo

>> +  FILE_GUID  = 3E29D940-0591-EE6A-CAD4-223A9CF55E75
>> +  MODULE_TYPE= BASE
>> +  VERSION_STRING = 1.0
>> +  LIBRARY_CLASS  = ArmVirtMemInfoLib|PEIM
>> +  CONSTRUCTOR= CloudHvVirtMemInfoPeiLibConstructor
>> +
>> +[Sources]
>> +  CloudHvVirtMemInfoLib.c
>> +  CloudHvVirtMemInfoPeiLibConstructor.c
>> +
>> +[Packages]
>> +  ArmPkg/ArmPkg.dec
>> +  ArmVirtPkg/ArmVirtPkg.dec
>> +  EmbeddedPkg/EmbeddedPkg.dec
>> +  MdeModulePkg/MdeModulePkg.dec
>> +  MdePkg/MdePkg.dec
>> +
>> +[LibraryClasses]
>> +  ArmLib
>> +  BaseMemoryLib
>> +  DebugLib
>> +  FdtLib
>> +  PcdLib
>> +  MemoryAllocationLib
>> +
>> +[Pcd]
>> +  gArmTokenSpaceGuid.PcdFdBaseAddress
>> +  gArmTokenSpaceGuid.PcdFvBaseAddress
>> +  gArmTokenSpaceGuid.PcdSystemMemoryBase
>> +  gArmTokenSpaceGuid.PcdSystemMemorySize
>> +
>> +[FixedPcd]
>> +  gArmTokenSpaceGuid.PcdFdSize
>> +  gArmTokenSpaceGuid.PcdFvSize
>> +  gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
>> diff --git 
>> a/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c 
>> b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c
>> new file mode 100644
>> index ..69f4e6ab6cc4
>> --- /dev/null
>> +++ b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c
>> @@ -0,0 +1,94 @@
>> +/** @file
>> +
>> +  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
> 
> (2) New file, ARM (C) missing.
> 
>> +
>> +  SPDX-License-Identifier: BSD-2-Clause-Patent
>> +
>> +**/
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +// Number of Virtual Memory Map Descriptors
>> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS  5
>> +
>> +//
>> +// mach-virt's core peripherals such as the UART, the GIC and the RTC are
>> +// all mapped in the 'miscellaneous device I/O' region, which we just map
>> +// in its entirety rather than device by device. Note that it does not
>> +// cover any of the NOR flash banks or PCI resource windows.
>> +//
>> +#define MACH_VIRT_PERIPH_BASE   0x0800
>> +#define MACH_VIRT_PERIPH_SIZE   SIZE_128MB
>> +
>> +//
>> +// in cloud-hypervisor, 0x0 ~ 0x800 is reserved as normal memory for 
>> UEFI
>> +//
>> +#define CLOUDHV_UEFI_MEM_BASE   0x0
>> +#define CLOUDHV_UEFI_MEM_SIZE   0x0800
>> +
>> +/**
>> +  Return the Virtual Memory Map of your platform
>> +
>> +  This Virtual Memory Map is used by MemoryInitPei Module to initialize the 
>> MMU
>> +  on your platform.
>> +
>> +  @param[out]   VirtualMemoryMapArray of ARM_MEMORY_REGION_DESCRIPTOR
>> +describing a Physical-to-Virtual Memory
>> +mapping. This array must be ended by a
>> +zero-filled entry. The allocated memory
>> +will not be freed.
>> +
>> +**/
>> +VOID
>> +ArmVirtGetMemoryMap (
>> +  OUT ARM_MEMORY_REGION_DESCRIPTOR   **VirtualMemoryMap
>> +  )
>> +{
>> +  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
>> +
>> +  ASSERT (VirtualMemoryMap != NULL);
>> +
>> +  VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
>> +

Re: [edk2-devel] [PATCH v2 1/5] ArmVirtPkg: Library: Memory initialization for Cloud Hypervisor