Re: [edk2-devel] [PATCH v8 00/37] Enable LoongArch virtual machine in edk2
Hi Ray and Laszlo, Sorry, I was busy the past few days, so V8 was late. Ray, I *removed* your review message in patches 11, 12, 24, 15 and 16, because our adjusted the folders layout, so please review again, thanks. Laszlo, I did what you pointed out, please refer the cover letter, please review, thanks. Thanks, Chao On 2024/1/26 14:27, Chao Li wrote: This patch set will enable LoongArch virtual machine in edk2, the new LoongArch virtual machine is located in OvmfPkg/LoongArchVirt/, it is a generic platform that dose not require any actual hardware. Patch1-Patch14: Submit the common library and driver for LoongArch virtual machine and real hardware. Such as base help functions, exception handel, MMU library, multiprocessor library etc. Patch15-Patch16: Add PrePiCpuIoSize for LoongArch64. and move ArmVirtPkg two PCDs into OvmfPkg for easier use by other architectures. Patch17-Patch29: LoongArch virtual machine private code, include SEC and PEI phase code, some library and drivers. Patch30: Add LoongArchVirt's self introduction-file. Modfied modues: MdePkg, UefiCpuPkg, EmbeddedPkg, ArmVirtPkg, OvmfPkg. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=4584 PR:https://github.com/tianocore/edk2/pull/5208 **Changes from V1 to V2:** 1. Add Ray's Ack signature to patch 13. 2. Add LoongArchVirt's self introduction-file. And made a standalone patch for this change. **Changes from V2 to V3:** Compared with V2, there are 9 more patches, removed 2 libraries and 1 driver from OvmfPkg/LoongArchVrt. New patches: MdePkg: Add a new library named PeiServicesTablePointerLibReg MdePkg: Add method of LoongArch64 to PeiServicesTablePointerLibReg MdePkg: Add a PCD feature flag named PcdPciIoTranslationIsEnabled UefiCpuPkg: Add MMIO method in CpuIo2Dxe ArmVirtPkg: Enable UefiCpuPkg version CpuIo2Dxe ArmPkg: Remove ArmPciCpuIo2Dxe from ArmPkg OvmfPkg/RiscVVirt: Enable UefiCpuPkg version CpuIo2Dxe OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg ArmVirtPkg: Move the PcdTerminalTypeGuidBuffer into OvmfPkg ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg For the review opinions: 1. Add MMIO method to CpuIo2Dxe driver to accommodate more ARCH that require MMIO method, enable it on ARM, RISCV64 and LOONGARCH64. Questioner: Gerd, Sunil. 2. Move the FdtSerialProtAddressLib to OvmfPkg and enabled it on ARM and LOONGARCH64. Questioner: Gerd, Laszlo. 3. Add a new library in MdePkg named PeiServiceTablePointerLibReg for the Register Mechanism and enabled it on LOONGARCH64. Questioner: Laszlo. 4. Moved the ARM version of PlatformBootManagerLib to OvmfPkg/Library, and enabled it on ARM and LOONGARCH64. Questioner: Laszlo, Gerd. 5. Adjust the order of some inf file in ArmVirtPkg. Questioner: Sami. 6. Move the CpuMmuLib.h some architecture-specific PTE #defines into Csr.h. Questioner: Andrei. **Changes from V3 to V4:** Compared with V3, 1 patch moving ArmPciCpuIo2Dxe has been removed. Adjusted the code of the LoongArch64 CPU timer library. Rename PeiServiceTablePointerLibReg to PeiServiceTablePointerLibKs0. Fixed some typos. Remove some APIs of CpuMmuLib. For the review opinions: 1. Removed the patch that removed ArmPciCpuIo2Dxe, there are 15 platforms in edk2-platforms were affected, so wait for this patch series to be merged, then submit a patch to remove it. Questioner: Leif. 2. Renamed the PeiServiceTablePointLibReg to PeiServiceTablePointLibKs0. Currently, this library is specific to LoongArch architecture. Questioner: Laszlo, Liming. 3. Adjust some logic of LoongArch64 CPU timer library. Using the safe INT library and adjust the bit width of stable counter. Questioner: Laszlo. 4. Removed some APIs from CpuMmuLib. Change some APIs to private. Questioner: Ray. **Changes from V4 to V5:** Compared with V4, 1 patch adding PcdPciIoTranslationIsEnabled in MdePkg has been removed. Copy ArmPciCpuIo2Dxe to UefiCpuPkg and renamed it to CpuMmio2Dxe. Restore the definitions in MdePkg/Include/Protocol/DebugSupport.h, and just add some comments. For the review opinions: 1. Copy ArmPciCpuIo2Dxe to UefiCpuPkg so that more other ARCHs can use it easily. Questioner: Ray, Ard. 2. Restore the changes of MdePkg/Include/Protocol/DebugSupport.h. Questioner: Liming. 3. Ia32 X64 and LoongArch64 use a same API definition, InitializeFloatingPointUnits in CpuLib.h. Questioner: Liming. 4. Adjust API definition in CpuMmuLib.h. Questioner: Ray. **Changes from V5 to V6:** 1. Added Sunil "Reviewed-by" message to patches 20 and 21. 2. Added Bibo "Reviced-by" message to patches 27, 29, 32 and 34. 3. Added the IPI handler in SEC and PEI stage. Modified patches 11 and 15. 4. Adjust some code styles to suit CI ECC. 5. Adjust the way of AP wakeup from IPI. 6. Adjust the order between setting exceptions and copying exception handlers. **Changes from V6 to V7:** Compared with V6, 1 patch has been added. Added Bibo "Reviewed-by" message to new patches 26, 27, 29, 31, 32, 36, 37.
[edk2-devel] [PATCH v8 37/37] OvmfPkg/LoongArchVirt: Add self introduction file
Add self introduction file for LoongArch virtual machine. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Ard Biesheuvel Cc: Laszlo Ersek Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Bibo Mao Cc: Dongyan Qian Signed-off-by: Chao Li Reviewed-by: Bibo Mao --- OvmfPkg/LoongArchVirt/Readme.md | 67 + 1 file changed, 67 insertions(+) create mode 100644 OvmfPkg/LoongArchVirt/Readme.md diff --git a/OvmfPkg/LoongArchVirt/Readme.md b/OvmfPkg/LoongArchVirt/Readme.md new file mode 100644 index 00..57fc74c296 --- /dev/null +++ b/OvmfPkg/LoongArchVirt/Readme.md @@ -0,0 +1,67 @@ +# LoongArch QEMU virt platform + +## Overview + + LoongArch QEMU virt is a generic platform that dose not require any actual hardware. + The minimum required QEMU version is [8.1](https://gitlab.com/qemu-project/qemu/-/tags), the minimum required GCC version is [GCC13](https://gcc.gnu.org/gcc-13/), the minimum required Binutils version is [2.40](https://ftp.gnu.org/gnu/binutils/). + +## Prepare (X86 Linux Environment) + +### Fedora39 +Install LoongArch64 cross compiler, LoongArch system QEMU. + +yum install gcc-loongarch64-linux-gnu +yum install qemu-system-loongarch64 + +### Others X86 OS ENV + Configure cross-tools + +**Download:** + +wget https://github.com/loongson/build-tools/releases/download/2023.08.08/x86_64-cross-tools-loongarch64-binutils_2.41-gcc_13.2.0.tar.xz + +**Configure the cross-tools environment:** + +mkdir /opt/loongarch64_cross-toolchain/ +tar -vxf x86_64-cross-tools-loongarch64-binutils_2.41-gcc_13.2.0.tar.xz -C /opt/loongarch64_cross-toolchain/ +export PATH=/opt/loongarch64_cross-toolchain/cross-tools/bin:$PATH + +Note: Please obtain [the latest cross-compilation](https://github.com/loongson/build-tools) toolchains. + + Build QEMU + +git clone https://gitlab.com/qemu-project/qemu.git + +Note: Please refer to QEMU compilation rules, located in qemu/doc/system/loongarch/virt.rst. + + +## Build LoongArch QEMU virtual machine firmware + Get edk2 resouces + +git clone --recurse-submodule https://github.com/tianocore/edk2.git + + Building LoongArch QEMU virt FW with GCC + +export WORKSPACE=`pwd` +export GCC5_LOONGARCH64_PREFIX=loongarch64-unknown-linux-gnu- +export PACKAGES_PATH=$WORKSPACE/edk2 +export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools +source edk2/edksetup.sh --reconfig +make -C edk2/BaseTools +source edk2/edksetup.sh BaseTools +build -b RELEASE -t GCC5 -a LOONGARCH64 -p OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc + +## Test LoongArch QEMU virtual machine firmware +qemu-system-loongarch64 \ +-m 4G \ +-M virt \ +-smp 2 \ +-cpu la464 \ +-bios Build/LoongArchVirtQemu/RELEASE_GCC5/FV/QEMU_EFI.fd \ +-serial stdio + +## Test LoongArch QEMU virtual machine OS + +* Download ArchLinux QCOW [images](https://mirrors.pku.edu.cn/loongarch/archlinux/images) for LoongArch. + +* [Running LoongArch ArchLinux on virtual machine](https://mirrors.pku.edu.cn/loongarch/archlinux/images/README.html). -- 2.27.0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114563): https://edk2.groups.io/g/devel/message/114563 Mute This Topic: https://groups.io/mt/103971689/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v8 36/37] OvmfPkg/LoongArchVirt: Add build file
Add infrastructure files to build edk2 for LoongArch QEMU virtual machine. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Ard Biesheuvel Cc: Laszlo Ersek Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Bibo Mao Cc: Dongyan Qian Signed-off-by: Chao Li Co-authored-by: Xianglai Li Co-authored-by: Bibo Mao Reviewed-by: Bibo Mao --- OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc | 34 + OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc | 679 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf | 313 + OvmfPkg/LoongArchVirt/VarStore.fdf.inc | 67 ++ 4 files changed, 1093 insertions(+) create mode 100644 OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc create mode 100644 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc create mode 100644 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf create mode 100644 OvmfPkg/LoongArchVirt/VarStore.fdf.inc diff --git a/OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc b/OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc new file mode 100644 index 00..22373bec6a --- /dev/null +++ b/OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc @@ -0,0 +1,34 @@ +## @file +# +# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +DEFINE BLOCK_SIZE = 0x1000 + + +# FW total +DEFINE FW_BASE_ADDRESS= 0x1c00 +DEFINE FW_BLOCKS = 0x400 +DEFINE FW_SIZE= 0x40 + + +#Flash code layout +#Set Sec size in flash +DEFINE SECFV_SIZE = 0x0001 + +#Set Pei size in flash +DEFINE PEIFV_SIZE = 0x0004 + +#Set Dxe size in flash +DEFINE DXEFV_SIZE = 0x0035 + +#Set FVMAIN size +DEFINE FVMAIN_SIZE= $(SECFV_SIZE) + $(PEIFV_SIZE) +$(DXEFV_SIZE) + +#Set Memory layout +DEFINE SEC_PEI_TEMP_RAM_BASE = 0x1 +DEFINE SEC_PEI_TEMP_RAM_SIZE = 0x8 +DEFINE DEVICE_TREE_RAM_BASE = 0x10 diff --git a/OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc b/OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc new file mode 100644 index 00..f1cb36edae --- /dev/null +++ b/OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc @@ -0,0 +1,679 @@ +## @file +# +# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +# +# Defines Section - statements that will be processed to create a Makefile. +# +### +[Defines] + PLATFORM_NAME = LoongArchVirtQemu + PLATFORMPKG_NAME = LoongArchVirtQemu + PLATFORM_GUID = 7926ea52-b0dc-4ee8-ac63-341eebd84ed4 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 1.29 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES= LOONGARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf + TTY_TERMINAL = FALSE + +!include LoongArchVirt.fdf.inc + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + DEFINE TTY_TERMINAL= FALSE + DEFINE SECURE_BOOT_ENABLE = FALSE + DEFINE TPM2_ENABLE = FALSE + DEFINE TPM2_CONFIG_ENABLE = FALSE + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE = FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE= FALSE + DEFINE NETWORK_SNP_ENABLE = FALSE + DEFINE NETWORK_TLS_ENABLE = FALSE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE + DEFINE NETWORK_ISCSI_ENABLE= FALSE + +!include NetworkPkg/NetworkDefines.dsc.inc + +# +# Defines for default states. These can be changed on the command line. +# -D FLAG=VALUE + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS = -DSPEEDUP + + # + # Disable deprecated APIs. + # + GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES + +!include NetworkPkg/NetworkBuildOptions.dsc.inc + +[BuildOptions.LOONGARCH64.EDKII.SEC] + *_*_*_CC_FLAGS = + +# +# Default page size is 16K for loongarch qemu tcg +# code section separated with data section with 16K page alignment, else data +# write operation in the same page with code section will cause qemu TB flush. +# +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] +
[edk2-devel] [PATCH v8 35/37] OvmfPkg/LoongArchVirt: Support PEI phase
Platfrom PEI module for LoongArch platfrom initialization.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo Mao
Reviewed-by: Bibo Mao
---
OvmfPkg/LoongArchVirt/PlatformPei/Fv.c| 39 ++
OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c | 201 +
OvmfPkg/LoongArchVirt/PlatformPei/Platform.c | 393 ++
OvmfPkg/LoongArchVirt/PlatformPei/Platform.h | 146 +++
.../LoongArchVirt/PlatformPei/PlatformPei.inf | 72
5 files changed, 851 insertions(+)
create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/Platform.c
create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/Platform.h
create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/PlatformPei.inf
diff --git a/OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
b/OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
new file mode 100644
index 00..d46326f135
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
@@ -0,0 +1,39 @@
+/** @file
+ Build FV related hobs for platform.
+
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include "Platform.h"
+
+/**
+ Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+ and DXE know about them.
+
+ @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
+**/
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
+
+ //
+ // Create a memory allocation HOB for the PEI FV.
+ //
+ BuildMemoryAllocationHob (
+FixedPcdGet64 (PcdOvmfSecPeiTempRamBase),
+FixedPcdGet32 (PcdOvmfSecPeiTempRamSize),
+EfiBootServicesData
+);
+
+ return EFI_SUCCESS;
+}
diff --git a/OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
b/OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
new file mode 100644
index 00..9c90413524
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
@@ -0,0 +1,201 @@
+/** @file
+ Memory Detection for Virtual Machines.
+
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include
+
+//
+// The Library classes this module consumes
+//
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "Platform.h"
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (128)
+#define LOONGARCH_FW_RAM_TOPBASE_256MB
+
+/**
+ Publish PEI core memory
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+**/
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Base;
+ UINT64 Size;
+ UINT64 RamTop;
+
+ //
+ // Determine the range of memory to use during PEI
+ //
+ Base = FixedPcdGet64 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32
(PcdOvmfSecPeiTempRamSize);
+ RamTop = LOONGARCH_FW_RAM_TOP;
+ Size = RamTop - Base;
+
+ //
+ // Publish this memory to the PEI Core
+ //
+ Status = PublishSystemMemory (Base, Size);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "Publish Memory Initialize done.\n"));
+ return Status;
+}
+
+/**
+ Peform Memory Detection
+ Publish system RAM and reserve memory regions
+**/
+VOID
+InitializeRamRegions (
+ VOID
+ )
+{
+ EFI_STATUSStatus;
+ FIRMWARE_CONFIG_ITEM FwCfgItem;
+ UINTN FwCfgSize;
+ MEMMAP_ENTRY MemoryMapEntry;
+ MEMMAP_ENTRY *StartEntry;
+ MEMMAP_ENTRY *pEntry;
+ UINTN Processed;
+
+ Status = QemuFwCfgFindFile ("etc/memmap", , );
+ if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/memmap error Status %d \n", __func__,
__LINE__, Status));
+return;
+ }
+
+ if (FwCfgSize % sizeof MemoryMapEntry != 0) {
+DEBUG ((DEBUG_ERROR, "no MemoryMapEntry FwCfgSize:%d\n", FwCfgSize));
+return;
+ }
+
+ QemuFwCfgSelectItem (FwCfgItem);
+ StartEntry = AllocatePages (EFI_SIZE_TO_PAGES (FwCfgSize));
+ QemuFwCfgReadBytes (FwCfgSize, StartEntry);
+ for (Processed = 0; Processed < (FwCfgSize / sizeof MemoryMapEntry);
Processed++) {
+pEntry = StartEntry + Processed;
+if (pEntry->Length == 0) {
+ continue;
+}
+
+DEBUG ((DEBUG_INFO, "MemmapEntry Base %p length %p type %d\n",
pEntry->BaseAddr, pEntry->Length, pEntry->Type));
+if (pEntry->Type != EfiAcpiAddressRangeMemory) {
+ continue;
+}
+
+AddMemoryRangeHob (pEntry->BaseAddr, pEntry->BaseAddr + pEntry->Length);
+ }
+
+ //
+ // When 0 address protection is enabled,
+ // 0-4k memory needs to be preallocated to
[edk2-devel] [PATCH v8 33/37] OvmfPkg/LoongArchVirt: Add reset system library
This library provides interface related to restart and shudown the
LoongArch64 virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo Mao
Reviewed-by: Bibo Mao
---
.../BaseResetSystemAcpiGed.c | 148 ++
.../BaseResetSystemAcpiGedLib.inf | 36 +++
.../DxeResetSystemAcpiGed.c | 259 ++
.../DxeResetSystemAcpiGedLib.inf | 41 +++
.../ResetSystemAcpiLib/ResetSystemAcpiGed.c | 125 +
.../ResetSystemAcpiLib/ResetSystemAcpiGed.h | 23 ++
6 files changed, 632 insertions(+)
create mode 100644
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGedLib.inf
create mode 100644
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGed.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGedLib.inf
create mode 100644
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.h
diff --git
a/OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
b/OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
new file mode 100644
index 00..0d94a62a38
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
@@ -0,0 +1,148 @@
+/** @file
+ Base ResetSystem library implementation.
+
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include "ResetSystemAcpiGed.h"
+
+/**
+ Get configuration item data by the firmware configuration file name.
+
+ @param[in] Name - Name of file to look up.
+
+ @returnVOID* The Pointer of Value of Firmware Configuration item
read.
+**/
+VOID *
+GetFwCfgData (
+ CONST CHAR8 *Name
+ )
+{
+ FIRMWARE_CONFIG_ITEM FwCfgItem;
+ EFI_STATUSStatus;
+ UINTN FwCfgSize;
+ VOID *Data;
+
+ Status = QemuFwCfgFindFile (Name, , );
+ if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "%a %d read %s error Status %d \n", __func__,
__LINE__, Name, Status));
+return NULL;
+ }
+
+ Data = AllocatePool (FwCfgSize);
+ if (Data == NULL) {
+return NULL;
+ }
+
+ QemuFwCfgSelectItem (FwCfgItem);
+ QemuFwCfgReadBytes (FwCfgSize, Data);
+
+ return Data;
+}
+
+/**
+ Find the power manager related info from ACPI table
+
+ @retval RETURN_SUCCESS Successfully find out all the required
information.
+ @retval RETURN_NOT_FOUND Failed to find the required info.
+**/
+STATIC EFI_STATUS
+GetPowerManagerByParseAcpiInfo (
+ VOID
+ )
+{
+ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt = NULL;
+ EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp = NULL;
+ EFI_ACPI_DESCRIPTION_HEADER *Xsdt = NULL;
+ EFI_ACPI_DESCRIPTION_HEADER *Rsdt = NULL;
+ VOID *AcpiTables = NULL;
+ UINT32*Entry32= NULL;
+ UINTN Entry32Num;
+ UINT32*Signature = NULL;
+ UINTN Idx;
+
+ Rsdp = GetFwCfgData ("etc/acpi/rsdp");
+ if (Rsdp == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/rsdp error \n", __func__,
__LINE__));
+return RETURN_NOT_FOUND;
+ }
+
+ AcpiTables = GetFwCfgData ("etc/acpi/tables");
+ if (AcpiTables == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/tables error \n", __func__,
__LINE__));
+FreePool (Rsdp);
+return RETURN_NOT_FOUND;
+ }
+
+ Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +
Rsdp->RsdtAddress);
+ Entry32= (UINT32 *)(Rsdt + 1);
+ Entry32Num = (Rsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+ for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+ Fadt = (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+ DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));
+ goto Done;
+}
+ }
+
+ Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +
Rsdp->XsdtAddress);
+ Entry32= (UINT32 *)(Xsdt + 1);
+ Entry32Num = (Xsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+ for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature ==
[edk2-devel] [PATCH v8 34/37] OvmfPkg/LoongArchVirt: Support SEC phase
Add SEC code for LoongArch virtual machine. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Ard Biesheuvel Cc: Laszlo Ersek Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Bibo Mao Cc: Dongyan Qian Signed-off-by: Chao Li Co-authored-by: Xianglai Li Co-authored-by: Bibo Mao Reviewed-by: Bibo Mao --- OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S | 184 +++ OvmfPkg/LoongArchVirt/Sec/SecMain.c | 507 ++ OvmfPkg/LoongArchVirt/Sec/SecMain.inf | 53 ++ 3 files changed, 744 insertions(+) create mode 100644 OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S create mode 100644 OvmfPkg/LoongArchVirt/Sec/SecMain.c create mode 100644 OvmfPkg/LoongArchVirt/Sec/SecMain.inf diff --git a/OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S b/OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S new file mode 100644 index 00..f3fa79289d --- /dev/null +++ b/OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S @@ -0,0 +1,184 @@ +#-- +# +# Start for Loongson LoongArch processor +# +# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Glossary: +#- CSR - CPU Status Register +#- EBASE - Exception Base Address +#-- +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include +#include +#include + +#define BOOTCORE_ID 0 +// +// For coding convenience, define the maximum valid +// LoongArch exception. +// Since UEFI V2.11, it will be present in DebugSupport.h. +// +#define MAX_LOONGARCH_EXCEPTION 64 + +ASM_GLOBAL ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + /* Disable global interrupt */ + bl DisableInterrupts + + /* Disable all local interrupt */ + li.w $a0, 0x1FFF + bl DisableLocalInterrupts + + /* Read physical cpu number id */ + bl GetApicId + li.d $t0, BOOTCORE_ID //0 + bne $a0, $t0, SlaveMain + + /* Set BSP stack */ + li.d $t0, FixedPcdGet64(PcdOvmfSecPeiTempRamBase) + FixedPcdGet32(PcdOvmfSecPeiTempRamSize) # stack base + move $sp, $t0 + addi.d $sp, $sp, -0x8 + + /* Load the exception vector base address */ + li.d $s0, FixedPcdGet64(PcdCpuExceptionVectorBaseAddress) + + /* Construct SEC and PEI step exception environment */ + la.pcrel $a1, ExceptionEntryStart + la.pcrel $t0, ExceptionEntryEnd + sub.d$a2, $t0, $a1 + li.w $t0, (MAX_LOONGARCH_EXCEPTION + MAX_LOONGARCH_INTERRUPT) * 512 + bgeu $a2, $t0, DeadLoop + move $a0, $s0 + bl CopyMem + + /* Configure BSP reset ebase */ + move $a0, $s0 + bl SetExceptionBaseAddress + +CallEntry: + /* Call C function make sure parameter true */ + li.d $a0, FixedPcdGet64(PcdOvmfFdBaseAddress) # FW base + addi.d $a1, $sp, 0x8 + bl SecCoreStartupWithStack +# End of _ModuleEntryPoint + +ASM_PFX(ClearMailBox): + /* Clear mailbox */ + li.d $t1, LOONGARCH_IOCSR_MBUF3 + iocsrwr.d $zero, $t1 + li.d $t1, LOONGARCH_IOCSR_MBUF2 + iocsrwr.d $zero, $t1 + li.d $t1, LOONGARCH_IOCSR_MBUF1 + iocsrwr.d $zero, $t1 + li.d $t1, LOONGARCH_IOCSR_MBUF0 + iocsrwr.d $zero, $t1 + jirl $zero, $ra, 0 +# End of ClearMailBox + +ASM_PFX(EnableIPI): + /* Enable IPI interrupt */ + li.w $t1, BIT12 + csrxchg $t1, $t1, LOONGARCH_CSR_ECFG + + li.w $t2, 0xU + li.d $t1, LOONGARCH_IOCSR_IPI_EN + iocsrwr.w $t2, $t1 + jirl $zero, $ra, 0 +# End of EeableIPI + +#/** +# Get APIC ID for every CPU. +# +# @param NULL +# @return APICID +# +# UINTN +# EFI_API +# GetApicId ( +# VOID +# ) +#**/ +ASM_PFX(GetApicId): + csrrd $a0, LOONGARCH_CSR_CPUNUM + andi $a0, $a0, 0x3ff + jirl $zero, $ra, 0 +# End of GetApicId + +ASM_PFX(ApInitStack): + li.d $t1, SIZE_1KB + csrrd $t0, LOONGARCH_CSR_TMID + mul.d $t1, $t0, $t1 + li.d $t2, FixedPcdGet32(PcdCpuMaxLogicalProcessorNumber) + bgeu $t0, $t2, DeadLoop + li.d $t0, FixedPcdGet64(PcdOvmfSecPeiTempRamBase) + FixedPcdGet32(PcdOvmfSecPeiTempRamSize) - SIZE_64KB + sub.d $sp, $t0, $t1 + addi.d $sp, $sp, -0x8 + jirl $zero, $ra, 0 +# End of ApInitStack + +ASM_PFX(SlaveMain): + /* Set AP exception handle in flash */ + la.pcrel $a0, ApException + blSetExceptionBaseAddress + + /* Clean up local mail box and open INT */ + blClearMailBox + blEnableIPI + blEnableInterrupts + +WaitForWake: + /* Wait for wakeup */ + blCpuSleep + b WaitForWake +# End of SlaveMain + +.align 12 +ASM_PFX(ApException): + csrrd $t0, LOONGARCH_CSR_ESTAT + srli.d$t0, $t0, 12 + andi $t0, $t0, 0x1 + beqz $t0, DeadLoop + + li.d $t0, LOONGARCH_IOCSR_IPI_STATUS + iocsrrd.w $t1, $t0 + li.d $t0, LOONGARCH_IOCSR_IPI_CLEAR + iocsrwr.w $t1, $t0 + + /* Read mail buf and jump to specified entry
[edk2-devel] [PATCH v8 32/37] OvmfPkg/LoongArchVirt: Add FdtQemuFwCfgLib
This library for PEI phase, and obtains the QemuFwCfg base address by
directly parsing the FDT, reads and writes the data in QemuFwCfg by
operating on the QemuFwCfg base address.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo Mao
Reviewed-by: Bibo Mao
---
.../FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c | 504 ++
.../FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.inf| 42 ++
.../FdtQemuFwCfgLib/QemuFwCfgLibInternal.h| 73 +++
.../Library/FdtQemuFwCfgLib/QemuFwCfgPei.c| 117
4 files changed, 736 insertions(+)
create mode 100644
OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.inf
create mode 100644
OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/QemuFwCfgLibInternal.h
create mode 100644 OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/QemuFwCfgPei.c
diff --git a/OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
b/OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
new file mode 100644
index 00..a1f114b327
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
@@ -0,0 +1,504 @@
+/** @file
+
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+- FwCfg - firmWare Configure
+- CTL - Control
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "QemuFwCfgLibInternal.h"
+
+EFI_GUID mFwCfgSelectorAddressGuid = FW_CONFIG_SELECTOR_ADDRESS_HOB_GUID;
+EFI_GUID mFwCfgDataAddressGuid = FW_CONFIG_DATA_ADDRESS_HOB_GUID;
+
+STATIC UINTN mFwCfgSelectorAddress;
+STATIC UINTN mFwCfgDataAddress;
+
+/**
+ To get firmware configure selector address.
+
+ @param VOID
+
+ @retval firmware configure selector address
+**/
+UINTN
+EFIAPI
+QemuGetFwCfgSelectorAddress (
+ VOID
+ )
+{
+ UINTN FwCfgSelectorAddress;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *DataInHob;
+
+ FwCfgSelectorAddress = mFwCfgSelectorAddress;
+ GuidHob = NULL;
+ DataInHob= NULL;
+
+ if (FwCfgSelectorAddress == 0) {
+GuidHob = GetFirstGuidHob ();
+DataInHob= GET_GUID_HOB_DATA (GuidHob);
+FwCfgSelectorAddress = (UINT64)(*(UINTN *)DataInHob);
+ }
+
+ return FwCfgSelectorAddress;
+}
+
+/**
+ To get firmware configure Data address.
+
+ @param VOID
+
+ @retval firmware configure data address
+**/
+UINTN
+EFIAPI
+QemuGetFwCfgDataAddress (
+ VOID
+ )
+{
+ UINTN FwCfgDataAddress;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *DataInHob;
+
+ FwCfgDataAddress = mFwCfgDataAddress;
+ GuidHob = NULL;
+ DataInHob= NULL;
+
+ if (FwCfgDataAddress == 0) {
+GuidHob = GetFirstGuidHob ();
+DataInHob= GET_GUID_HOB_DATA (GuidHob);
+FwCfgDataAddress = (UINT64)(*(UINTN *)DataInHob);
+ }
+
+ return FwCfgDataAddress;
+}
+
+/**
+ Selects a firmware configuration item for reading.
+
+ Following this call, any data read from this item will start from
+ the beginning of the configuration item's data.
+
+ @param[in] QemuFwCfgItem - Firmware Configuration item to read
+**/
+VOID
+EFIAPI
+QemuFwCfgSelectItem (
+ IN FIRMWARE_CONFIG_ITEM QemuFwCfgItem
+ )
+{
+ UINTN FwCfgSelectorAddress;
+
+ FwCfgSelectorAddress = QemuGetFwCfgSelectorAddress ();
+ MmioWrite16 (FwCfgSelectorAddress, SwapBytes16
((UINT16)(UINTN)QemuFwCfgItem));
+}
+
+/**
+ Slow READ_BYTES_FUNCTION.
+
+ @param[in] The size of the data to be read.
+ @param[in] BufferThe buffer that stores the readout data.
+**/
+VOID
+EFIAPI
+MmioReadBytes (
+ IN UINTN Size,
+ IN VOID *Buffer OPTIONAL
+ )
+{
+ UINTN Left;
+ UINT8 *Ptr;
+ UINT8 *End;
+ UINTN FwCfgDataAddress;
+
+ Left = Size & 7;
+
+ Size -= Left;
+ Ptr = Buffer;
+ End = Ptr + Size;
+
+ FwCfgDataAddress = QemuGetFwCfgDataAddress ();
+ while (Ptr < End) {
+*(UINT64 *)Ptr = MmioRead64 (FwCfgDataAddress);
+Ptr += 8;
+ }
+
+ if (Left & 4) {
+*(UINT32 *)Ptr = MmioRead32 (FwCfgDataAddress);
+Ptr += 4;
+ }
+
+ if (Left & 2) {
+*(UINT16 *)Ptr = MmioRead16 (FwCfgDataAddress);
+Ptr += 2;
+ }
+
+ if (Left & 1) {
+*Ptr = MmioRead8 (FwCfgDataAddress);
+ }
+}
+
+/**
+ Slow WRITE_BYTES_FUNCTION.
+
+ @param[in] The size of the data to be write.
+ @param[in] BufferThe buffer that stores the writein data.
+**/
+VOID
+EFIAPI
+MmioWriteBytes (
+ IN UINTN Size,
+ IN VOID *Buffer OPTIONAL
+ )
+{
+ UINTN Idx;
+ UINTN FwCfgDataAddress;
+
+ FwCfgDataAddress = QemuGetFwCfgDataAddress ();
+
[edk2-devel] [PATCH v8 31/37] OvmfPkg/LoongArchVirt: Add NorFlashQemuLib
Add NorFlashQemuLib for LoongArch, it is referenced from ArmVirtPkg.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo Mao
Reviewed-by: Bibo Mao
---
.../Library/NorFlashQemuLib/NorFlashQemuLib.c | 140 ++
.../NorFlashQemuLib/NorFlashQemuLib.inf | 43 ++
2 files changed, 183 insertions(+)
create mode 100644
OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.inf
diff --git a/OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
b/OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
new file mode 100644
index 00..ae9af09c4c
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
@@ -0,0 +1,140 @@
+/** @file
+
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+
+#include
+
+#define QEMU_NOR_BLOCK_SIZE SIZE_128KB
+
+EFI_STATUS
+VirtNorFlashPlatformInitialization (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+STATIC VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevices;
+
+EFI_STATUS
+VirtNorFlashPlatformGetDevices (
+ OUT VIRT_NOR_FLASH_DESCRIPTION **NorFlashDescriptions,
+ OUT UINT32 *Count
+ )
+{
+ FDT_CLIENT_PROTOCOL *FdtClient;
+ INT32Node;
+ EFI_STATUS Status;
+ EFI_STATUS FindNodeStatus;
+ CONST UINT32 *Reg;
+ UINT32 PropSize;
+ UINT64 Base;
+ UINT64 Size;
+
+ Status = gBS->LocateProtocol (
+ ,
+ NULL,
+ (VOID **)
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ FindNodeStatus = FdtClient->FindCompatibleNode (
+FdtClient,
+"cfi-flash",
+
+);
+ ASSERT_EFI_ERROR (FindNodeStatus);
+
+ Status = FdtClient->GetNodeProperty (
+FdtClient,
+Node,
+"reg",
+(CONST VOID **),
+
+);
+ if (EFI_ERROR (Status)) {
+DEBUG ((
+ DEBUG_ERROR,
+ "%a: GetNodeProperty () failed (Status == %r)\n",
+ __func__,
+ Status
+ ));
+return Status;
+ }
+
+ ASSERT ((PropSize % (4 * sizeof (UINT32))) == 0);
+
+ if (PropSize < (4 * sizeof (UINT32))) {
+DEBUG ((
+ DEBUG_ERROR,
+ "%a: reg node size(%d) is too small \n",
+ __func__,
+ PropSize
+ ));
+return EFI_NOT_FOUND;
+ }
+
+ Base = SwapBytes64 (ReadUnaligned64 ((VOID *)[0]));
+ Size = SwapBytes64 (ReadUnaligned64 ((VOID *)[2]));
+
+ mNorFlashDevices.DeviceBaseAddress = (UINTN)Base;
+ mNorFlashDevices.RegionBaseAddress = (UINTN)Base;
+ mNorFlashDevices.Size = (UINTN)Size;
+ mNorFlashDevices.BlockSize = QEMU_NOR_BLOCK_SIZE;
+
+ Status = PcdSet32S (PcdFlashNvStorageVariableBase, Base);
+ ASSERT_EFI_ERROR (Status);
+
+ /*
+ * Base is the value of PcdFlashNvStorageVariableBase,
+ * PcdFlashNvStorageFtwWorkingBase can be got by
+ * PcdFlashNvStorageVariableBase + PcdFlashNvStorageVariableSize
+ */
+ Base += PcdGet32 (PcdFlashNvStorageVariableSize);
+ Status = PcdSet32S (PcdFlashNvStorageFtwWorkingBase, Base);
+ ASSERT_EFI_ERROR (Status);
+
+ /*
+ * Now,Base is the value of PcdFlashNvStorageFtwWorkingBase,
+ * PcdFlashNvStorageFtwSpareBase can be got by
+ * PcdFlashNvStorageFtwWorkingBase + PcdFlashNvStorageFtwWorkingSize.
+ */
+ Base += PcdGet32 (PcdFlashNvStorageFtwWorkingSize);
+ Status = PcdSet32S (PcdFlashNvStorageFtwSpareBase, Base);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // UEFI takes ownership of the NOR flash, and exposes its functionality
+ // through the UEFI Runtime Services GetVariable, SetVariable, etc. This
+ // means we need to disable it in the device tree to prevent the OS from
+ // attaching its device driver as well.
+ // Note that this also hides other flash banks, but the only other flash
+ // bank we expect to encounter is the one that carries the UEFI executable
+ // code, which is not intended to be guest updatable, and is usually backed
+ // in a readonly manner by QEMU anyway.
+ //
+ Status = FdtClient->SetNodeProperty (
+FdtClient,
+Node,
+"status",
+"disabled",
+sizeof ("disabled")
+);
+ if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_WARN, "Failed to set NOR flash status to 'disabled'\n"));
+ }
+
+ *NorFlashDescriptions =
+
[edk2-devel] [PATCH v8 30/37] OvmfPkg/LoongArchVirt: Add real time clock library
This library is provides real time clock for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authored-by: Xianglai Li
Reviewed-by: Bibo Mao
---
.../DxeLsRealTimeClockLib.c | 327 ++
.../DxeLsRealTimeClockLib.inf | 41 +++
.../LsRealTimeClockLib/LsRealTimeClock.h | 47 +++
.../PeiLsRealTimeClockLib.c | 31 ++
.../PeiLsRealTimeClockLib.inf | 29 ++
5 files changed, 475 insertions(+)
create mode 100644
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.inf
create mode 100644
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/LsRealTimeClock.h
create mode 100644
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/PeiLsRealTimeClockLib.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/PeiLsRealTimeClockLib.inf
diff --git
a/OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
b/OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
new file mode 100644
index 00..e990728069
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
@@ -0,0 +1,327 @@
+/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "LsRealTimeClock.h"
+
+STATIC BOOLEANmInitialized = FALSE;
+STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
+STATIC UINTN mRtcBase;
+
+/*
+ Enable Real-time clock.
+
+ @param VOID
+
+ @retval VOID
+ */
+VOID
+InitRtc (
+ VOID
+ )
+{
+ UINTN Val;
+ EFI_HOB_GUID_TYPE *GuidHob = NULL;
+ VOID *DataInHob = NULL;
+
+ if (!mInitialized) {
+/* Enable rtc */
+GuidHob = GetFirstGuidHob ();
+if (GuidHob) {
+ DataInHob = GET_GUID_HOB_DATA (GuidHob);
+ mRtcBase = (UINT64)(*(UINTN *)DataInHob);
+ Val = MmioRead32 (mRtcBase + RTC_CTRL_REG);
+ Val |= TOY_ENABLE_BIT | OSC_ENABLE_BIT;
+ MmioWrite32 (mRtcBase + RTC_CTRL_REG, Val);
+ mInitialized = TRUE;
+} else {
+ DebugPrint (EFI_D_INFO, "RTC register address not found!\n");
+ ASSERT (FALSE);
+}
+ }
+}
+
+/**
+ Returns the current time and date information, and the time-keeping
capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of
the current time.
+ @param Capabilities An optional pointer to a buffer to receive
the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESSThe operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to
hardware error.
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an
authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ UINT32 Val;
+
+ // Ensure Time is a valid pointer
+ if (Time == NULL) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ Val= MmioRead32 (mRtcBase + TOY_READ1_REG);
+ Time->Year = Val + 1900;
+
+ Val = MmioRead32 (mRtcBase + TOY_READ0_REG);
+ Time->Month = (Val >> TOY_MON_SHIFT) & TOY_MON_MASK;
+ Time->Day= (Val >> TOY_DAY_SHIFT) & TOY_DAY_MASK;
+ Time->Hour = (Val >> TOY_HOUR_SHIFT) & TOY_HOUR_MASK;
+ Time->Minute = (Val >> TOY_MIN_SHIFT) & TOY_MIN_MASK;
+ Time->Second = (Val >> TOY_SEC_SHIFT) & TOY_SEC_MASK;
+ Time->Nanosecond = 0;
+ return EFI_SUCCESS;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware
error.
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ UINT32 Val;
+
+ // Initialize the hardware if not already done
+
+ Val = 0;
+ Val |= (Time->Second << TOY_SEC_SHIFT);
+ Val |= (Time->Minute << TOY_MIN_SHIFT);
+ Val |= (Time->Hour << TOY_HOUR_SHIFT);
+ Val |= (Time->Day<< TOY_DAY_SHIFT);
+ Val |= (Time->Month << TOY_MON_SHIFT);
+ MmioWrite32 (mRtcBase + TOY_WRITE0_REG, Val);
+
+ Val = Time->Year - 1900;
+ MmioWrite32 (mRtcBase + TOY_WRITE1_REG, Val);
+
[edk2-devel] [PATCH v8 29/37] OvmfPkg/LoongArchVirt: Add the early serial port output library
Add a early serial port output library into LoongArchVirt that named
EarlyFdtSerialPortLib16550, this library is referenced from
MdeModulePkg.
This library is used in the PEI phase. Since the serial port address can
not be saved in memory of the LoongArch QEMU virtual machine in the PEI
phase, the serial prot base address will be obtained from the FDT before
each output.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Reviewed-by: Bibo Mao
---
.../EarlyFdtSerialPortLib16550.c | 815 ++
.../EarlyFdtSerialPortLib16550.inf| 46 +
2 files changed, 861 insertions(+)
create mode 100644
OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.inf
diff --git
a/OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
b/OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
new file mode 100644
index 00..8cc108501c
--- /dev/null
+++
b/OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
@@ -0,0 +1,815 @@
+/** @file
+ 16550 UART Serial Port library functions
+
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+//
+// PCI Defintions.
+//
+#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF 0// LCR_DLAB = 0
+#define R_UART_TXBUF 0// LCR_DLAB = 0
+#define R_UART_BAUD_LOW0// LCR_DLAB = 1
+#define R_UART_BAUD_HIGH 1// LCR_DLAB = 1
+#define R_UART_IER 1// LCR_DLAB = 0
+#define R_UART_FCR 2
+#define B_UART_FCR_FIFOE BIT0
+#define B_UART_FCR_FIFO64 BIT5
+#define R_UART_LCR 3
+#define B_UART_LCR_DLABBIT7
+#define R_UART_MCR 4
+#define B_UART_MCR_DTRCBIT0
+#define B_UART_MCR_RTS BIT1
+#define R_UART_LSR 5
+#define B_UART_LSR_RXRDY BIT0
+#define B_UART_LSR_TXRDY BIT5
+#define B_UART_LSR_TEMTBIT6
+#define R_UART_MSR 6
+#define B_UART_MSR_CTS BIT4
+#define B_UART_MSR_DSR BIT5
+#define B_UART_MSR_RI BIT6
+#define B_UART_MSR_DCD BIT7
+
+/**
+ Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value
is read from
+ MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O
space. The
+ parameter Offset is added to the base address of the 16550 registers that is
specified
+ by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO
space access
+ width and defaults to 8 bit access, and supports 8 or 32 bit access.
+
+ @param BaseThe base address register of UART device.
+ @param Offset The offset of the 16550 register to read.
+
+ @return The value read from the 16550 register.
+**/
+UINT8
+SerialPortReadRegister (
+ UINTN Base,
+ UINTN Offset
+ )
+{
+ if (PcdGetBool (PcdSerialUseMmio)) {
+if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
+ return (UINT8)MmioRead32 (Base + Offset * PcdGet32
(PcdSerialRegisterStride));
+}
+
+return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+ } else {
+return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+ }
+}
+
+/**
+ Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value
is written to
+ MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O
space. The
+ parameter Offset is added to the base address of the 16550 registers that is
specified
+ by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO
space access
+ width and defaults to 8 bit access, and supports 8 or 32 bit access.
+
+ @param BaseThe base address register of UART device.
+ @param Offset The offset of the 16550 register to write.
+ @param Value The value to write to the 16550 register specified by Offset.
+
+ @return The value written to the 16550 register.
+**/
+UINT8
+SerialPortWriteRegister (
+ UINTN Base,
+ UINTN Offset,
+ UINT8 Value
+ )
+{
+ if (PcdGetBool (PcdSerialUseMmio)) {
+if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
+ return (UINT8)MmioWrite32 (Base + Offset * PcdGet32
(PcdSerialRegisterStride), (UINT8)Value);
+}
+
+return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride),
Value);
+ } else {
+return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride),
Value);
+ }
+}
+
+/**
+ Retrieve the I/O or MMIO base address register for the PCI UART device.
+
+ This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in
PCI
[edk2-devel] [PATCH v8 28/37] OvmfPkg/LoongArchVirt: Add serial port hook library
Add a serial port hook library in LoongArchVirt named
Fdt16550SerialProtHookLib, this library is referenced from ArmVirtPkg.
LoongArch QEMU virtual machine uses register of LOONGARCH_CSR_KS1 to
transfer serial port base addres from the PEI phase to the DXE phase.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Reviewed-by: Bibo Mao
---
.../EarlyFdt16550SerialPortHookLib.c | 52 +++
.../EarlyFdt16550SerialPortHookLib.inf| 37 +
.../Fdt16550SerialPortHookLib.c | 39 ++
.../Fdt16550SerialPortHookLib.inf | 33
.../Fdt16550SerialPortHookLib.uni | 14 +
5 files changed, 175 insertions(+)
create mode 100644
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
create mode 100644
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.inf
create mode 100644
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.uni
diff --git
a/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
new file mode 100644
index 00..9f1fcc970a
--- /dev/null
+++
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
@@ -0,0 +1,52 @@
+/** @file
+ PEI Phase Early Platform Hook Library instance for 16550 Uart.
+
+ Copyright (c) 2020 - 2023, Arm Ltd. All rights reserved.
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+
+/** Platform hook to retrieve the 16550 UART base address from the platform
+Device tree and store it in the reigster LOONGARCH_CSR_KS1.
+
+ @retval RETURN_SUCCESSSuccess.
+ @retval RETURN_INVALID_PARAMETER A parameter was invalid.
+ @retval RETURN_NOT_FOUND Serial port information not found.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+ RETURN_STATUS Status;
+ VOID *DeviceTreeBase;
+ UINT64 SerialConsoleAddress;
+
+ if (PcdGet64 (PcdSerialRegisterBase) != 0) {
+return RETURN_SUCCESS;
+ }
+
+ DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAddress);
+ if (DeviceTreeBase == NULL) {
+return RETURN_NOT_FOUND;
+ }
+
+ Status = FdtSerialGetConsolePort (DeviceTreeBase, );
+ if (RETURN_ERROR (Status)) {
+return Status;
+ }
+
+ CsrWrite (LOONGARCH_CSR_KS1, (UINTN)SerialConsoleAddress);
+
+ return RETURN_SUCCESS;
+}
diff --git
a/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
new file mode 100644
index 00..55b0c03a01
--- /dev/null
+++
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
@@ -0,0 +1,37 @@
+## @file
+# PEI Phase Early Platform Hook Library instance for 16550 Uart.
+#
+# Copyright (c) 2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 1.29
+ BASE_NAME = EarlyFdt16550SerialPortHookLib
+ MODULE_UNI_FILE= Fdt16550SerialPortHookLib.uni
+ FILE_GUID = 6A5FEBCB-C676-A7C1-A96C-B79D4860EEC5
+ MODULE_TYPE= PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformHookLib|SEC PEI_CORE PEIM
+
+[Sources]
+ EarlyFdt16550SerialPortHookLib.c
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ FdtLib
+ FdtSerialPortAddressLib
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
+
+[Pcd]
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git
a/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
new file mode 100644
index 00..fd188f75b8
--- /dev/null
+++
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
@@ -0,0 +1,39 @@
+/** @file
+ Platform Hook Library instance for 16550 Uart.
+
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ Copyright
[edk2-devel] [PATCH v8 26/37] OvmfPkg/LoongArchVirt: Add stable timer driver
Add a CPU timer driver named StableTimerDxe, which proviedes
EFI_TIMER_ARCH_PROTOCOL for LoongArch.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Reviewed-by: Bibo Mao
---
.../Drivers/StableTimerDxe/Timer.c| 381 ++
.../Drivers/StableTimerDxe/Timer.h| 127 ++
.../Drivers/StableTimerDxe/TimerDxe.inf | 41 ++
3 files changed, 549 insertions(+)
create mode 100644 OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
create mode 100644 OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.h
create mode 100644 OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/TimerDxe.inf
diff --git a/OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
b/OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
new file mode 100644
index 00..0e0f10970a
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
@@ -0,0 +1,381 @@
+/** @file
+ Timer Architectural Protocol as defined in the DXE CIS
+
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "Timer.h"
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLE mTimerHandle = NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL mTimer = {
+ TimerDriverRegisterHandler,
+ TimerDriverSetTimerPeriod,
+ TimerDriverGetTimerPeriod,
+ TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+/**
+ Sets the counter value for timer.
+
+ @param CountThe 16-bit counter value to program into stable timer.
+
+ @retval VOID
+**/
+VOID
+SetPitCount (
+ IN UINT64 Count
+ )
+{
+ if (Count <= 4) {
+return;
+ }
+
+ Count &= LOONGARCH_CSR_TMCFG_TIMEVAL;
+ Count |= LOONGARCH_CSR_TMCFG_EN | LOONGARCH_CSR_TMCFG_PERIOD;
+ CsrWrite (LOONGARCH_CSR_TMCFG, Count);
+}
+
+/**
+ Timer Interrupt Handler.
+
+ @param InterruptTypeThe type of interrupt that occurred
+ @param SystemContextA pointer to the system context when the interrupt
occurred
+
+ @retval VOID
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ EFI_TPL OriginalTPL;
+
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+ //
+ // Clear interrupt.
+ //
+ CsrWrite (LOONGARCH_CSR_TINTCLR, 0x1);
+
+ if (mTimerNotifyFunction != NULL) {
+//
+// @bug : This does not handle missed timer interrupts
+//
+mTimerNotifyFunction (mTimerPeriod);
+ }
+
+ gBS->RestoreTPL (OriginalTPL);
+}
+
+/**
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a
handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not
registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires.
This
+ function executes at TPL_HIGH_LEVEL. The DXE Core
will
+ register a handler for the timer interrupt, so it
can know
+ how much time has passed. This information is used
to
+ signal timer based events. NULL will unregister the
handler.
+
+ @retvalEFI_SUCCESSThe timer handler was registered.
+ @retvalEFI_UNSUPPORTEDThe platform does not support timer
interrupts.
+ @retvalEFI_ALREADY_STARTEDNotifyFunction is not NULL, and a
handler is already
+registered.
+ @retvalEFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler
was not
+previously registered.
+ @retvalEFI_DEVICE_ERROR The
[edk2-devel] [PATCH v8 27/37] OvmfPkg/LoongArchVirt: Add a NULL library named CollectApResouceLibNull
This Library is used to collect APs resources, but is currently NULL
for OvmfPkg, because it is not used by the LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Reviewed-by: Bibo Mao
---
.../CollectApResourceLibNull.c| 38 +++
.../CollectApResourceLibNull.inf | 31 +++
.../CollectApResourceLibNull.uni | 9 +
3 files changed, 78 insertions(+)
create mode 100644
OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
create mode 100644
OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
create mode 100644
OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
diff --git
a/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
new file mode 100644
index 00..471418f11e
--- /dev/null
+++
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
@@ -0,0 +1,38 @@
+/** @file
+ LoongArch64 CPU Collect AP resource NULL Library functions.
+
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include "../../../UefiCpuPkg/Library/MpInitLib/LoongArch64/MpLib.h"
+
+VOID
+SaveProcessorResourceData (
+ IN PROCESSOR_RESOURCE_DATA *
+ );
+
+VOID
+EFIAPI
+SaveProcessorResource (
+ PROCESSOR_RESOURCE_DATA *mProcessorResource
+ )
+{
+ SaveProcessorResourceData (mProcessorResource);
+}
+
+VOID
+EFIAPI
+CollectAllProcessorResource (
+ VOID
+ )
+{
+ return;
+}
diff --git
a/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
new file mode 100644
index 00..c166df6bbd
--- /dev/null
+++
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
@@ -0,0 +1,31 @@
+## @file
+# LoongArch64 CPU Collect AP resource NULL Library.
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 1.29
+ BASE_NAME = CollectApResourceLibNull
+ MODULE_UNI_FILE= CollectApResourceLibNull.uni
+ FILE_GUID = 8C3B54BF-6A9F-E8B4-4D57-67B3AB578DD6
+ MODULE_TYPE= PEIM
+ VERSION_STRING = 1.1
+ LIBRARY_CLASS = PEIM
+
+[Sources.common]
+ CollectApResourceLibNull.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ HobLib
+ MemoryAllocationLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
diff --git
a/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
new file mode 100644
index 00..d1638ab11e
--- /dev/null
+++
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
@@ -0,0 +1,9 @@
+// @file
+// LoongArch64 CPU Collect AP resource NULL Library.
+//
+// Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+
+#string STR_MODULE_ABSTRACT #language en-US "CPU Collect AP
resource NULL Library."
+
+#string STR_MODULE_DESCRIPTION #language en-US "CPU Collect AP
resource NULL Library."
--
2.27.0
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[edk2-devel] [PATCH v8 25/37] ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg
Moved the PlatformBootManagerLib to OvmfPkg and renamed to
PlatformBootManagerLibLight for easy use by other ARCH.
Build-tested only (with "ArmVirtQemu.dsc and OvmfPkgX64.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Cc: Lazlo Ersek
Signed-off-by: Chao Li
---
ArmVirtPkg/ArmVirtPkg.ci.yaml | 1 -
ArmVirtPkg/ArmVirtQemu.dsc | 2 +-
ArmVirtPkg/ArmVirtQemuKernel.dsc| 2 +-
.../Library/PlatformBootManagerLibLight}/PlatformBm.c | 0
.../Library/PlatformBootManagerLibLight}/PlatformBm.h | 0
.../PlatformBootManagerLibLight}/PlatformBootManagerLib.inf | 2 +-
.../Library/PlatformBootManagerLibLight}/QemuKernel.c | 0
7 files changed, 3 insertions(+), 4 deletions(-)
rename {ArmVirtPkg/Library/PlatformBootManagerLib =>
OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.c (100%)
rename {ArmVirtPkg/Library/PlatformBootManagerLib =>
OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBm.h (100%)
rename {ArmVirtPkg/Library/PlatformBootManagerLib =>
OvmfPkg/Library/PlatformBootManagerLibLight}/PlatformBootManagerLib.inf (93%)
rename {ArmVirtPkg/Library/PlatformBootManagerLib =>
OvmfPkg/Library/PlatformBootManagerLibLight}/QemuKernel.c (100%)
diff --git a/ArmVirtPkg/ArmVirtPkg.ci.yaml b/ArmVirtPkg/ArmVirtPkg.ci.yaml
index 506b0e72f0..b186d4eb42 100644
--- a/ArmVirtPkg/ArmVirtPkg.ci.yaml
+++ b/ArmVirtPkg/ArmVirtPkg.ci.yaml
@@ -24,7 +24,6 @@
],
## Both file path and directory path are accepted.
"IgnoreFiles": [
-"Library/PlatformBootManagerLib/PlatformBm.c"
]
},
## options defined .pytool/Plugin/CompilerPlugin
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 147180f645..e48c75b5e9 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -70,7 +70,7 @@
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
-
PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+
PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index c22a422353..668a65ba64 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -69,7 +69,7 @@
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
-
PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+
PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c
b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.c
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c
rename to OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.c
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h
b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.h
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h
rename to OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.h
diff --git
a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
similarity index 93%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
rename to OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
index 8e7cd5605f..f2fb69bd3c 100644
--- a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBootManagerLib.inf
@@ -20,7 +20,7 @@
#
# The following information is for reference only and not required by the
build tools.
#
-# VALID_ARCHITECTURES = ARM AARCH64
+# VALID_ARCHITECTURES = ARM AARCH64 LOONGARCH64
#
[Sources]
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/QemuKernel.c
b/OvmfPkg/Library/PlatformBootManagerLibLight/QemuKernel.c
similarity index 100%
rename from
[edk2-devel] [PATCH v8 24/37] ArmVirtPkg: Move two PCD variables into OvmfPkg
Move the PcdTerminalTypeGuidBuffer and PcdUninstallMemAttrProtocol into
OvmfPkg so other ARCH can easily use it.
Build-tested only (with "ArmVirtQemu.dsc and OvmfPkgX64.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Signed-off-by: Chao Li
---
ArmVirtPkg/ArmVirtPkg.dec | 13 -
ArmVirtPkg/ArmVirtQemu.dsc | 2 +-
ArmVirtPkg/ArmVirtQemuKernel.dsc| 2 +-
.../PlatformBootManagerLib.inf | 5 ++---
OvmfPkg/OvmfPkg.dec | 13 +
5 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index a658c91031..6aa5ea05f4 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -41,21 +41,8 @@
gArmVirtTokenSpaceGuid.PcdTpm2SupportEnabled|FALSE|BOOLEAN|0x0004
[PcdsFixedAtBuild, PcdsPatchableInModule]
- #
- # Binary representation of the GUID that determines the terminal type. The
- # size must be exactly 16 bytes. The default value corresponds to
- # EFI_VT_100_GUID.
- #
- gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 0xDF,
0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1,
0x4D}|VOID*|0x0007
-
##
# This is the physical address of Rsdp which is the core struct of Acpi.
# Cloud Hypervisor has no other way to pass Rsdp address to the guest except
use a PCD.
#
gArmVirtTokenSpaceGuid.PcdCloudHvAcpiRsdpBaseAddress|0x0|UINT64|0x0005
-
- ##
- # Whether the EFI memory attributes protocol should be uninstalled before
- # invoking the OS loader. This may be needed to work around problematic
- # builds of shim that use the protocol incorrectly.
- gArmVirtTokenSpaceGuid.PcdUninstallMemAttrProtocol|FALSE|BOOLEAN|0x0006
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index dbd2396c78..147180f645 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -182,7 +182,7 @@
!if $(TTY_TERMINAL) == TRUE
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
# Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID
- gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d,
0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
+ gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91,
0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
!else
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
!endif
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index 6a6ecfc12a..c22a422353 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -147,7 +147,7 @@
!if $(TTY_TERMINAL) == TRUE
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
# Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID
- gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d,
0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
+ gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91,
0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
!else
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
!endif
diff --git
a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 70e4ebf94a..8e7cd5605f 100644
--- a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -29,7 +29,6 @@
QemuKernel.c
[Packages]
- ArmVirtPkg/ArmVirtPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
OvmfPkg/OvmfPkg.dec
@@ -56,15 +55,15 @@
UefiRuntimeServicesTableLib
[FixedPcd]
- gArmVirtTokenSpaceGuid.PcdUninstallMemAttrProtocol
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+ gUefiOvmfPkgTokenSpaceGuid.PcdUninstallMemAttrProtocol
[Pcd]
- gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+ gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer
[Guids]
gEfiEndOfDxeEventGroupGuid
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 13e69e6648..fbc81e4c80 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -405,6 +405,19 @@
#
gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x6f
+ #
+ # Binary representation of the GUID that determines the terminal type. The
+ # size must be exactly 16 bytes. The default value corresponds to
+ # EFI_VT_100_GUID.
+ #
+ gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65,
[edk2-devel] [PATCH v8 23/37] ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg
Move the FdtSerialPortAddressLib to Ovmfpkg so that other ARCH can
easily use it.
Build-tested only (with "ArmVirtQemu.dsc and OvmfPkgX64.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Cc: Laszlo Ersek
Signed-off-by: Chao Li
---
ArmVirtPkg/ArmVirt.dsc.inc| 2 +-
ArmVirtPkg/ArmVirtPkg.dec | 1 -
.../Include/Library/FdtSerialPortAddressLib.h | 0
.../Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c | 0
.../FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf | 2 +-
OvmfPkg/OvmfPkg.dec | 4
6 files changed, 6 insertions(+), 3 deletions(-)
rename {ArmVirtPkg => OvmfPkg}/Include/Library/FdtSerialPortAddressLib.h (100%)
rename {ArmVirtPkg =>
OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c (100%)
rename {ArmVirtPkg =>
OvmfPkg}/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf (90%)
diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc
index 9b23ef97ec..2bc6a29eb1 100644
--- a/ArmVirtPkg/ArmVirt.dsc.inc
+++ b/ArmVirtPkg/ArmVirt.dsc.inc
@@ -122,7 +122,7 @@
# ARM PL011 UART Driver
PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
SerialPortLib|ArmVirtPkg/Library/FdtPL011SerialPortLib/FdtPL011SerialPortLib.inf
-
FdtSerialPortAddressLib|ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
+
FdtSerialPortAddressLib|OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
#PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index 05d2d36c1d..a658c91031 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -27,7 +27,6 @@
[LibraryClasses]
ArmVirtMemInfoLib|Include/Library/ArmVirtMemInfoLib.h
- FdtSerialPortAddressLib|Include/Library/FdtSerialPortAddressLib.h
[Guids.common]
gArmVirtTokenSpaceGuid = { 0x0B6F5CA7, 0x4F53, 0x445A, { 0xB7, 0x6E, 0x2E,
0x36, 0x5B, 0x80, 0x63, 0x66 } }
diff --git a/ArmVirtPkg/Include/Library/FdtSerialPortAddressLib.h
b/OvmfPkg/Include/Library/FdtSerialPortAddressLib.h
similarity index 100%
rename from ArmVirtPkg/Include/Library/FdtSerialPortAddressLib.h
rename to OvmfPkg/Include/Library/FdtSerialPortAddressLib.h
diff --git
a/ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
b/OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
similarity index 100%
rename from ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
rename to OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.c
diff --git
a/ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
b/OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
similarity index 90%
rename from
ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
rename to OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
index ae6d0d374b..e27742e9fa 100644
--- a/ArmVirtPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
+++ b/OvmfPkg/Library/FdtSerialPortAddressLib/FdtSerialPortAddressLib.inf
@@ -18,9 +18,9 @@
FdtSerialPortAddressLib.c
[Packages]
- ArmVirtPkg/ArmVirtPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
[LibraryClasses]
BaseLib
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 7bc2bf1674..13e69e6648 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -29,6 +29,10 @@
## @libraryclass Verify blobs read from the VMM
BlobVerifierLib|Include/Library/BlobVerifierLib.h
+ ## @libraryclass FdtSerialPortAddressLib
+ #
+ FdtSerialPortAddressLib|Include/Library/FdtSerialPortAddressLib.h
+
## @libraryclass Loads and boots a Linux kernel image
#
LoadLinuxLib|Include/Library/LoadLinuxLib.h
--
2.27.0
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[edk2-devel] [PATCH v8 22/37] OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt
CpuIo2Dxe is already used by RiscVVirt, so remove it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Sunil V L
Cc: Andrei Warkentin
Signed-off-by: Chao Li
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 --
.../RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 --
2 files changed, 605 deletions(-)
delete mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
delete mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
b/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
deleted file mode 100644
index f3bf07e631..00
--- a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
+++ /dev/null
@@ -1,557 +0,0 @@
-/** @file
- Produces the CPU I/O 2 Protocol.
-
-Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
-Copyright (c) 2016, Linaro Ltd. All rights reserved.
-Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
-
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include
-
-#include
-
-#include
-#include
-#include
-#include
-#include
-
-#define MAX_IO_PORT_ADDRESS 0x
-
-//
-// Handle for the CPU I/O 2 Protocol
-//
-STATIC EFI_HANDLE mHandle = NULL;
-
-//
-// Lookup table for increment values based on transfer widths
-//
-STATIC CONST UINT8 mInStride[] = {
- 1, // EfiCpuIoWidthUint8
- 2, // EfiCpuIoWidthUint16
- 4, // EfiCpuIoWidthUint32
- 8, // EfiCpuIoWidthUint64
- 0, // EfiCpuIoWidthFifoUint8
- 0, // EfiCpuIoWidthFifoUint16
- 0, // EfiCpuIoWidthFifoUint32
- 0, // EfiCpuIoWidthFifoUint64
- 1, // EfiCpuIoWidthFillUint8
- 2, // EfiCpuIoWidthFillUint16
- 4, // EfiCpuIoWidthFillUint32
- 8 // EfiCpuIoWidthFillUint64
-};
-
-//
-// Lookup table for increment values based on transfer widths
-//
-STATIC CONST UINT8 mOutStride[] = {
- 1, // EfiCpuIoWidthUint8
- 2, // EfiCpuIoWidthUint16
- 4, // EfiCpuIoWidthUint32
- 8, // EfiCpuIoWidthUint64
- 1, // EfiCpuIoWidthFifoUint8
- 2, // EfiCpuIoWidthFifoUint16
- 4, // EfiCpuIoWidthFifoUint32
- 8, // EfiCpuIoWidthFifoUint64
- 0, // EfiCpuIoWidthFillUint8
- 0, // EfiCpuIoWidthFillUint16
- 0, // EfiCpuIoWidthFillUint32
- 0 // EfiCpuIoWidthFillUint64
-};
-
-/**
- Check parameters to a CPU I/O 2 Protocol service request.
-
- The I/O operations are carried out exactly as requested. The caller is
responsible
- for satisfying any alignment and I/O width restrictions that a PI System on a
- platform might require. For example on some platforms, width requests of
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
- be handled by the driver.
-
- @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port
operation.
- @param[in] Width Signifies the width of the I/O or Memory operation.
- @param[in] AddressThe base address of the I/O operation.
- @param[in] Count The number of I/O operations to perform. The
number of
-bytes moved is Width size * Count, starting at
Address.
- @param[in] Buffer For read operations, the destination buffer to
store the results.
-For write operations, the source buffer from which
to write data.
-
- @retval EFI_SUCCESSThe parameters for this request pass the
checks.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width.
- @retval EFI_UNSUPPORTEDThe address range specified by Address, Width,
- and Count is not valid for this PI system.
-
-**/
-STATIC
-EFI_STATUS
-CpuIoCheckParameter (
- IN BOOLEANMmioOperation,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- UINT64 MaxCount;
- UINT64 Limit;
-
- //
- // Check to see if Buffer is NULL
- //
- if (Buffer == NULL) {
-return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check to see if Width is in the valid range
- //
- if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
-return EFI_INVALID_PARAMETER;
- }
-
- //
- // For FIFO type, the target address won't increase during the access,
- // so treat Count as 1
- //
- if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64))
{
-Count = 1;
- }
-
- //
- // Check to see if Width is in the valid range for I/O Port operations
- //
- Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
- if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
-return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check to see if Address is aligned
- //
- if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
-return EFI_UNSUPPORTED;
- }
-
- //
- // Check to see if any address associated with this transfer exceeds the
maximum
- // allowed address.
[edk2-devel] [PATCH v8 21/37] OvmfPkg/RiscVVirt: Enable CpuMmio2Dxe
CpuMmio2Dxe is supports MMIO, enable it.
Build-tested only (with "RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Sunil V L
Cc: Andrei Warkentin
Signed-off-by: Chao Li
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 +-
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
index 774dc81840..27f24648e8 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
@@ -433,7 +433,7 @@
#
# PCI support
#
- OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
}
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
index 8121b9e579..e579f5b9b7 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
@@ -184,7 +184,7 @@ INF OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
# PCI support
#
-INF OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
--
2.27.0
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[edk2-devel] [PATCH v8 20/37] ArmVirtPkg: Enable CpuMmio2Dxe
CpuMmio2Dxe is supports MMIO, enable it.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
ArmVirtPkg/ArmVirtCloudHv.dsc| 2 +-
ArmVirtPkg/ArmVirtCloudHv.fdf| 2 +-
ArmVirtPkg/ArmVirtKvmTool.dsc| 2 +-
ArmVirtPkg/ArmVirtKvmTool.fdf| 2 +-
ArmVirtPkg/ArmVirtQemu.dsc | 2 +-
ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +-
ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc
index 76c0d28544..5cb2a609b1 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.dsc
+++ b/ArmVirtPkg/ArmVirtCloudHv.dsc
@@ -341,7 +341,7 @@
#
# PCI support
#
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
}
diff --git a/ArmVirtPkg/ArmVirtCloudHv.fdf b/ArmVirtPkg/ArmVirtCloudHv.fdf
index 56d1ea6e8c..8554efc294 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.fdf
+++ b/ArmVirtPkg/ArmVirtCloudHv.fdf
@@ -201,7 +201,7 @@ READ_LOCK_STATUS = TRUE
#
# PCI support
#
- INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc
index cac4fe06d3..20da331966 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.dsc
+++ b/ArmVirtPkg/ArmVirtKvmTool.dsc
@@ -372,7 +372,7 @@
#
# PCI support
#
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
NULL|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf
diff --git a/ArmVirtPkg/ArmVirtKvmTool.fdf b/ArmVirtPkg/ArmVirtKvmTool.fdf
index 82aff47673..cdf756c112 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.fdf
+++ b/ArmVirtPkg/ArmVirtKvmTool.fdf
@@ -195,7 +195,7 @@ READ_LOCK_STATUS = TRUE
#
# PCI support
#
- INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index cf306cac08..dbd2396c78 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -526,7 +526,7 @@
#
# PCI support
#
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
}
diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
index 9b3e37d5c9..c5d097ffb9 100644
--- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
+++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
@@ -153,7 +153,7 @@ READ_LOCK_STATUS = TRUE
#
# PCI support
#
- INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index c0d079e28d..6a6ecfc12a 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -431,7 +431,7 @@
#
# PCI support
#
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf {
NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
}
--
2.27.0
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[edk2-devel] [PATCH v8 19/37] UefiCpuPkg: Add a new CPU IO 2 driver named CpuMmio2Dxe
CpuIo2Dxe only supports IO to access to CPU IO. Some ARCHs that do not
implement ports for CPU IO require MMIO to access PCI IO, and they
pretty much put the IO devices under the LPC bus, which is usually under
the PCIe/PCI bus. CpuMmio2Dxe was added to meet these needs.
CpuMmio2Dxe depends on PcdPciIoTranslation. The code is copied from
ArmPkg.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ray Ni
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Sami Mujawar
Signed-off-by: Chao Li
Reviewed-by: Ray Ni
---
UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c | 557 +
UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf | 48 +++
UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni | 18 +
UefiCpuPkg/UefiCpuPkg.dsc | 2 +
4 files changed, 625 insertions(+)
create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni
diff --git a/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
new file mode 100644
index 00..32ccac1cc6
--- /dev/null
+++ b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c
@@ -0,0 +1,557 @@
+/** @file
+ Produces the CPU I/O 2 Protocol.
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2016, Linaro Ltd. All rights reserved.
+Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define MAX_IO_PORT_ADDRESS 0x
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 0, // EfiCpuIoWidthFifoUint8
+ 0, // EfiCpuIoWidthFifoUint16
+ 0, // EfiCpuIoWidthFifoUint32
+ 0, // EfiCpuIoWidthFifoUint64
+ 1, // EfiCpuIoWidthFillUint8
+ 2, // EfiCpuIoWidthFillUint16
+ 4, // EfiCpuIoWidthFillUint32
+ 8 // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 1, // EfiCpuIoWidthFifoUint8
+ 2, // EfiCpuIoWidthFifoUint16
+ 4, // EfiCpuIoWidthFifoUint32
+ 8, // EfiCpuIoWidthFifoUint64
+ 0, // EfiCpuIoWidthFillUint8
+ 0, // EfiCpuIoWidthFillUint16
+ 0, // EfiCpuIoWidthFillUint32
+ 0 // EfiCpuIoWidthFillUint64
+};
+
+/**
+ Check parameters to a CPU I/O 2 Protocol service request.
+
+ The I/O operations are carried out exactly as requested. The caller is
responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port
operation.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] AddressThe base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The
number of
+bytes moved is Width size * Count, starting at
Address.
+ @param[in] Buffer For read operations, the destination buffer to
store the results.
+For write operations, the source buffer from which
to write data.
+
+ @retval EFI_SUCCESSThe parameters for this request pass the
checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTEDThe address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+ IN BOOLEANMmioOperation,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT64 MaxCount;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64))
{
+Count = 1;
+ }
+
+ //
+
[edk2-devel] [PATCH v8 18/37] ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkg
Moved PcdDeviceTreeInitialBaseAddress and PcdDeviceTreeAllocationPadding
to OvmfPkg for easier use by other architectures.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Laszlo Ersek
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Cc: Jordan Justen
Signed-off-by: Chao Li
Acked-by: Gerd Hoffmann
Reviewed-by: Sami Mujawar
---
ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +-
ArmVirtPkg/ArmVirtKvmTool.dsc | 2 +-
ArmVirtPkg/ArmVirtPkg.dec | 14 --
ArmVirtPkg/ArmVirtQemu.dsc| 2 +-
ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +-
ArmVirtPkg/ArmVirtXen.dsc | 2 +-
.../ArmVirtPsciResetSystemPeiLib.inf | 3 ++-
.../CloudHvVirtMemInfoPeiLib.inf | 3 ++-
.../DebugLibFdtPL011UartFlash.inf | 3 ++-
.../EarlyFdt16550SerialPortHookLib.inf| 3 ++-
.../EarlyFdtPL011SerialPortLib.inf| 3 ++-
.../KvmtoolPlatformPeiLib.inf | 5 +++--
.../Library/PlatformPeiLib/PlatformPeiLib.inf | 10 +-
.../QemuVirtMemInfoLib/QemuVirtMemInfoPeiLib.inf | 3 ++-
.../PrePi/ArmVirtPrePiUniCoreRelocatable.inf | 3 ++-
OvmfPkg/OvmfPkg.dec | 15 +++
16 files changed, 42 insertions(+), 33 deletions(-)
diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc
index 2cb89ce10c..76c0d28544 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.dsc
+++ b/ArmVirtPkg/ArmVirtCloudHv.dsc
@@ -129,7 +129,7 @@
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x4000
# initial location of the device tree blob passed by Cloud Hypervisor --
base of DRAM
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c,
0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc
index f50d53bf15..cac4fe06d3 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.dsc
+++ b/ArmVirtPkg/ArmVirtKvmTool.dsc
@@ -179,7 +179,7 @@
# We are booting from RAM using the Linux kernel boot protocol,
# x0 will point to the DTB image in memory.
#
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0
gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
gArmTokenSpaceGuid.PcdFvBaseAddress|0x0
diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index 313aebda90..05d2d36c1d 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -42,20 +42,6 @@
gArmVirtTokenSpaceGuid.PcdTpm2SupportEnabled|FALSE|BOOLEAN|0x0004
[PcdsFixedAtBuild, PcdsPatchableInModule]
- #
- # This is the physical address where the device tree is expected to be stored
- # upon first entry into UEFI. This needs to be a FixedAtBuild PCD, so that we
- # can do a first pass over the device tree in the SEC phase to discover the
- # UART base address.
- #
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0|UINT64|0x0001
-
- #
- # Padding in bytes to add to the device tree allocation, so that the DTB can
- # be modified in place (default: 256 bytes)
- #
- gArmVirtTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x0002
-
#
# Binary representation of the GUID that determines the terminal type. The
# size must be exactly 16 bytes. The default value corresponds to
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 30e3cfc8b9..cf306cac08 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -201,7 +201,7 @@
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x4000
# initial location of the device tree blob passed by QEMU -- base of DRAM
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c,
0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index b50f8e84a3..c0d079e28d 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -198,7 +198,7 @@
# Define a default initial address for the device tree.
# Ignored if x0 != 0 at entry.
#
- gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
+ gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x4000
gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
[edk2-devel] [PATCH v8 17/37] EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64
Added LoongArch64 architecture CPU IO width. https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Abner Chang Cc: Daniel Schaefer Signed-off-by: Chao Li Reviewed-by: Leif Lindholm --- EmbeddedPkg/EmbeddedPkg.dec | 3 +++ 1 file changed, 3 insertions(+) diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec index b4834e8b4f..5dfbbc2933 100644 --- a/EmbeddedPkg/EmbeddedPkg.dec +++ b/EmbeddedPkg/EmbeddedPkg.dec @@ -166,6 +166,9 @@ [PcdsFixedAtBuild.X64] gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16|UINT8|0x0011 +[PcdsFixedAtBuild.LOONGARCH64] + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16|UINT8|0x0011 + [PcdsFixedAtBuild.common, PcdsDynamic.common] # # Value to add to a host address to obtain a device address, using -- 2.27.0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114543): https://edk2.groups.io/g/devel/message/114543 Mute This Topic: https://groups.io/mt/103971656/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v8 16/37] UefiCpuPkg: Add CpuDxe driver for LoongArch64
Added LoongArch64 CPU driver into CpuDxe.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authored-by: Dongyan Qian
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 23 +-
UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c| 454 ++
UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.h| 288
UefiCpuPkg/CpuDxe/LoongArch64/CpuMp.c | 544 ++
UefiCpuPkg/CpuDxe/LoongArch64/Exception.c | 159 +++
5 files changed, 1464 insertions(+), 4 deletions(-)
create mode 100644 UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c
create mode 100644 UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.h
create mode 100644 UefiCpuPkg/CpuDxe/LoongArch64/CpuMp.c
create mode 100644 UefiCpuPkg/CpuDxe/LoongArch64/Exception.c
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index 1d3e9f8cdb..18ebd2eb2c 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,17 +23,16 @@
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
-[LibraryClasses]
+[LibraryClasses.common]
BaseLib
BaseMemoryLib
CpuLib
+ CacheMaintenanceLib
DebugLib
DxeServicesTableLib
MemoryAllocationLib
- MtrrLib
UefiBootServicesTableLib
UefiDriverEntryPoint
- LocalApicLib
UefiLib
CpuExceptionHandlerLib
HobLib
@@ -41,7 +41,14 @@
TimerLib
PeCoffGetEntryPointLib
-[Sources]
+[LibraryClasses.IA32, LibraryClasses.X64]
+ LocalApicLib
+ MtrrLib
+
+[LibraryClasses.LoongArch64]
+ CpuMmuLib
+
+[Sources.IA32, Sources.X64]
CpuDxe.c
CpuDxe.h
CpuGdt.c
@@ -59,6 +66,13 @@
X64/CpuAsm.nasm
X64/PagingAttribute.c
+[Sources.LoongArch64]
+ CpuMp.h
+ LoongArch64/CpuDxe.c
+ LoongArch64/CpuMp.c
+ LoongArch64/Exception.c
+ LoongArch64/CpuDxe.h
+
[Protocols]
gEfiCpuArchProtocolGuid ## PRODUCES
gEfiMpServiceProtocolGuid ## PRODUCES
@@ -77,6 +91,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##
CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##
CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask##
CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuExceptionVectorBaseAddress##
CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList ##
CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize##
CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask##
CONSUMES
diff --git a/UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c
b/UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c
new file mode 100644
index 00..65ed0b3913
--- /dev/null
+++ b/UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c
@@ -0,0 +1,454 @@
+/** @file CpuDxe.c
+
+ CPU DXE Module to produce CPU ARCH Protocol.
+
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "CpuDxe.h"
+#include "CpuMp.h"
+#include
+#include
+#include
+#include
+
+UINT64 mTimerPeriod = 0;
+
+/**
+ IPI Interrupt Handler.
+
+ @param InterruptTypeThe type of interrupt that occurred
+ @param SystemContextA pointer to the system context when the interrupt
occurred
+**/
+VOID
+EFIAPI
+IpiInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ );
+
+//
+// Globals used to initialize the protocol
+//
+EFI_HANDLE mCpuHandle = NULL;
+EFI_CPU_ARCH_PROTOCOL gCpu = {
+ CpuFlushCpuDataCache,
+ CpuEnableInterrupt,
+ CpuDisableInterrupt,
+ CpuGetInterruptState,
+ CpuInit,
+ CpuRegisterInterruptHandler,
+ CpuGetTimerValue,
+ CpuSetMemoryAttributes,
+ 0, // NumberOfTimers
+ 4, // DmaBufferAlignment
+};
+
+/**
+ This function flushes the range of addresses from Start to Start+Length
+ from the processor's data cache. If Start is not aligned to a cache line
+ boundary, then the bytes before Start to the preceding cache line boundary
+ are also flushed. If Start+Length is not aligned to a cache line boundary,
+ then the bytes past Start+Length to the end of the next cache line boundary
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+ supported. If the data cache is fully coherent with all DMA operations, then
+ this function can just return EFI_SUCCESS. If the processor does not support
+ flushing a range of the data cache, then the entire data cache can be
flushed.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param StartThe beginning
[edk2-devel] [PATCH v8 15/37] UefiCpuPkg: Add multiprocessor library for LoongArch64
Added LoongArch multiprocessor initialization instance into MpInitLib.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 27 +-
.../Library/MpInitLib/LoongArch64/DxeMpLib.c | 480 +
.../Library/MpInitLib/LoongArch64/MpLib.c | 1621 +
.../Library/MpInitLib/LoongArch64/MpLib.h | 361
.../Library/MpInitLib/LoongArch64/PeiMpLib.c | 404
UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 27 +-
6 files changed, 2902 insertions(+), 18 deletions(-)
create mode 100644 UefiCpuPkg/Library/MpInitLib/LoongArch64/DxeMpLib.c
create mode 100644 UefiCpuPkg/Library/MpInitLib/LoongArch64/MpLib.c
create mode 100644 UefiCpuPkg/Library/MpInitLib/LoongArch64/MpLib.h
create mode 100644 UefiCpuPkg/Library/MpInitLib/LoongArch64/PeiMpLib.c
diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
index 55e46d4a1f..6db26f5fec 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
@@ -2,6 +2,7 @@
# MP Initialize Library instance for DXE driver.
#
# Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -18,7 +19,7 @@
#
# The following information is for reference only and not required by the
build tools.
#
-# VALID_ARCHITECTURES = IA32 X64
+# VALID_ARCHITECTURES = IA32 X64 LOONGARCH64
#
[Sources.IA32]
@@ -31,7 +32,7 @@
X64/MpFuncs.nasm
X64/CreatePageTable.c
-[Sources.common]
+[Sources.IA32, Sources.X64]
AmdSev.c
MpEqu.inc
DxeMpLib.c
@@ -40,24 +41,32 @@
Microcode.c
MpHandOff.h
+[Sources.LoongArch64]
+ LoongArch64/DxeMpLib.c
+ LoongArch64/MpLib.c
+ LoongArch64/MpLib.h
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
-[LibraryClasses]
+[LibraryClasses.common]
BaseLib
- LocalApicLib
- MemoryAllocationLib
- HobLib
- MtrrLib
CpuLib
- UefiBootServicesTableLib
DebugAgentLib
- SynchronizationLib
+ HobLib
+ MemoryAllocationLib
PcdLib
+ UefiBootServicesTableLib
+ SynchronizationLib
+
+[LibraryClasses.IA32, LibraryClasses.X64]
CcExitLib
+ LocalApicLib
MicrocodeLib
+ MtrrLib
+
[LibraryClasses.X64]
CpuPageTableLib
diff --git a/UefiCpuPkg/Library/MpInitLib/LoongArch64/DxeMpLib.c
b/UefiCpuPkg/Library/MpInitLib/LoongArch64/DxeMpLib.c
new file mode 100644
index 00..739da77e32
--- /dev/null
+++ b/UefiCpuPkg/Library/MpInitLib/LoongArch64/DxeMpLib.c
@@ -0,0 +1,480 @@
+/** @file
+ LoongArch64 MP initialize support functions for DXE phase.
+
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "MpLib.h"
+
+#include
+#include
+#include
+
+#include
+
+CPU_MP_DATA *mCpuMpData= NULL;
+EFI_EVENT mCheckAllApsEvent = NULL;
+volatile BOOLEAN mStopCheckAllApsStatus = TRUE;
+
+/**
+ Enable Debug Agent to support source debugging on AP function.
+
+**/
+VOID
+EnableDebugAgent (
+ VOID
+ )
+{
+ //
+ // Initialize Debug Agent to support source level debug in DXE phase
+ //
+ InitializeDebugAgent (DEBUG_AGENT_INIT_DXE_AP, NULL, NULL);
+}
+
+/**
+ Get the pointer to CPU MP Data structure.
+
+ @return The pointer to CPU MP Data structure.
+**/
+CPU_MP_DATA *
+GetCpuMpData (
+ VOID
+ )
+{
+ ASSERT (mCpuMpData != NULL);
+ return mCpuMpData;
+}
+
+/**
+ Save the pointer to CPU MP Data structure.
+
+ @param[in] CpuMpData The pointer to CPU MP Data structure will be saved.
+**/
+VOID
+SaveCpuMpData (
+ IN CPU_MP_DATA *CpuMpData
+ )
+{
+ mCpuMpData = CpuMpData;
+}
+
+/**
+ Get available EfiBootServicesCode memory below 4GB by specified size.
+
+ This buffer is required to safely transfer AP from real address mode to
+ protected mode or long mode, due to the fact that the buffer returned by
+ GetWakeupBuffer() may be marked as non-executable.
+
+ @param[in] BufferSize Wakeup transition buffer size.
+
+ @retval other Return wakeup transition buffer address below 4GB.
+ @retval 0 Cannot find free memory below 4GB.
+**/
+UINTN
+GetModeTransitionBuffer (
+ IN UINTN BufferSize
+ )
+{
+ return 0;
+}
+
+/**
+ Checks APs status and updates APs status if needed.
+
+**/
+VOID
+CheckAndUpdateApsStatus (
+ VOID
+ )
+{
+ UINTNProcessorNumber;
+ EFI_STATUS Status;
+ CPU_MP_DATA *CpuMpData;
+
+ CpuMpData = GetCpuMpData ();
+
+ //
+ // First, check whether pending StartupAllAPs() exists.
+ //
+ if (CpuMpData->WaitEvent != NULL) {
+Status = CheckAllAPs ();
+//
+// If all APs finish for StartupAllAPs(), signal the WaitEvent for it.
+//
+if (Status != EFI_NOT_READY) {
+
[edk2-devel] [PATCH v8 14/37] UefiCpuPkg: Add CpuMmuLib to UefiCpuPkg
Add a new library named CpuMmuLib and add a LoongArch64 instance with in the library. It provides two-stage MMU libraryinstances, PEI and DXE. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Chao Li Co-authored-by: Baoqi Zhang Co-authored-by: Dongyan Qian Co-authored-by: Xianglai Li Co-authored-by: Bibo Mao --- UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.inf | 36 + UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.uni | 14 + .../CpuMmuLib/LoongArch64/CommonMmuLib.c | 988 ++ .../CpuMmuLib/LoongArch64/CommonMmuLib.h | 43 + .../Library/CpuMmuLib/LoongArch64/Page.h | 279 + .../CpuMmuLib/LoongArch64/PeiCpuMmuLib.c | 178 .../Library/CpuMmuLib/LoongArch64/Tlb.h | 48 + .../CpuMmuLib/LoongArch64/TlbOperation.S | 44 + UefiCpuPkg/Library/CpuMmuLib/PeiCpuMmuLib.inf | 44 + UefiCpuPkg/Library/CpuMmuLib/PeiCpuMmuLib.uni | 14 + UefiCpuPkg/UefiCpuPkg.dsc | 4 + 11 files changed, 1692 insertions(+) create mode 100644 UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.inf create mode 100644 UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.uni create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CommonMmuLib.c create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CommonMmuLib.h create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/Page.h create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/PeiCpuMmuLib.c create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/Tlb.h create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/TlbOperation.S create mode 100644 UefiCpuPkg/Library/CpuMmuLib/PeiCpuMmuLib.inf create mode 100644 UefiCpuPkg/Library/CpuMmuLib/PeiCpuMmuLib.uni diff --git a/UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.inf b/UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.inf new file mode 100644 index 00..bfce3ce96d --- /dev/null +++ b/UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.inf @@ -0,0 +1,36 @@ +## @file +# CPU Memory Map Unit DXE phase driver. +# +# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION= 1.29 + BASE_NAME = DxeCpuMmuLib + MODULE_UNI_FILE= DxeCpuMmuLib.uni + FILE_GUID = DA8F0232-FB14-42F0-922C-63104D2C70BE + MODULE_TYPE= DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = CpuMmuLib | DXE_DRIVER + CONSTRUCTOR= MmuInitialize + +# +# VALID_ARCHITECTURES = LOONGARCH64 +# + +[Sources.LoongArch64] + LoongArch64/TlbOperation.S | GCC + LoongArch64/CommonMmuLib.c + LoongArch64/Page.h + LoongArch64/Tlb.h + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + DebugLib + MemoryAllocationLib diff --git a/UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.uni b/UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.uni new file mode 100644 index 00..7342249516 --- /dev/null +++ b/UefiCpuPkg/Library/CpuMmuLib/DxeCpuMmuLib.uni @@ -0,0 +1,14 @@ +// /** @file +// CPU Memory Manager Unit library instance for DXE modules. +// +// CPU Memory Manager Unit library instance for DXE modules. +// +// Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "CPU Memory Manager Unit library instance for DXE modules." + +#string STR_MODULE_DESCRIPTION #language en-US "CPU Memory Manager Unit library instance for DXE modules." diff --git a/UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CommonMmuLib.c b/UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CommonMmuLib.c new file mode 100644 index 00..2e852c3371 --- /dev/null +++ b/UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CommonMmuLib.c @@ -0,0 +1,988 @@ +/** @file + + CPU Memory Map Unit Handler Library common functions. + + Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: +- Pgd or Pgd or PGD- Page Global Directory +- Pud or Pud or PUD- Page Upper Directory +- Pmd or Pmd or PMD- Page Middle Directory +- Pte or pte or PTE- Page Table Entry +- Val or VAL or val- Value +- Dir- Directory +**/ +#include +#include +#include +#include +#include +#include +#include +#include "Tlb.h" +#include "Page.h" + +#define SWAP_PAGE_DIR CsrRead(LOONGARCH_CSR_PGDL) +#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \ +EFI_MEMORY_WC | \ +EFI_MEMORY_WT | \ +EFI_MEMORY_WB | \ +EFI_MEMORY_UCE \ +
[edk2-devel] [PATCH v8 13/37] UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg
Add a new header file CpuMmuLib.h, whitch is referenced from
ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for
LoongArch64 is added, and more architectures can be accommodated in the
future.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Sami Mujawar
Cc: Sunil V L
Cc: Andrei Warkentin
Signed-off-by: Chao Li
Reviewed-by: Andrei Warkentin
Reviewed-by: Ray Ni
---
UefiCpuPkg/Include/Library/CpuMmuLib.h | 62 ++
UefiCpuPkg/UefiCpuPkg.dec | 4 ++
2 files changed, 66 insertions(+)
create mode 100644 UefiCpuPkg/Include/Library/CpuMmuLib.h
diff --git a/UefiCpuPkg/Include/Library/CpuMmuLib.h
b/UefiCpuPkg/Include/Library/CpuMmuLib.h
new file mode 100644
index 00..f88ec4eb2e
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/CpuMmuLib.h
@@ -0,0 +1,62 @@
+/** @file
+
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_MMU_LIB_H_
+#define CPU_MMU_LIB_H_
+
+#include
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESSPhysicalBase;
+ EFI_VIRTUAL_ADDRESS VirtualBase;
+ UINTN Length;
+ UINTN Attributes;
+} MEMORY_REGION_DESCRIPTOR;
+
+/**
+ Finds the first of the length and memory properties of the memory region
corresponding
+ to the specified base address.
+
+ @param[in] BaseAddress To find the base address of the memory
region.
+ @param[in, out] RegionLength Pointer holding:
+ - At entry, the length of the memory
region
+expected to be found.
+ - At exit, the length of the memory
region found.
+ @param[out] RegionAttributes Properties of the memory region found.
+
+ @retval EFI_SUCCESSThe corresponding memory area was successfully found
+ EFI_NOT_FOUNDNo memory area found
+**/
+EFI_STATUS
+EFIAPI
+GetMemoryRegionAttributes (
+ IN UINTN BaseAddress,
+ IN OUT UINTN *RegionLength,
+ OUTUINTN *RegionAttributes
+ );
+
+/**
+ Sets the Attributes of the specified memory region.
+
+ @param[in] BaseAddressThe base address of the memory region to set the
Attributes.
+ @param[in] Length The length of the memory region to set the
Attributes.
+ @param[in] Attributes The Attributes to be set.
+ @param[in] AttributeMask Mask of memory attributes to take into account.
+
+ @retval EFI_SUCCESSThe Attributes was set successfully
+**/
+EFI_STATUS
+EFIAPI
+SetMemoryRegionAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN Length,
+ IN UINTN Attributes,
+ IN UINT64AttributeMask
+ );
+
+#endif // CPU_MMU_LIB_H_
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index f5febe46ba..9992626e62 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -62,6 +62,10 @@
## @libraryclass Provides function for manipulating x86 paging structures.
CpuPageTableLib|Include/Library/CpuPageTableLib.h
+[LibraryClasses.LoongArch64]
+ ## @libraryclass Provides macros and functions for the memory management
unit.
+ CpuMmuLib|Include/Library/CpuMmuLib.h
+
## @libraryclass Provides functions for manipulating smram savestate
registers.
MmSaveStateLib|Include/Library/MmSaveStateLib.h
--
2.27.0
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[edk2-devel] [PATCH v8 12/37] UefiCpuPkg: Add CPU exception library for LoongArch
Added LoongArch exception handler into CpuExceptionHandlerLib.
Adjust the file order in INF of CpuExceptionHandlerLib with alphabetical
order.
Adjust files order in CpuExceptionHandlerLib INF in alphabetical order.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
---
.../DxeCpuExceptionHandlerLib.inf | 34 +-
.../LoongArch/DxeExceptionLib.c | 198 ++
.../LoongArch/ExceptionCommon.c | 171
.../LoongArch/ExceptionCommon.h | 131 +++
.../LoongArch64/ArchExceptionHandler.c| 268 +
.../LoongArch64/ExceptionHandlerAsm.S | 366 ++
.../LoongArch/SecPeiExceptionLib.c| 102 +
.../SecPeiCpuExceptionHandlerLib.inf | 29 +-
UefiCpuPkg/UefiCpuPkg.dec | 5 +
9 files changed, 1283 insertions(+), 21 deletions(-)
create mode 100644
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/DxeExceptionLib.c
create mode 100644
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/ExceptionCommon.c
create mode 100644
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/ExceptionCommon.h
create mode 100644
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/LoongArch64/ArchExceptionHandler.c
create mode 100644
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/LoongArch64/ExceptionHandlerAsm.S
create mode 100644
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/SecPeiExceptionLib.c
diff --git
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index fdbebadab9..f5bacbe2bc 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -18,25 +18,32 @@
#
# The following information is for reference only and not required by the
build tools.
#
-# VALID_ARCHITECTURES = IA32 X64
+# VALID_ARCHITECTURES = IA32 X64 LOONGARCH64
#
[Sources.Ia32]
- Ia32/ExceptionHandlerAsm.nasm
- Ia32/ExceptionTssEntryAsm.nasm
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
+ Ia32/ExceptionHandlerAsm.nasm
+ Ia32/ExceptionTssEntryAsm.nasm
[Sources.X64]
- X64/ExceptionHandlerAsm.nasm
X64/ArchExceptionHandler.c
X64/ArchInterruptDefs.h
+ X64/ExceptionHandlerAsm.nasm
-[Sources.common]
+[Sources.Ia32, Sources.X64]
CpuExceptionCommon.h
CpuExceptionCommon.c
- PeiDxeSmmCpuException.c
DxeException.c
+ PeiDxeSmmCpuException.c
+
+[Sources.LoongArch64]
+ LoongArch/DxeExceptionLib.c
+ LoongArch/ExceptionCommon.h
+ LoongArch/ExceptionCommon.c
+ LoongArch/LoongArch64/ArchExceptionHandler.c
+ LoongArch/LoongArch64/ExceptionHandlerAsm.S | GCC
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
@@ -51,16 +58,19 @@
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
-[LibraryClasses]
+[LibraryClasses.common]
BaseLib
- SerialPortLib
+ CpuLib
+ DebugLib
+ MemoryAllocationLib
+ PeCoffGetEntryPointLib
PrintLib
+ SerialPortLib
SynchronizationLib
- LocalApicLib
- PeCoffGetEntryPointLib
- MemoryAllocationLib
- DebugLib
+
+[LibraryClasses.Ia32, LibraryClasses.X64]
CcExitLib
+ LocalApicLib
[BuildOptions]
XCODE:*_*_X64_NASM_FLAGS = -D NO_ABSOLUTE_RELOCS_IN_TEXT
diff --git
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/DxeExceptionLib.c
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/DxeExceptionLib.c
new file mode 100644
index 00..2c5d202b33
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/DxeExceptionLib.c
@@ -0,0 +1,198 @@
+/** @file DxeExceptionLib.c
+
+ LoongArch exception library implemenation for DXE modules.
+
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ExceptionCommon.h"
+
+EFI_EXCEPTION_CALLBACK ExternalInterruptHandler[MAX_LOONGARCH_INTERRUPT + 1]
= { 0 };
+EFI_EXCEPTION_CALLBACK ExceptionHandler[MAX_LOONGARCH_EXCEPTION + 1]
= { 0 };
+
+/**
+ Registers a function to be called from the processor interrupt or exception
handler.
+
+ This function registers and enables the handler specified by
InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler
is NULL, then the
+ handler for the processor interrupt or exception type specified by
InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or
exception.
+
+ @param InterruptTypeA pointer to the processor's current interrupt
state. Set to TRUE if interrupts
+ are enabled and FALSE if interrupts are disabled.
+ @param
[edk2-devel] [PATCH v8 11/37] UefiCpuPkg: Add LoongArch64 CPU Timer instance
Add the LoongArch64 CPU Timer instance to CpuTimerLib, using CPUCFG 0x4
and 0x5 for Stable Counter frequency.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
.../Library/CpuTimerLib/BaseCpuTimerLib.inf | 9 +-
.../CpuTimerLib/LoongArch64/CpuTimerLib.c | 251 ++
2 files changed, 258 insertions(+), 2 deletions(-)
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c
diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
index de0648de91..7e6152ef7e 100644
--- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
@@ -5,6 +5,7 @@
# counter features are provided by the processors time stamp counter.
#
# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -18,18 +19,22 @@
LIBRARY_CLASS = TimerLib
MODULE_UNI_FILE= BaseCpuTimerLib.uni
-[Sources]
+[Sources.IA32, Sources.X64]
CpuTimerLib.c
BaseCpuTimerLib.c
+[Sources.LOONGARCH64]
+ LoongArch64/CpuTimerLib.c
+
[Packages]
MdePkg/MdePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
BaseLib
- PcdLib
DebugLib
+ PcdLib
+ SafeIntLib
[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES
diff --git a/UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c
b/UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c
new file mode 100644
index 00..a5ae8d0185
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c
@@ -0,0 +1,251 @@
+/** @file
+ CPUCFG 0x4 and 0x5 for Stable Counter frequency instance of Timer Library.
+
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Calculate clock frequency using CPUCFG 0x4 and 0x5 registers.
+
+ @param VOID.
+
+ @return The frequency in Hz.
+
+**/
+STATIC
+UINT64
+CalcConstFreq (
+ VOID
+ )
+{
+ UINT32 BaseFreq;
+ UINT64 ClockMultiplier;
+ UINT32 ClockDivide;
+ CPUCFG_REG4_INFO_DATA CcFreq;
+ CPUCFG_REG5_INFO_DATA CpucfgReg5Data;
+ UINT64 StableTimerFreq;
+
+ //
+ // Get the the crystal frequency corresponding to the constant
+ // frequency timer and the clock used by the timer.
+ //
+ AsmCpucfg (CPUCFG_REG4_INFO, );
+
+ //
+ // Get the multiplication factor and frequency division factor
+ // corresponding to the constant frequency timer and the clock
+ // used by the timer.
+ //
+ AsmCpucfg (CPUCFG_REG5_INFO, );
+
+ BaseFreq= CcFreq.Bits.CC_FREQ;
+ ClockMultiplier = CpucfgReg5Data.Bits.CC_MUL & 0x;
+ ClockDivide = CpucfgReg5Data.Bits.CC_DIV & 0x;
+
+ if ((BaseFreq == 0x0) || (ClockMultiplier == 0x0) || (ClockDivide == 0x0)) {
+DEBUG ((
+ DEBUG_ERROR,
+ "LoongArch Stable Timer is not available in the CPU, hence this library
cannot be used.\n"
+ ));
+ASSERT (FALSE);
+CpuDeadLoop ();
+ }
+
+ StableTimerFreq = ((ClockMultiplier * BaseFreq) / ClockDivide);
+
+ if (StableTimerFreq == 0x0) {
+ASSERT (FALSE);
+ }
+
+ return StableTimerFreq;
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+ UINT64 CurrentTicks, ExceptedTicks, Remaining;
+ RETURN_STATUS Status;
+
+ Status = SafeUint64Mult (MicroSeconds, CalcConstFreq (), );
+ ASSERT_RETURN_ERROR (Status);
+
+ ExceptedTicks = DivU64x32 (Remaining, 100U);
+ CurrentTicks = AsmReadStableCounter ();
+ ExceptedTicks += CurrentTicks;
+
+ do {
+CurrentTicks = AsmReadStableCounter ();
+ } while (CurrentTicks < ExceptedTicks);
+
+ return MicroSeconds;
+}
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+ UINTN MicroSeconds;
+
+ // Round up to 1us Tick Number
+ MicroSeconds = NanoSeconds / 1000;
+ MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;
+
+ MicroSecondDelay (MicroSeconds);
+
+ return NanoSeconds;
+}
+
+/**
+ Retrieves the current value of a 64-bit free running Stable Counter.
+
+ The LoongArch defines a constant frequency timer, whose main body is a
+ 64-bit
[edk2-devel] [PATCH v8 10/37] MdePkg: Add some comments for LoongArch exceptions
Added some comments for registing LoongArch exceptions.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Reviewed-by: Liming Gao
---
MdePkg/Include/Protocol/DebugSupport.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/MdePkg/Include/Protocol/DebugSupport.h
b/MdePkg/Include/Protocol/DebugSupport.h
index 9742663619..06f99ba7f7 100644
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -683,6 +683,20 @@ typedef struct {
//
// LoongArch processor exception types.
//
+// The exception types is located in the CSR ESTAT
+// register offset 16 bits, width 6 bits.
+//
+// If you want to register an exception hook, you can
+// shfit the number left by 16 bits, and the exception
+// handler will know the types.
+//
+// For example:
+// mCpu->CpuRegisterInterruptHandler (
+// mCpu,
+// (EXCEPT_LOONGARCH_PPI << CSR_ESTAT_EXC_SHIFT),
+// PpiExceptionHandler
+// );
+//
#define EXCEPT_LOONGARCH_INT 0
#define EXCEPT_LOONGARCH_PIL 1
#define EXCEPT_LOONGARCH_PIS 2
--
2.27.0
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[edk2-devel] [PATCH v8 09/37] MdePkg: Add a new library named PeiServicesTablePointerLibKs0
Adding PeiServicesTablePointerLibKs0 for LoongArch64, which provides
setting and getting the PEI service table pointer through the CSR KS0
register.
The idea of this library is derived from
ArmPkg/Library/PeiServicesTablePointerLib/
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Chao Li
Reviewed-by: Liming Gao
---
.../Library/PeiServicesTablePointerLib.h | 9 +-
.../PeiServicesTablePointer.c | 87 +++
.../PeiServicesTablePointerLibKs0.inf | 37
.../PeiServicesTablePointerLibKs0.uni | 20 +
MdePkg/MdePkg.dsc | 3 +
5 files changed, 152 insertions(+), 4 deletions(-)
create mode 100644
MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
create mode 100644
MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf
create mode 100644
MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.uni
diff --git a/MdePkg/Include/Library/PeiServicesTablePointerLib.h
b/MdePkg/Include/Library/PeiServicesTablePointerLib.h
index 61635eff00..f85c38363c 100644
--- a/MdePkg/Include/Library/PeiServicesTablePointerLib.h
+++ b/MdePkg/Include/Library/PeiServicesTablePointerLib.h
@@ -52,10 +52,11 @@ SetPeiServicesTablePointer (
immediately preceding the Interrupt Descriptor Table (IDT) in memory.
For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
immediately preceding the Interrupt Descriptor Table (IDT) in memory.
- For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
- a dedicated CPU register. This means that there is no memory storage
- associated with storing the PEI Services Table pointer, so no additional
- migration actions are required for Itanium or ARM CPUs.
+ For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer
+ is stored in a dedicated CPU register. This means that there is no
+ memory storage associated with storing the PEI Services Table pointer,
+ so no additional migration actions are required for Itanium, ARM and
+ LoongArch CPUs.
**/
VOID
diff --git
a/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
new file mode 100644
index 00..f9800936b2
--- /dev/null
+++ b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
@@ -0,0 +1,87 @@
+/** @file
+ PEI Services Table Pointer Library For Reigseter Mechanism.
+
+ This library is used for PEIM which does executed from flash device directly
but
+ executed in memory.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.
+ Copyright (c) 2024 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+
+/**
+ Caches a pointer PEI Services Table.
+
+ Caches the pointer to the PEI Services Table specified by
PeiServicesTablePointer
+ in a platform specific manner.
+
+ If PeiServicesTablePointer is NULL, then ASSERT().
+
+ @paramPeiServicesTablePointer The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer
+ )
+{
+ ASSERT (PeiServicesTablePointer != NULL);
+ CsrWrite (LOONGARCH_CSR_KS0, (UINTN)PeiServicesTablePointer);
+}
+
+/**
+ Retrieves the cached value of the PEI Services Table pointer.
+
+ Returns the cached value of the PEI Services Table pointer in a CPU specific
manner
+ as specified in the CPU binding section of the Platform Initialization
Pre-EFI
+ Initialization Core Interface Specification.
+
+ If the cached PEI Services Table pointer is NULL, then ASSERT().
+
+ @return The pointer to PeiServices.
+
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+ VOID
+ )
+{
+ CONST EFI_PEI_SERVICES **PeiServices;
+
+ PeiServices = (CONST EFI_PEI_SERVICES **)(CsrRead (LOONGARCH_CSR_KS0));
+ ASSERT (PeiServices != NULL);
+ return PeiServices;
+}
+
+/**
+ Perform CPU specific actions required to migrate the PEI Services Table
+ pointer from temporary RAM to permanent RAM.
+
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer
+ is stored in a dedicated CPU register. This means that there is no
+ memory storage associated with storing the PEI Services Table pointer,
+ so no additional migration actions are required for Itanium, ARM and
+ LoongArch CPUs.
+
+**/
+VOID
+EFIAPI
[edk2-devel] [PATCH v8 08/37] MdePkg: Add IOCSR operation for LoongArch
Add IoCsrRead8, IoCsrRead16, IoCsrRead32, IoCsrRead64, IoCsrWrite8, IoCsrWrite16, IoCsrWrite32, IoCsrWrite64 to operate the IOCSR registers of LoongArch architecture. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Acked-by: Michael D Kinney Reviewed-by: Liming Gao --- MdePkg/Include/Library/BaseLib.h | 112 +++ MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Library/BaseLib/LoongArch64/IoCsr.S | 120 + 3 files changed, 233 insertions(+) create mode 100644 MdePkg/Library/BaseLib/LoongArch64/IoCsr.S diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 4e97368ae2..1fff0fb224 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -396,6 +396,118 @@ CsrXChg ( IN UINTN Mask ); +/** + IO CSR read byte operation. + + @param[in] Select IO CSR read instruction select values. + + @return The return value of iocsrrd.b instruction. + +**/ +UINT8 +IoCsrRead8 ( + IN UINTN Select + ); + +/** + IO CSR read half word operation. + + @param[in] Select IO CSR read instruction select values. + + @return The return value of iocsrrd.h instruction. + +**/ +UINT16 +IoCsrRead16 ( + IN UINTN Select + ); + +/** + IO CSR read word operation. + + @param[in] Select IO CSR read instruction select values. + + @return The return value of iocsrrd.w instruction. + +**/ +UINT32 +IoCsrRead32 ( + IN UINTN Select + ); + +/** + IO CSR read double word operation. Only for LoongArch64. + + @param[in] Select IO CSR read instruction select values. + + @return The return value of iocsrrd.d instruction. + +**/ +UINT64 +IoCsrRead64 ( + IN UINTN Select + ); + +/** + IO CSR write byte operation. + + @param[in] Select IO CSR write instruction select values. + @param[in] ValueThe iocsrwr.b will write the value. + + @return VOID. + +**/ +VOID +IoCsrWrite8 ( + IN UINTN Select, + IN UINT8 Value + ); + +/** + IO CSR write half word operation. + + @param[in] Select IO CSR write instruction select values. + @param[in] ValueThe iocsrwr.h will write the value. + + @return VOID. + +**/ +VOID +IoCsrWrite16 ( + IN UINTN Select, + IN UINT16 Value + ); + +/** + IO CSR write word operation. + + @param[in] Select IO CSR write instruction select values. + @param[in] ValueThe iocsrwr.w will write the value. + + @return VOID. + +**/ +VOID +IoCsrWrite32 ( + IN UINTN Select, + IN UINT32 Value + ); + +/** + IO CSR write double word operation. Only for LoongArch64. + + @param[in] Select IO CSR write instruction select values. + @param[in] ValueThe iocsrwr.d will write the value. + + @return VOID. + +**/ +VOID +IoCsrWrite64 ( + IN UINTN Select, + IN UINT64 Value + ); + #endif // defined (MDE_CPU_LOONGARCH64) // diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 7c46306883..4dbe94be71 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -413,6 +413,7 @@ LoongArch64/Csr.c LoongArch64/InternalSwitchStack.c LoongArch64/AsmCsr.S | GCC + LoongArch64/IoCsr.S | GCC LoongArch64/GetInterruptState.S | GCC LoongArch64/EnableInterrupts.S| GCC LoongArch64/DisableInterrupts.S | GCC diff --git a/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S b/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S new file mode 100644 index 00..a659908bc4 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S @@ -0,0 +1,120 @@ +#-- +# +# LoongArch ASM IO CSR operation functions +# +# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#-- + +ASM_GLOBAL ASM_PFX (IoCsrRead8) +ASM_GLOBAL ASM_PFX (IoCsrRead16) +ASM_GLOBAL ASM_PFX (IoCsrRead32) +ASM_GLOBAL ASM_PFX (IoCsrRead64) + +ASM_GLOBAL ASM_PFX (IoCsrWrite8) +ASM_GLOBAL ASM_PFX (IoCsrWrite16) +ASM_GLOBAL ASM_PFX (IoCsrWrite32) +ASM_GLOBAL ASM_PFX (IoCsrWrite64) + +#/** +# IO CSR read byte operation. +# +# @param[in] Select IO CSR read instruction select values. +# +# @return The return value of iocsrrd.b instruction. +# +#**/ +ASM_PFX (IoCsrRead8): + iocsrrd.b $a0, $a0 + jirl$zero, $ra, 0 + +#/** +# IO CSR read half word operation. +# +# @param[in] Select IO CSR read instruction select values. +# +# @return The return value of iocsrrd.h instruction. +# +#**/ +ASM_PFX (IoCsrRead16): + iocsrrd.h $a0, $a0 + jirl$zero, $ra, 0 + +#/** +# IO CSR read word operation. +# +# @param[in] Select IO CSR read instruction select values. +# +# @return The return value of iocsrrd.w instruction.
[edk2-devel] [PATCH v8 07/37] MdePkg: Add CSR operation for LoongArch
Add CsrRead, CsrWrite and CsrXChg functions for LoongArch, and use them to operate the CSR register of LoongArch architecture. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Co-authored-by: Bibo Mao Acked-by: Michael D Kinney Reviewed-by: Liming Gao --- MdePkg/Include/Library/BaseLib.h| 45 +++ MdePkg/Library/BaseLib/BaseLib.inf | 2 + MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S | 422 MdePkg/Library/BaseLib/LoongArch64/Csr.c| 81 4 files changed, 550 insertions(+) create mode 100644 MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Csr.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 29009adbc9..4e97368ae2 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -351,6 +351,51 @@ AsmReadStableCounter ( VOID ); +/** + CSR read operation. + + @param[in] Select CSR read instruction select values. + + @return The return value of csrrd instruction, return -1 means no CSR instruction + is found. +**/ +UINTN +CsrRead ( + IN UINT16 Select + ); + +/** + CSR write operation. + + @param[in] Select CSR write instruction select values. + @param[in] ValueThe csrwr will write the value. + + @return The return value of csrwr instruction, that is, store the old value of + the register, return -1 means no CSR instruction is found. +**/ +UINTN +CsrWrite ( + IN UINT16 Select, + IN UINTN Value + ); + +/** + CSR exchange operation. + + @param[in] Select CSR exchange instruction select values. + @param[in] ValueThe csrxchg will write the value. + @param[in] Mask The csrxchg mask value. + + @return The return value of csrxchg instruction, that is, store the old value of + the register, return -1 means no CSR instruction is found. +**/ +UINTN +CsrXChg ( + IN UINT16 Select, + IN UINTN Value, + IN UINTN Mask + ); + #endif // defined (MDE_CPU_LOONGARCH64) // diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 1dad587b0c..7c46306883 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -410,7 +410,9 @@ [Sources.LOONGARCH64] Math64.c Unaligned.c + LoongArch64/Csr.c LoongArch64/InternalSwitchStack.c + LoongArch64/AsmCsr.S | GCC LoongArch64/GetInterruptState.S | GCC LoongArch64/EnableInterrupts.S| GCC LoongArch64/DisableInterrupts.S | GCC diff --git a/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S new file mode 100644 index 00..3a879411f5 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S @@ -0,0 +1,422 @@ +#-- +# +# LoongArch ASM CSR operation functions +# +# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#-- + +#include + +ASM_GLOBAL ASM_PFX (AsmCsrRead) +ASM_GLOBAL ASM_PFX (AsmCsrWrite) +ASM_GLOBAL ASM_PFX (AsmCsrXChg) + +.macro AsmCsrRd Sel + csrrd $a0, \Sel + jirl$zero, $ra, 0 +.endm + +.macro AsmCsrWr Sel + csrwr $a0, \Sel + jirl$zero, $ra, 0 +.endm + +.macro AsmCsrXChange Sel + csrxchg $a0, $a1, \Sel + jirl$zero, $ra, 0 +.endm + +ASM_PFX(AsmCsrRead): + blt $a0, $zero, ReadSelNumErr + li.w $t0, LOONGARCH_CSR_EBASE + bltu $t0, $a0, TlbCsrRd + +BasicCsrRd: + la.pcrel $t0, BasicCsrRead + alsl.d $t0, $a0, $t0, 3 + jirl $zero, $t0, 0 + +TlbCsrRd: + li.w $t0, LOONGARCH_CSR_TLBIDX + bltu $a0, $t0, ReadSelNumErr + li.w $t0, LOONGARCH_CSR_RVACFG + bltu $t0, $a0, CfgCsrRd + la.pcrel $t0, TlbCsrRead + addi.w $t1, $a0, -LOONGARCH_CSR_TLBIDX + alsl.d $t0, $t1, $t0, 3 + jirl $zero, $t0, 0 + +CfgCsrRd: + li.w $t0, LOONGARCH_CSR_CPUNUM + bltu $a0, $t0, ReadSelNumErr + li.w $t0, LOONGARCH_CSR_PRCFG3 + bltu $t0, $a0, KcsCsrRd + la.pcrel $t0, CfgCsrRead + addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM + alsl.d $t0, $t1, $t0, 3 + jirl $zero, $t0, 0 + +KcsCsrRd: + li.w $t0, LOONGARCH_CSR_KS0 + bltu $a0, $t0, ReadSelNumErr + li.w $t0, LOONGARCH_CSR_KS8 + bltu $t0, $a0, StableTimerCsrRd + la.pcrel $t0, KcsCsrRead + addi.w $t1, $a0, -LOONGARCH_CSR_KS0 + alsl.d $t0, $t1, $t0, 3 + jirl $zero, $t0, 0 + +StableTimerCsrRd: + li.w $t0, LOONGARCH_CSR_TMID + bltu $a0, $t0, ReadSelNumErr + li.w $t0, LOONGARCH_CSR_TINTCLR + bltu $t0, $a0, TlbRefillCsrRd + la.pcrel $t0, StableTimerCsrRead + addi.w $t1, $a0, -LOONGARCH_CSR_TMID + alsl.d $t0, $t1, $t0, 3 + jirl $zero, $t0, 0 + +TlbRefillCsrRd: +
[edk2-devel] [PATCH v8 06/37] MdePkg: Add read stable counter operation for LoongArch
Add LoongArch gets stable counter ASM function. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Acked-by: Michael D Kinney Reviewed-by: Liming Gao --- MdePkg/Include/Library/BaseLib.h | 12 ++ MdePkg/Library/BaseLib/BaseLib.inf| 1 + .../BaseLib/LoongArch64/ReadStableCounter.S | 24 +++ 3 files changed, 37 insertions(+) create mode 100644 MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index d64e406b7c..29009adbc9 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -339,6 +339,18 @@ AsmCpucfg ( OUT UINT32 *Data ); +/** + Gets the timer count value. + + @param[] VOID + @retval timer count value. + +**/ +UINTN +AsmReadStableCounter ( + VOID + ); + #endif // defined (MDE_CPU_LOONGARCH64) // diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 2f1e3b3d91..1dad587b0c 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -422,6 +422,7 @@ LoongArch64/SwitchStack.S | GCC LoongArch64/ExceptionBase.S | GCC LoongArch64/Cpucfg.S | GCC + LoongArch64/ReadStableCounter.S | GCC [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S b/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S new file mode 100644 index 00..aa74ff603e --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S @@ -0,0 +1,24 @@ +#-- +# +# LoongArch Read Stable Counter +# +# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#-- + +ASM_GLOBAL ASM_PFX(AsmReadStableCounter) + +#/** +# Gets the timer count value. +# +# @param[] VOID +# @retval timer count value. +# +#**/ + +ASM_PFX(AsmReadStableCounter): + rdtime.d $a0, $zero + jirl $zero, $ra, 0 + .end -- 2.27.0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114532): https://edk2.groups.io/g/devel/message/114532 Mute This Topic: https://groups.io/mt/103971643/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v8 05/37] MdePkg: Add LoongArch Cpucfg function
Add LoongArch AsmCpucfg function and Cpucfg definitions.
Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of
EccCheck.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Acked-by: Michael D Kinney
Reviewed-by: Liming Gao
---
MdePkg/Include/Library/BaseLib.h | 12 +
MdePkg/Include/Register/LoongArch64/Cpucfg.h | 565 +++
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S | 26 +
MdePkg/MdePkg.ci.yaml| 3 +-
5 files changed, 606 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Include/Register/LoongArch64/Cpucfg.h
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 91322d2dfa..d64e406b7c 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -327,6 +327,18 @@ DisableLocalInterrupts (
IN UINT16
);
+/**
+ Read CPUCFG register.
+
+ @param Index Specifies the register number of the CPUCFG to read the data.
+ @param Data A pointer to the variable used to store the CPUCFG register
value.
+**/
+VOID
+AsmCpucfg (
+ IN UINT32 Index,
+ OUT UINT32 *Data
+ );
+
#endif // defined (MDE_CPU_LOONGARCH64)
//
diff --git a/MdePkg/Include/Register/LoongArch64/Cpucfg.h
b/MdePkg/Include/Register/LoongArch64/Cpucfg.h
new file mode 100644
index 00..570748b194
--- /dev/null
+++ b/MdePkg/Include/Register/LoongArch64/Cpucfg.h
@@ -0,0 +1,565 @@
+/** @file
+ CPUCFG definitions.
+
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef CPUCFG_H_
+#define CPUCFG_H_
+
+/**
+ CPUCFG REG0 Information
+
+ @code
+ CPUCFG_REG0_INFO_DATA
+ **/
+#define CPUCFG_REG0_INFO 0x0
+
+/**
+ CPUCFG REG0 Information returned data.
+ #CPUCFG_REG0_INFO
+ **/
+typedef union {
+ struct {
+///
+/// [Bit 31:0] Processor Identity.
+///
+UINT32PRID : 32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32Uint32;
+} CPUCFG_REG0_INFO_DATA;
+
+/**
+ CPUCFG REG1 Information
+
+ @code
+ CPUCFG_REG1_INFO_DATA
+ **/
+#define CPUCFG_REG1_INFO 0x1
+
+/**
+ CPUCFG REG1 Information returned data.
+ #CPUCFG_REG1_INFO
+ **/
+typedef union {
+ struct {
+///
+/// [Bit 1:0] Architecture:
+/// 2'b00 indicates the implementation of simplified
LoongAarch32;
+/// 2'b01 indicates the implementation of LoongAarch32;
+/// 2'b10 indicates the implementation of LoongAarch64;
+/// 2'b11 reserved;
+///
+UINT32ARCH : 2;
+///
+/// [Bit 2] Paging mapping mode. A value of 1 indicates the processor MMU
supports
+/// page mapping mode.
+///
+UINT32PGMMU : 1;
+///
+/// [Bit 3] A value of 1 indicates the processor supports the IOCSR
instruction.
+///
+UINT32IOCSR : 1;
+///
+/// [Bit 11:4] Physical address bits. The supported physical address bits
PALEN value
+/// minus 1.
+///
+UINT32PALEN : 8;
+///
+/// [Bit 19:12] Virtual address bits. The supported virtual address bits
VALEN value
+/// minus 1.
+///
+UINT32VALEN : 8;
+///
+/// [Bit 20] Non-aligned Memory Access. A value of 1 indicates the
processor supports
+/// non-aligned memory access.
+///
+UINT32UAL : 1;
+///
+/// [Bit 21] Page Read Inhibit. A value of 1 indicates the processor
supports page
+/// attribute of "Read Inhibit".
+///
+UINT32RI: 1;
+///
+/// [Bit 22] Page Execution Protection. A value of 1 indicates the
processor supports
+/// page attribute of "Execution Protection".
+///
+UINT32EP: 1;
+///
+/// [Bit 23] A value of 1 indicates the processor supports for page
attributes of RPLV.
+///
+UINT32RPLV : 1;
+///
+/// [Bit 24] Huge Page. A value of 1 indicates the processor supports page
attribute
+/// of huge page.
+///
+UINT32HP: 1;
+///
+/// [Bit 25] A value of 1 indicates that the string of processor product
information
+/// is recorded at address 0 of the IOCSR access space.
+///
+UINT32IOCSR_BRD : 1;
+///
+/// [Bit 26] A value of 1 indicates that the external interrupt uses the
message
+/// interrupt mode, otherwise it is the level interrupt line mode.
+///
+UINT32MSG_INT : 1;
+///
+/// [Bit 31:27] Reserved.
+///
+UINT32Reserved : 5;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32Uint32;
+} CPUCFG_REG1_INFO_DATA;
+
+/**
+ CPUCFG REG2 Information
+
+ @code
+ CPUCFG_REG2_INFO_DATA
+ **/
+#define CPUCFG_REG2_INFO 0x2
+
+/**
+ CPUCFG REG2 Information
[edk2-devel] [PATCH v8 04/37] MdePkg: Add LoongArch64 local interrupt function set into BaseLib
Adding LoongArch local interrupt function set, which is used to control the opening or closing of the local interrupt when the global interrupt is enabled. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Acked-by: Michael D Kinney Reviewed-by: Liming Gao --- MdePkg/Include/Library/BaseLib.h | 20 + .../BaseLib/LoongArch64/DisableInterrupts.S | 22 ++- .../BaseLib/LoongArch64/EnableInterrupts.S| 22 ++- 3 files changed, 54 insertions(+), 10 deletions(-) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 7117c4288f..91322d2dfa 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -307,6 +307,26 @@ SetTlbRebaseAddress ( IN UINT64 ); +/** + Enables local CPU interrupts. + + @param Needs to enable local interrupt bit. +**/ +VOID +EnableLocalInterrupts ( + IN UINT16 + ); + +/** + Disables local CPU interrupts. + + @param Needs to disable local interrupt bit. +**/ +VOID +DisableLocalInterrupts ( + IN UINT16 + ); + #endif // defined (MDE_CPU_LOONGARCH64) // diff --git a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S index 0f228339af..8f9ee888b1 100644 --- a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S +++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S @@ -1,21 +1,33 @@ #-- # -# LoongArch interrupt disable +# LoongArch interrupt disable operations # -# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved. +# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # #-- +#include +#include + +ASM_GLOBAL ASM_PFX(DisableLocalInterrupts) ASM_GLOBAL ASM_PFX(DisableInterrupts) #/** -# Disables CPU interrupts. +# Disables local CPU interrupts. +# +# @param Needs to disable local interrupt bit. #**/ +ASM_PFX(DisableLocalInterrupts): + csrxchg $zero, $a0, LOONGARCH_CSR_ECFG + jirl$zero, $ra, 0 +#/** +# Disables global CPU interrupts. +#**/ ASM_PFX(DisableInterrupts): - li.w$t0, 0x4 - csrxchg $zero, $t0, 0x0 + li.w$t0, BIT2 + csrxchg $zero, $t0, LOONGARCH_CSR_CRMD jirl$zero, $ra, 0 .end diff --git a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S index 3c34fb2cdd..126c7b49b3 100644 --- a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S +++ b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S @@ -1,21 +1,33 @@ #-- # -# LoongArch interrupt enable +# LoongArch interrupt enable operations # -# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved. +# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # #-- +#include +#include + +ASM_GLOBAL ASM_PFX(EnableLocalInterrupts) ASM_GLOBAL ASM_PFX(EnableInterrupts) #/** -# Enables CPU interrupts. +# Enables local CPU interrupts. +# +# @param Needs to enable local interrupt bit. #**/ +ASM_PFX(EnableLocalInterrupts): + csrxchg $a0, $a0, LOONGARCH_CSR_ECFG + jirl$zero, $ra, 0 +#/** +# Enables global CPU interrupts. +#**/ ASM_PFX(EnableInterrupts): - li.w$t0, 0x4 - csrxchg $t0, $t0, 0x0 + li.w$t0, BIT2 + csrxchg $t0, $t0, LOONGARCH_CSR_CRMD jirl$zero, $ra, 0 .end -- 2.27.0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114530): https://edk2.groups.io/g/devel/message/114530 Mute This Topic: https://groups.io/mt/103971639/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v8 03/37] MdePkg: Add LoongArch64 exception function set into BaseLib
Adding SetExceptionBaseAddress and SetTlbRebaseAddress functions
for LoongArch64.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Acked-by: Michael D Kinney
Reviewed-by: Liming Gao
---
MdePkg/Include/Library/BaseLib.h | 20 +
MdePkg/Library/BaseLib/BaseLib.inf| 1 +
.../BaseLib/LoongArch64/ExceptionBase.S | 41 +++
3 files changed, 62 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index ca0d06c7f3..7117c4288f 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -287,6 +287,26 @@ typedef struct {
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+/*
+ * Set the exception base address for LoongArch.
+ *
+ * @param ExceptionBaseAddress The exception base address, must be aligned
greater than or qeual to 4K .
+ */
+VOID
+SetExceptionBaseAddress (
+ IN UINT64
+ );
+
+/*
+ * Set the TlbRebase address for LoongArch.
+ *
+ * @param TlbRebaseAddress The TlbRebase address, must be aligned greater
than or qeual to 4K .
+ */
+VOID
+SetTlbRebaseAddress (
+ IN UINT64
+ );
+
#endif // defined (MDE_CPU_LOONGARCH64)
//
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
b/MdePkg/Library/BaseLib/BaseLib.inf
index 6b46949be3..22b38b59e7 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -420,6 +420,7 @@
LoongArch64/CpuPause.S| GCC
LoongArch64/SetJumpLongJump.S | GCC
LoongArch64/SwitchStack.S | GCC
+ LoongArch64/ExceptionBase.S | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
b/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
new file mode 100644
index 00..b6e90a8f28
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
@@ -0,0 +1,41 @@
+#--
+#
+# LoongArch set exception base address operations
+#
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+
+#include
+#include
+
+ASM_GLOBAL ASM_PFX(SetExceptionBaseAddress)
+ASM_GLOBAL ASM_PFX(SetTlbRebaseAddress)
+
+#/**
+# Set the exception base address for LoongArch.
+#
+# @param ExceptionBaseAddress The exception base address, must be aligned
greater than or qeual to 4K .
+#**/
+ASM_PFX(SetExceptionBaseAddress):
+ csrrd $t0, LOONGARCH_CSR_ECFG
+ li.d$t1, ~(BIT16 | BIT17 | BIT18)
+ and $t0, $t0, $t1
+ csrwr $t0, LOONGARCH_CSR_ECFG
+
+ move$t0, $a0
+ csrwr $t0, LOONGARCH_CSR_EBASE
+ jirl$zero, $ra, 0
+
+#/**
+# Set the TlbRebase address for LoongArch.
+#
+# @param TlbRebaseAddress The TlbRebase address, must be aligned greater
than or qeual to 4K .
+#**/
+ASM_PFX(SetTlbRebaseAddress):
+ move$t0, $a0
+ csrwr $t0, LOONGARCH_CSR_TLBREBASE
+ jirl$zero, $ra, 0
+.end
--
2.27.0
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[edk2-devel] [PATCH v8 02/37] MdePkg: Add LoongArch64 FPU function set into BaseCpuLib
Adding InitializeFloatingPointUnits, EnableFloatingPointUnits and DisableFloatingPointUnits functions for LoongArch64. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Acked-by: Michael D Kinney Reviewed-by: Liming Gao --- MdePkg/Include/Library/CpuLib.h | 43 ++-- MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 7 ++- .../Library/BaseCpuLib/LoongArch/DisableFpu.S | 17 +++ .../Library/BaseCpuLib/LoongArch/EnableFpu.S | 17 +++ .../BaseCpuLib/LoongArch/InitializeFpu.S | 51 +++ 5 files changed, 128 insertions(+), 7 deletions(-) create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/InitializeFpu.S diff --git a/MdePkg/Include/Library/CpuLib.h b/MdePkg/Include/Library/CpuLib.h index 3f29937dc7..27f3f82ab9 100644 --- a/MdePkg/Include/Library/CpuLib.h +++ b/MdePkg/Include/Library/CpuLib.h @@ -8,6 +8,7 @@ As a result, these services could not be defined in the Base Library. Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved. +Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -41,14 +42,16 @@ CpuFlushTlb ( VOID ); -#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) || defined (MDE_CPU_LOONGARCH64) /** + Initialize the CPU floating point units. + Initializes floating point units for requirement of UEFI specification. - This function initializes floating-point control word to 0x027F (all exceptions - masked,double-precision, round-to-nearest) and multimedia-extensions control word - (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero - for masked underflow). + For IA32 and X64, this function initializes floating-point control word to 0x027F + (all exceptions masked,double-precision, round-to-nearest) and multimedia-extensions + control word (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, + flush to zero for masked underflow). **/ VOID EFIAPI @@ -56,6 +59,10 @@ InitializeFloatingPointUnits ( VOID ); +#endif + +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) + /** Determine if the standard CPU signature is "AuthenticAMD". @retval TRUE The CPU signature matches. @@ -89,4 +96,30 @@ GetCpuSteppingId ( #endif +#if defined (MDE_CPU_LOONGARCH64) + +/** + Enable the CPU floating point units. + + Enable the CPU floating point units. +**/ +VOID +EFIAPI +EnableFloatingPointUnits ( + VOID + ); + +/** + Disable the CPU floating point units. + + Disable the CPU floating point units. +**/ +VOID +EFIAPI +DisableFloatingPointUnits ( + VOID + ); + +#endif + #endif diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf index 9a162afe6d..89f6272f11 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -65,8 +65,11 @@ RiscV/Cpu.S [Sources.LOONGARCH64] - LoongArch/CpuFlushTlb.S | GCC - LoongArch/CpuSleep.S| GCC + LoongArch/CpuFlushTlb.S | GCC + LoongArch/CpuSleep.S | GCC + LoongArch/InitializeFpu.S | GCC + LoongArch/EnableFpu.S | GCC + LoongArch/DisableFpu.S| GCC [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S b/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S new file mode 100644 index 00..33c6bf3411 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S @@ -0,0 +1,17 @@ +#-- +# +# DisableFloatingPointUnits() for LoongArch64 +# +# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#-- +ASM_GLOBAL ASM_PFX(DisableFloatingPointUnits) + +ASM_PFX(DisableFloatingPointUnits): + li.w$t0, 0x1 + csrxchg $zero, $t0, 0x2 + + jirl $zero, $ra, 0 + .end diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S b/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S new file mode 100644 index 00..3e4f7411f1 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S @@ -0,0 +1,17 @@ +#-- +# +# EnableFloatingPointUnits() for LoongArch64 +# +# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#-- +ASM_GLOBAL ASM_PFX(EnableFloatingPointUnits) + +ASM_PFX(EnableFloatingPointUnits): + li.w$t0, 0x1 +
[edk2-devel] [PATCH v8 01/37] MdePkg: Add the header file named Csr.h for LoongArch64
Adding Csr.h for LoongArch64, it is use for accessing the CSR registers. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Acked-by: Michael D Kinney Reviewed-by: Liming Gao --- MdePkg/Include/Register/LoongArch64/Csr.h | 263 ++ 1 file changed, 263 insertions(+) create mode 100644 MdePkg/Include/Register/LoongArch64/Csr.h diff --git a/MdePkg/Include/Register/LoongArch64/Csr.h b/MdePkg/Include/Register/LoongArch64/Csr.h new file mode 100644 index 00..aa22a26564 --- /dev/null +++ b/MdePkg/Include/Register/LoongArch64/Csr.h @@ -0,0 +1,263 @@ +/** @file + + Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: +- EXC - Exception +- CSR - CPU Status Register +**/ + +#ifndef LOONGARCH_CSR_H_ +#define LOONGARCH_CSR_H_ + +#include + +// +// CSR register numbers +// + +// +// Basic CSR registers +// +#define LOONGARCH_CSR_CRMD 0x0 +#define LOONGARCH_CSR_PRMD 0x1 +#define LOONGARCH_CSR_EUEN 0x2 +#define CSR_EUEN_LBTEN_SHIFT 3 +#define CSR_EUEN_LBTEN (0x1ULL << CSR_EUEN_LBTEN_SHIFT) +#define CSR_EUEN_LASXEN_SHIFT 2 +#define CSR_EUEN_LASXEN(0x1ULL << CSR_EUEN_LASXEN_SHIFT) +#define CSR_EUEN_LSXEN_SHIFT 1 +#define CSR_EUEN_LSXEN (0x1ULL << CSR_EUEN_LSXEN_SHIFT) +#define CSR_EUEN_FPEN_SHIFT0 +#define CSR_EUEN_FPEN (0x1ULL << CSR_EUEN_FPEN_SHIFT) +#define LOONGARCH_CSR_MISC 0x3 +#define LOONGARCH_CSR_ECFG 0x4 + +#define LOONGARCH_CSR_ESTAT 0x5 +#define CSR_ESTAT_ESUBCODE_SHIFT 22 +#define CSR_ESTAT_ESUBCODE_WIDTH 9 +#define CSR_ESTAT_ESUBCODE(0x1ffULL << CSR_ESTAT_ESUBCODE_SHIFT) +#define CSR_ESTAT_EXC_SHIFT 16 +#define CSR_ESTAT_EXC_WIDTH 6 +#define CSR_ESTAT_EXC (0x3FULL << CSR_ESTAT_EXC_SHIFT) +#define CSR_ESTAT_IS_SHIFT0 +#define CSR_ESTAT_IS_WIDTH15 +#define CSR_ESTAT_IS (0x7FFFULL << CSR_ESTAT_IS_SHIFT) + +#define LOONGARCH_CSR_ERA0x6 +#define LOONGARCH_CSR_BADV 0x7 +#define LOONGARCH_CSR_BADI 0x8 +#define LOONGARCH_CSR_EBASE 0xC // Exception entry base address + +// +// TLB related CSR registers +// +#define LOONGARCH_CSR_TLBIDX 0x10 // TLB Index, EHINV, PageSize, NP +#define LOONGARCH_CSR_TLBEHI 0x11 // TLB EntryHi +#define LOONGARCH_CSR_TLBELO0 0x12 // TLB EntryLo0 +#define LOONGARCH_CSR_TLBELO1 0x13 // TLB EntryLo1 +#define LOONGARCH_CSR_ASID0x18 // ASID +#define LOONGARCH_CSR_PGDL0x19 // Page table base address when VA[47] = 0 +#define LOONGARCH_CSR_PGDH0x1A // Page table base address when VA[47] = 1 +#define LOONGARCH_CSR_PGD 0x1B // Page table base +#define LOONGARCH_CSR_PWCTL0 0x1C // PWCtl0 +#define LOONGARCH_CSR_PWCTL1 0x1D // PWCtl1 +#define LOONGARCH_CSR_STLBPGSIZE 0x1E +#define LOONGARCH_CSR_RVACFG 0x1F + +/// +/// Page table property definitions +/// +#define PAGE_VALID_SHIFT 0 +#define PAGE_DIRTY_SHIFT 1 +#define PAGE_PLV_SHIFT 2 // 2~3, two bits +#define CACHE_SHIFT4 // 4~5, two bits +#define PAGE_GLOBAL_SHIFT 6 +#define PAGE_HUGE_SHIFT6 // HUGE is a PMD bit + +#define PAGE_HGLOBAL_SHIFT 12 // HGlobal is a PMD bit +#define PAGE_PFN_SHIFT 12 +#define PAGE_PFN_END_SHIFT 48 +#define PAGE_NO_READ_SHIFT 61 +#define PAGE_NO_EXEC_SHIFT 62 +#define PAGE_RPLV_SHIFT 63 + +/// +/// Used by TLB hardware (placed in EntryLo*) +/// +#define PAGE_VALID((UINTN)(1) << PAGE_VALID_SHIFT) +#define PAGE_DIRTY((UINTN)(1) << PAGE_DIRTY_SHIFT) +#define PAGE_PLV ((UINTN)(3) << PAGE_PLV_SHIFT) +#define PAGE_GLOBAL ((UINTN)(1) << PAGE_GLOBAL_SHIFT) +#define PAGE_HUGE ((UINTN)(1) << PAGE_HUGE_SHIFT) +#define PAGE_HGLOBAL ((UINTN)(1) << PAGE_HGLOBAL_SHIFT) +#define PAGE_NO_READ ((UINTN)(1) << PAGE_NO_READ_SHIFT) +#define PAGE_NO_EXEC ((UINTN)(1) << PAGE_NO_EXEC_SHIFT) +#define PAGE_RPLV ((UINTN)(1) << PAGE_RPLV_SHIFT) +#define CACHE_MASK((UINTN)(3) << CACHE_SHIFT) +#define PFN_SHIFT (EFI_PAGE_SHIFT - 12 + PAGE_PFN_SHIFT) + +#define PLV_KERNEL 0 +#define PLV_USER3 + +#define PAGE_USER(PLV_USER << PAGE_PLV_SHIFT) +#define PAGE_KERNEL (PLV_KERN << PAGE_PLV_SHIFT) + +#define CACHE_SUC (0 << CACHE_SHIFT) // Strong-ordered UnCached +#define CACHE_CC (1 << CACHE_SHIFT) // Coherent Cached +#define CACHE_WUC (2 << CACHE_SHIFT) // Weak-ordered UnCached + +// +// Config CSR registers +// +#define LOONGARCH_CSR_CPUNUM 0x20// CPU core number +#define LOONGARCH_CSR_PRCFG1 0x21// Config1 +#define LOONGARCH_CSR_PRCFG2 0x22// Config2 +#define LOONGARCH_CSR_PRCFG3 0x23// Config3 + +// +// Kscratch registers +// +#define LOONGARCH_CSR_KS0 0x30 +#define LOONGARCH_CSR_KS1 0x31 +#define LOONGARCH_CSR_KS2 0x32 +#define LOONGARCH_CSR_KS3 0x33 +#define
[edk2-devel] [PATCH v8 00/37] Enable LoongArch virtual machine in edk2
This patch set will enable LoongArch virtual machine in edk2, the new LoongArch virtual machine is located in OvmfPkg/LoongArchVirt/, it is a generic platform that dose not require any actual hardware. Patch1-Patch14: Submit the common library and driver for LoongArch virtual machine and real hardware. Such as base help functions, exception handel, MMU library, multiprocessor library etc. Patch15-Patch16: Add PrePiCpuIoSize for LoongArch64. and move ArmVirtPkg two PCDs into OvmfPkg for easier use by other architectures. Patch17-Patch29: LoongArch virtual machine private code, include SEC and PEI phase code, some library and drivers. Patch30: Add LoongArchVirt's self introduction-file. Modfied modues: MdePkg, UefiCpuPkg, EmbeddedPkg, ArmVirtPkg, OvmfPkg. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 PR: https://github.com/tianocore/edk2/pull/5208 **Changes from V1 to V2:** 1. Add Ray's Ack signature to patch 13. 2. Add LoongArchVirt's self introduction-file. And made a standalone patch for this change. **Changes from V2 to V3:** Compared with V2, there are 9 more patches, removed 2 libraries and 1 driver from OvmfPkg/LoongArchVrt. New patches: MdePkg: Add a new library named PeiServicesTablePointerLibReg MdePkg: Add method of LoongArch64 to PeiServicesTablePointerLibReg MdePkg: Add a PCD feature flag named PcdPciIoTranslationIsEnabled UefiCpuPkg: Add MMIO method in CpuIo2Dxe ArmVirtPkg: Enable UefiCpuPkg version CpuIo2Dxe ArmPkg: Remove ArmPciCpuIo2Dxe from ArmPkg OvmfPkg/RiscVVirt: Enable UefiCpuPkg version CpuIo2Dxe OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkg ArmVirtPkg: Move the PcdTerminalTypeGuidBuffer into OvmfPkg ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkg For the review opinions: 1. Add MMIO method to CpuIo2Dxe driver to accommodate more ARCH that require MMIO method, enable it on ARM, RISCV64 and LOONGARCH64. Questioner: Gerd, Sunil. 2. Move the FdtSerialProtAddressLib to OvmfPkg and enabled it on ARM and LOONGARCH64. Questioner: Gerd, Laszlo. 3. Add a new library in MdePkg named PeiServiceTablePointerLibReg for the Register Mechanism and enabled it on LOONGARCH64. Questioner: Laszlo. 4. Moved the ARM version of PlatformBootManagerLib to OvmfPkg/Library, and enabled it on ARM and LOONGARCH64. Questioner: Laszlo, Gerd. 5. Adjust the order of some inf file in ArmVirtPkg. Questioner: Sami. 6. Move the CpuMmuLib.h some architecture-specific PTE #defines into Csr.h. Questioner: Andrei. **Changes from V3 to V4:** Compared with V3, 1 patch moving ArmPciCpuIo2Dxe has been removed. Adjusted the code of the LoongArch64 CPU timer library. Rename PeiServiceTablePointerLibReg to PeiServiceTablePointerLibKs0. Fixed some typos. Remove some APIs of CpuMmuLib. For the review opinions: 1. Removed the patch that removed ArmPciCpuIo2Dxe, there are 15 platforms in edk2-platforms were affected, so wait for this patch series to be merged, then submit a patch to remove it. Questioner: Leif. 2. Renamed the PeiServiceTablePointLibReg to PeiServiceTablePointLibKs0. Currently, this library is specific to LoongArch architecture. Questioner: Laszlo, Liming. 3. Adjust some logic of LoongArch64 CPU timer library. Using the safe INT library and adjust the bit width of stable counter. Questioner: Laszlo. 4. Removed some APIs from CpuMmuLib. Change some APIs to private. Questioner: Ray. **Changes from V4 to V5:** Compared with V4, 1 patch adding PcdPciIoTranslationIsEnabled in MdePkg has been removed. Copy ArmPciCpuIo2Dxe to UefiCpuPkg and renamed it to CpuMmio2Dxe. Restore the definitions in MdePkg/Include/Protocol/DebugSupport.h, and just add some comments. For the review opinions: 1. Copy ArmPciCpuIo2Dxe to UefiCpuPkg so that more other ARCHs can use it easily. Questioner: Ray, Ard. 2. Restore the changes of MdePkg/Include/Protocol/DebugSupport.h. Questioner: Liming. 3. Ia32 X64 and LoongArch64 use a same API definition, InitializeFloatingPointUnits in CpuLib.h. Questioner: Liming. 4. Adjust API definition in CpuMmuLib.h. Questioner: Ray. **Changes from V5 to V6:** 1. Added Sunil "Reviewed-by" message to patches 20 and 21. 2. Added Bibo "Reviced-by" message to patches 27, 29, 32 and 34. 3. Added the IPI handler in SEC and PEI stage. Modified patches 11 and 15. 4. Adjust some code styles to suit CI ECC. 5. Adjust the way of AP wakeup from IPI. 6. Adjust the order between setting exceptions and copying exception handlers. **Changes from V6 to V7:** Compared with V6, 1 patch has been added. Added Bibo "Reviewed-by" message to new patches 26, 27, 29, 31, 32, 36, 37. Added Liming "Reviewed-by" message to all MdePkg changes. For the review opinions: 1. Moved the changes to OvmfPkg.dec from old patch 24 to new patch 23. Questioner: Laszlo. 2. Separate the changes to DebugSupport.h from old patch 11 and create a new patch 10. Questioner: Liming. **Changes from V7 to V8:** Adjusted the folders layout in UefiCpuPkg, most
[edk2-devel] [PATCH V2 32/32] AMD/VanGoghBoard: Check in Chachani board project files and build script
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[edk2-devel] [PATCH V2 31/32] AMD/VanGoghBoard: Check in AMD SmmControlPei module
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial AMD SmmControlPei module in Silicon folder.
This module initializes SMM-related registers, and installs gPeiSmmControlPpi.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../Smm/SmmControlPei/SmmControlPei.c | 307 ++
.../Smm/SmmControlPei/SmmControlPei.inf | 40 +++
2 files changed, 347 insertions(+)
create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.inf
diff --git a/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
new file mode 100644
index 00..4752aede9c
--- /dev/null
+++ b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c
@@ -0,0 +1,307 @@
+/** @file
+ Implements SmmControlPei.c
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+
+/**
+ This routine generates an SMI
+
+ @param[in] PeiServices Describes the list of possible PEI
Services.
+ @param[in] This The pointer to this instance of this
PPI.
+ @param[in, out] ArgumentBufferThe buffer of argument
+ @param[in, out] ArgumentBufferSizeThe size of the argument buffer
+ @param[in] Periodic TRUE to indicate a periodical SMI
+ @param[in] ActivationIntervalInterval of periodic SMI
+
+ @retval EFI_SUCCESSSMI generated.
+ @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported
+**/
+EFI_STATUS
+EFIAPI
+PeiTrigger (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_CONTROL_PPI *This,
+ IN OUT INT8 *ArgumentBuffer OPTIONAL,
+ IN OUT UINTN*ArgumentBufferSize OPTIONAL,
+ IN BOOLEAN Periodic OPTIONAL,
+ IN UINTNActivationInterval OPTIONAL
+ );
+
+/**
+ Clear SMI related chipset status.
+
+ @param[in] PeiServices Describes the list of possible PEI
Services.
+ @param[in] This The pointer to this instance of this PPI.
+ @param[in] Periodic TRUE to indicate a periodical SMI.
+
+ @return Return value from ClearSmi()
+**/
+EFI_STATUS
+EFIAPI
+PeiClear (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_CONTROL_PPI *This,
+ IN BOOLEAN Periodic OPTIONAL
+ );
+
+STATIC PEI_SMM_CONTROL_PPI mSmmControlPpi = {
+ PeiTrigger,
+ PeiClear
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ ,
+
+};
+
+/**
+ Init related registers
+
+ @param [in]None
+
+ @retval EFI_LOAD_ERROR Get ACPI MMIO base error.
+ @retval EFI_SUCCESS The function completed successfully..
+*/
+EFI_STATUS
+SmmControlPeiPreInit (
+ VOID
+ )
+{
+ UINT16 SmmControlData16;
+ UINT16 SmmControlMask16;
+ UINT32 SmmControlData32;
+ UINT8 SmmControlIndex;
+ UINT16 AcpiPmBase;
+
+ //
+ // Get ACPI MMIO base and AcpiPm1EvtBlk address
+ //
+ AcpiPmBase = MmioRead16 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60);
+
+ if (0 == AcpiPmBase) {
+return EFI_LOAD_ERROR;
+ }
+
+ //
+ // Clean up all SMI status and enable bits
+ //
+ // Clear all SmiControl registers
+ SmmControlData32 = 0;
+ for (SmmControlIndex = FCH_SMI_REGA0; SmmControlIndex <= FCH_SMI_REGC4;
SmmControlIndex += 4) {
+MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + SmmControlIndex,
SmmControlData32);
+ }
+
+ // Clear all SmiStatus registers (SmiStatus0-4)
+ SmmControlData32 = 0x;
+ MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG80, SmmControlData32);
+ MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG84, SmmControlData32);
+ MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG88, SmmControlData32);
+ MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG8C, SmmControlData32);
+ MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG90, SmmControlData32);
+
+ //
+ // If SCI is not enabled, clean up all ACPI PM status/enable registers
+ //
+ SmmControlData16 = IoRead16 (AcpiPmBase + R_FCH_ACPI_PM_CONTROL);
+ if (!(SmmControlData16 & BIT0)) {
+// Clear WAKE_EN, RTC_EN, SLPBTN_EN, GBL_EN and TMR_EN
+SmmControlData16 = 0;
+SmmControlMask16 = (UINT16) ~(BIT15 + BIT10 + BIT9 + BIT5 + BIT0);
+IoAndThenOr16 (AcpiPmBase + R_FCH_ACPI_PM1_ENABLE, SmmControlMask16,
SmmControlData16);
+
+// Clear WAKE_STS, RTC_STS, SLPBTN_STS, GBL_STS and TMR_STS
+SmmControlData16 = BIT15 + BIT10 + BIT9 + BIT5 + BIT0;
+IoWrite16
[edk2-devel] [PATCH V2 28/32] AMD/VanGoghBoard: Check in SmmCpuFeaturesLibCommon module.
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial SmmCpuFeaturesLibCommon module. The CPU specific programming for
PiSmmCpuDxeSmm module when STM support is not included.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../SmmCpuFeaturesLibCommon.c | 623 ++
1 file changed, 623 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
diff --git
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
new file mode 100644
index 00..f3615e2d9e
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
@@ -0,0 +1,623 @@
+/** @file
+Implementation shared across all library instances.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "CpuFeaturesLib.h"
+
+//
+// Machine Specific Registers (MSRs)
+//
+#define SMM_FEATURES_LIB_IA32_MTRR_CAP0x0FE
+#define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A
+#define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2
+#define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3
+#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0
+#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
+#defineEFI_MSR_SMRR_MASK 0xF000
+#defineEFI_MSR_SMRR_PHYS_MASK_VALIDBIT11
+#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0
+
+//
+// MSRs required for configuration of SMM Code Access Check
+//
+#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
+#define SMM_CODE_ACCESS_CHK_BIT BIT58
+
+extern UINT8 mSmmSaveStateRegisterLma;
+
+//
+// Set default value to assume SMRR is not supported
+//
+BOOLEAN mSmrrSupported = FALSE;
+
+//
+// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
+//
+BOOLEAN mSmmFeatureControlSupported = FALSE;
+
+//
+// Set default value to assume IA-32 Architectural MSRs are used
+//
+UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
+UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;
+
+//
+// Set default value to assume MTRRs need to be configured on each SMI
+//
+BOOLEAN mNeedConfigureMtrrs = TRUE;
+
+//
+// Array for state of SMRR enable on all CPUs
+//
+BOOLEAN *mSmrrEnabled;
+
+/**
+ Performs library initialization.
+
+ This initialization function contains common functionality shared betwen all
+ library instance constructors.
+
+**/
+VOID
+CpuFeaturesLibInitialization (
+ VOID
+ )
+{
+ UINT32 RegEax;
+ UINT32 RegEdx;
+ UINTN FamilyId;
+ UINTN ModelId;
+
+ //
+ // Retrieve CPU Family and Model
+ //
+ AsmCpuid (CPUID_VERSION_INFO, , NULL, NULL, );
+ FamilyId = (RegEax >> 8) & 0xf;
+ ModelId = (RegEax >> 4) & 0xf;
+ if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
+ModelId = ModelId | ((RegEax >> 12) & 0xf0);
+ }
+
+ //
+ // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
+ //
+ if ((RegEdx & BIT12) != 0) {
+//
+// Check MTRR_CAP MSR bit 11 for SMRR support
+//
+if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {
+ mSmrrSupported = TRUE;
+}
+ }
+
+ //
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+ // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
+ //
+ // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
+ // SMRR Physical Base and SMM Physical Mask MSRs are not available.
+ //
+ if (FamilyId == 0x06) {
+if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) ||
(ModelId == 0x35) || (ModelId == 0x36)) {
+ mSmrrSupported = FALSE;
+}
+ }
+
+ //
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+ // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
+ //
+ // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
+ // Processor Family MSRs
+ //
+ if (FamilyId == 0x06) {
+if ((ModelId == 0x17) || (ModelId == 0x0f)) {
+ mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
+ mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
+}
+ }
+
+ //
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+ // Volume 3C, Section 34.4.2 SMRAM
[edk2-devel] [PATCH V2 29/32] AMD/VanGoghBoard: Check in SmramSaveState module
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial SmramSaveState module.
This module provides services to access SMRAM Save State Map.
Signed-off-by: Ken Yao
Cc: Eric Xing
Cc: Duke Zhai
Cc: Igniculus Fu
Cc: Abner Chang
---
.../PiSmmCpuDxeSmm/SmramSaveState.c | 706 ++
1 file changed, 706 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
diff --git
a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
new file mode 100644
index 00..ca63de9ba6
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -0,0 +1,706 @@
+/** @file
+Provides services to access SMRAM Save State Map
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include "PiSmmCpuDxeSmm.h"
+
+typedef struct {
+ UINT64Signature; // Offset 0x00
+ UINT16Reserved1; // Offset 0x08
+ UINT16Reserved2; // Offset 0x0A
+ UINT16Reserved3; // Offset 0x0C
+ UINT16SmmCs; // Offset 0x0E
+ UINT16SmmDs; // Offset 0x10
+ UINT16SmmSs; // Offset 0x12
+ UINT16SmmOtherSegment;// Offset 0x14
+ UINT16Reserved4; // Offset 0x16
+ UINT64Reserved5; // Offset 0x18
+ UINT64Reserved6; // Offset 0x20
+ UINT64Reserved7; // Offset 0x28
+ UINT64SmmGdtPtr; // Offset 0x30
+ UINT32SmmGdtSize; // Offset 0x38
+ UINT32Reserved8; // Offset 0x3C
+ UINT64Reserved9; // Offset 0x40
+ UINT64Reserved10; // Offset 0x48
+ UINT16Reserved11; // Offset 0x50
+ UINT16Reserved12; // Offset 0x52
+ UINT32Reserved13; // Offset 0x54
+ UINT64Reserved14; // Offset 0x58
+} PROCESSOR_SMM_DESCRIPTOR;
+
+extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
+
+//
+// EFER register LMA bit
+//
+#define LMA BIT10
+
+///
+/// Macro used to simplify the lookup table entries of type
CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
+///
+#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
+
+///
+/// Macro used to simplify the lookup table entries of type
CPU_SMM_SAVE_STATE_REGISTER_RANGE
+///
+#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
+
+///
+/// Structure used to describe a range of registers
+///
+typedef struct {
+ EFI_SMM_SAVE_STATE_REGISTERStart;
+ EFI_SMM_SAVE_STATE_REGISTEREnd;
+ UINTN Length;
+} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
+
+///
+/// Structure used to build a lookup table to retrieve the widths and offsets
+/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
+///
+
+#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1
+#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2
+#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3
+#define SMM_SAVE_STATE_REGISTER_MAX_INDEX4
+
+typedef struct {
+ UINT8 Width32;
+ UINT8 Width64;
+ UINT16 Offset32;
+ UINT16 Offset64Lo;
+ UINT16 Offset64Hi;
+ BOOLEANWriteable;
+} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
+
+///
+/// Structure used to build a lookup table for the IOMisc width information
+///
+typedef struct {
+ UINT8 Width;
+ EFI_SMM_SAVE_STATE_IO_WIDTHIoWidth;
+} CPU_SMM_SAVE_STATE_IO_WIDTH;
+
+///
+/// Variables from SMI Handler
+///
+X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;
+extern volatile UINT8 gcSmiHandlerTemplate[];
+extern CONST UINT16 gcSmiHandlerSize;
+
+//
+// Variables used by SMI Handler
+//
+IA32_DESCRIPTOR gSmiHandlerIdtr;
+
+///
+/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
+///
[edk2-devel] [PATCH V2 26/32] AMD/VanGoghBoard: Check in Smbios platform dxe drivers
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial Smbios platform DXE drivers. Static SMBIOS Table for Chachani
platform.
SmbiosLib provides detailed information of Chachani platform.
Signed-off-by: Eric Xing
Cc: Ken Yao
Cc: Duke Zhai
Cc: Igniculus Fu
Cc: Abner Chang
---
.../PlatformSmbiosDxe/PlatformSmbiosDxe.c | 75
.../PlatformSmbiosDxe/PlatformSmbiosDxe.inf | 53 +++
.../Universal/PlatformSmbiosDxe/SmbiosTable.c | 382 ++
3 files changed, 510 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
create mode 100644
Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
create mode 100644
Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/SmbiosTable.c
diff --git
a/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
new file mode 100644
index 00..c4de6ca133
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.c
@@ -0,0 +1,75 @@
+/** @file
+ Static SMBIOS Table for platform
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2012, Apple Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+extern SMBIOS_TEMPLATE_ENTRY gSmbiosTemplate[];
+
+/**
+ Main entry for this driver.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to SystemTable.
+
+ @retval EFI_SUCESS This function always complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformSmbiosDriverEntryPoint (
+ IN EFI_HANDLEImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUSStatus;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ SMBIOS_STRUCTURE_POINTER Smbios;
+
+ DEBUG ((DEBUG_INFO, " PlatfomrSmbiosDriverEntryPoint \n"));
+
+ // Phase 0 - Patch table to make SMBIOS 2.7 structures smaller to conform
+ // to an early version of the specification.
+
+ // Phase 1 - Initialize SMBIOS tables from template
+ Status = SmbiosLibInitializeFromTemplate (gSmbiosTemplate);
+ ASSERT_EFI_ERROR (Status);
+
+ // Phase 2 - Patch SMBIOS table entries
+ Smbios.Hdr = SmbiosLibGetRecord (EFI_SMBIOS_TYPE_BIOS_INFORMATION, 0,
);
+ if (Smbios.Type0 != NULL) {
+// 64K * (n+1) bytes
+Smbios.Type0->BiosSize = (UINT8)DivU64x32 (FixedPcdGet64
(PcdFlashAreaSize), 64*1024) - 1;
+
+SmbiosLibUpdateUnicodeString (
+ SmbiosHandle,
+ Smbios.Type0->BiosVersion,
+ (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString)
+ );
+
+DEBUG ((
+ DEBUG_INFO,
+ " Smbios.Type0->BiosSize: %dMB, Smbios.Type0->BiosVersion: %S, Build
Time: %a,%a\n",
+ (Smbios.Type0->BiosSize +1) * 64 / 1024,
+ (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
+ __DATE__,
+ __TIME__
+ ));
+ }
+
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
new file mode 100644
index 00..e16a448d7a
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/Universal/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
@@ -0,0 +1,53 @@
+## @file
+# Platform SMBIOS driver that fills in SMBIOS table entries.
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2012, Apple Inc. All rights reserved.
+# Portions copyright (c) 2006 - 2010, Intel Corporation. All rights
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION= 0x00010005
+ BASE_NAME = PlatformSmbiosDxe
+ FILE_GUID = 15EEEB97-709E-91FA-CDA7-44A9C85DDB78
+ MODULE_TYPE= DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT= PlatformSmbiosDriverEntryPoint
+
+
+[Sources]
+ SmbiosTable.c
+ PlatformSmbiosDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ VanGoghCommonPkg/AmdCommonPkg.dec
+ ChachaniBoardPkg/Project.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiLib
+ HobLib
+ SmbiosLib
+
+[Protocols]
+ gEfiSmbiosProtocolGuid
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
+
+[Depex]
+ gEfiSmbiosProtocolGuid
diff --git
[edk2-devel] [PATCH V2 25/32] AMD/VanGoghBoard: Check in PlatformInitPei module
-=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114518): https://edk2.groups.io/g/devel/message/114518 Mute This Topic: https://groups.io/mt/103971418/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH V2 24/32] AMD/VanGoghBoard: Check in FchSpi module
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial FchSpi module. FCH SPI Common Driver implements
the SPI Host Controller Compatibility Interface.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../Universal/FchSpi/FchSpiProtect.c | 67 ++
.../Universal/FchSpi/FchSpiProtect.h | 38 +
.../Universal/FchSpi/FchSpiRuntimeDxe.c | 163
.../Universal/FchSpi/FchSpiRuntimeDxe.h | 49 ++
.../Universal/FchSpi/FchSpiRuntimeDxe.inf | 84 ++
.../VanGoghBoard/Universal/FchSpi/FchSpiSmm.c | 112 +++
.../VanGoghBoard/Universal/FchSpi/FchSpiSmm.h | 32 +
.../Universal/FchSpi/FchSpiSmm.inf| 94 +++
.../VanGoghBoard/Universal/FchSpi/SpiCommon.c | 790 ++
.../VanGoghBoard/Universal/FchSpi/SpiInfo.h | 24 +
10 files changed, 1453 insertions(+)
create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
create mode 100644
Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
create mode 100644
Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.h
create mode 100644
Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.inf
create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiSmm.c
create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiSmm.h
create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiSmm.inf
create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/SpiCommon.c
create mode 100644 Platform/AMD/VanGoghBoard/Universal/FchSpi/SpiInfo.h
diff --git a/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
new file mode 100644
index 00..658d9b063d
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.c
@@ -0,0 +1,67 @@
+/** @file
+ Implements FchSpiProtect.c
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "FchSpiProtect.h"
+
+/**
+
+ Fch Spi Protect Lock
+
+ @param SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_Lock (
+ IN UINTN SpiMmioBase
+ )
+{
+ if (!(MmioRead8 (SpiMmioBase + 2) & 0xC0)) {
+// Check BIT7+BIT6
+return EFI_SUCCESS;
+ } else {
+MmioWrite8 (SpiMmioBase + 9, 0x6);//
PrefixOpCode WRITE_ENABLE
+MmioWrite8 (SpiMmioBase + 2, MmioRead8 (SpiMmioBase + 2) & 0x3F); // Clear
BIT7+BIT6
+if (MmioRead8 (SpiMmioBase + 2) & 0xC0) {
+ return EFI_DEVICE_ERROR;
+}
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Fch Spi Protect UnLock
+
+ @param SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_UnLock (
+ IN UINTN SpiMmioBase
+ )
+{
+ if ((MmioRead8 (SpiMmioBase + 2) & 0xC0) || (6 != MmioRead8 (SpiMmioBase +
9))) {
+return EFI_SUCCESS;
+ } else {
+MmioWrite8 (SpiMmioBase + 9, 0x0);
+MmioWrite8 (SpiMmioBase + 2, MmioRead8 (SpiMmioBase + 2) | 0xC0); // Set
BIT7+BIT6
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
new file mode 100644
index 00..1dd57c6f52
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiProtect.h
@@ -0,0 +1,38 @@
+/** @file
+ Implements FchSpiProtect.h
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef FCH_SPI_PROTECT_H__
+#define FCH_SPI_PROTECT_H__
+
+/**
+
+ Fch Spi Protect Lock
+
+ @param UINTN SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_Lock (
+ IN UINTN SpiMmioBase
+ );
+
+/**
+
+ Fch Spi Protect UnLock
+
+ @param UINTN SpiMmioBase
+
+**/
+EFI_STATUS
+EFIAPI
+FchSpiProtect_UnLock (
+ IN UINTN SpiMmioBase
+ );
+
+#endif
diff --git a/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
new file mode 100644
index 00..7bb402402c
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/FchSpi/FchSpiRuntimeDxe.c
@@ -0,0 +1,163 @@
+/** @file
+PCH SPI Runtime Driver implements the SPI Host Controller Compatibility
Interface.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2015 Intel Corporation.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef _MSC_VER
+ #pragma optimize( "", off )
+#endif
+
+#ifdef __GNUC__
+ #ifndef __clang__
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+ #else
+
[edk2-devel] [PATCH V2 23/32] AMD/VanGoghBoard: Check in AcpiPlatform
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial Acpi platform dxe drivers. Use firmware volume protocol
to update global NVS area for ASL and SMM init code.
Signed-off-by: Eric Xing
Cc: Ken Yao
Cc: Duke Zhai
Cc: Igniculus Fu
Cc: Abner Chang
---
.../Universal/AcpiPlatformDxe/AcpiPlatform.c | 336 ++
.../AcpiPlatformDxe/AcpiPlatform.uni | 15 +
.../AcpiPlatformDxe/AcpiPlatformDxe.inf | 59 +++
.../AcpiPlatformDxe/AcpiPlatformExtra.uni | 13 +
.../AcpiPlatformDxe/AcpiPlatformHooks.c | 152
.../AcpiPlatformDxe/AcpiPlatformHooks.h | 48 +++
6 files changed, 623 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
create mode 100644
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.uni
create mode 100644
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformDxe.inf
create mode 100644
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformExtra.uni
create mode 100644
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformHooks.c
create mode 100644
Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatformHooks.h
diff --git a/Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
b/Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 00..73a022594e
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/Universal/AcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,336 @@
+/** @file
+ Sample ACPI Platform Driver
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "AcpiPlatformHooks.h"
+#include
+
+EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param Instance Return pointer to the first instance of the protocol
+
+ @return EFI_SUCCESS The function completed successfully.
+ @return EFI_NOT_FOUND The protocol could not be located.
+ @return EFI_OUT_OF_RESOURCES There are not enough resources to find the
protocol.
+
+**/
+EFI_STATUS
+LocateFvInstanceWithTables (
+ OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPEFileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;
+
+ FvStatus = 0;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ ,
+ NULL,
+ ,
+
+ );
+ if (EFI_ERROR (Status)) {
+//
+// Defined errors at this time are not found and out of resources.
+//
+return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+//
+// Get the protocol on this handle
+// This should not fail because of LocateHandleBuffer
+//
+Status = gBS->HandleProtocol (
+HandleBuffer[Index],
+,
+(VOID **)
+);
+ASSERT_EFI_ERROR (Status);
+
+//
+// See if it has the ACPI storage file
+//
+Status = FvInstance->ReadFile (
+ FvInstance,
+ (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile),
+ NULL,
+ ,
+ ,
+ ,
+
+ );
+
+//
+// If we found it, then we are done
+//
+if (Status == EFI_SUCCESS) {
+ *Instance = FvInstance;
+ break;
+}
+ }
+
+ //
+ // Our exit status is determined by the success of the previous operations
+ // If the protocol was found, Instance already points to it.
+ //
+
+ //
+ // Free any allocated buffers
+ //
+ gBS->FreePool (HandleBuffer);
+
+ return Status;
+}
+
+/**
+ This function calculates and updates an UINT8 checksum.
+
+ @param Buffer Pointer to buffer to checksum
+ @param SizeNumber of bytes to checksum
+
+**/
+VOID
[edk2-devel] [PATCH V2 21/32] AMD/VanGoghBoard: Check in SignedCapsule
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial SignedCapsule module for Signed Capsule.
Produce FMP instance to update system firmware.
Signed-off-by: Ken Yao
Cc: Eric Xing
Cc: Duke Zhai
Cc: Igniculus Fu
Cc: Abner Chang
---
.../BaseTools/Source/Python/GenFds/Capsule.py | 253 +++
.../SystemFirmwareUpdate/ParseConfigProfile.c | 231 +++
.../SystemFirmwareCommonDxe.c | 371 +
.../SystemFirmwareUpdate/SystemFirmwareDxe.h | 421 +
.../SystemFirmwareUpdateDxe.c | 1426 +
.../SystemFirmwareUpdateDxe.inf | 91 ++
.../SystemFirmwareUpdateDxe.uni | 15 +
.../SystemFirmwareUpdateDxeExtra.uni | 15 +
8 files changed, 2823 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/ParseConfigProfile.c
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareCommonDxe.c
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareDxe.h
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.c
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.uni
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxeExtra.uni
diff --git
a/Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
b/Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
new file mode 100644
index 00..0ec0b3ca43
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/Override/edk2/BaseTools/Source/Python/GenFds/Capsule.py
@@ -0,0 +1,253 @@
+## @file
+# generate capsule
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc.
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+##
+# Import Modules
+#
+from __future__ import absolute_import
+from .GenFdsGlobalVariable import GenFdsGlobalVariable, FindExtendTool
+from CommonDataClass.FdfClass import CapsuleClassObject
+import Common.LongFilePathOs as os
+from io import BytesIO
+from Common.Misc import SaveFileOnChange, PackGUID
+import uuid
+from struct import pack
+from Common import EdkLogger
+from Common.BuildToolError import GENFDS_ERROR
+from Common.DataType import TAB_LINE_BREAK
+
+WIN_CERT_REVISION = 0x0200
+WIN_CERT_TYPE_EFI_GUID = 0x0EF1
+EFI_CERT_TYPE_PKCS7_GUID = uuid.UUID('{4aafd29d-68df-49ee-8aa9-347d375665a7}')
+EFI_CERT_TYPE_RSA2048_SHA256_GUID =
uuid.UUID('{a7717414-c616-4977-9420-844712a735bf}')
+
+## create inf file describes what goes into capsule and call GenFv to generate
capsule
+#
+#
+class Capsule (CapsuleClassObject):
+## The constructor
+#
+# @param selfThe object pointer
+#
+def __init__(self):
+CapsuleClassObject.__init__(self)
+# For GenFv
+self.BlockSize = None
+# For GenFv
+self.BlockNum = None
+self.CapsuleName = None
+
+## Generate FMP capsule
+#
+# @retval string Generated Capsule file path
+#
+def GenFmpCapsule(self):
+#
+# Generate capsule header
+# typedef struct {
+# EFI_GUID CapsuleGuid;
+# UINT32HeaderSize;
+# UINT32Flags;
+# UINT32CapsuleImageSize;
+# } EFI_CAPSULE_HEADER;
+#
+Header = BytesIO()
+#
+# Use FMP capsule GUID: 6DCBD5ED-E82D-4C44-BDA1-7194199AD92A
+#
+
Header.write(PackGUID('6DCBD5ED-E82D-4C44-BDA1-7194199AD92A'.split('-')))
+HdrSize = 0
+if 'CAPSULE_HEADER_SIZE' in self.TokensDict:
+Header.write(pack('=I',
int(self.TokensDict['CAPSULE_HEADER_SIZE'], 16)))
+HdrSize = int(self.TokensDict['CAPSULE_HEADER_SIZE'], 16)
+else:
+Header.write(pack('=I', 0x20))
+HdrSize = 0x20
+Flags = 0
+if 'CAPSULE_FLAGS' in self.TokensDict:
+for flag in self.TokensDict['CAPSULE_FLAGS'].split(','):
+flag = flag.strip()
+if flag == 'PopulateSystemTable':
+Flags |= 0x0001 | 0x0002
+elif
[edk2-devel] [PATCH V2 22/32] AMD/VanGoghBoard: Check in Vtf0
From: Duke Zhai BZ #:4640 In V2: Improve coding style. 1.Remove the leading underscore and use double underscore at trailing in C header files. 2.Remove old tianocore licenses and redundant license description. 3.Improve coding style. For example: remove space between @param. In V1: Initial Vtf0 module. This module includes all assembly code files of reset vector. Signed-off-by: Eric Xing Cc: Ken Yao Cc: Duke Zhai Cc: Igniculus Fu Cc: Abner Chang --- .../ResetVector/Vtf0/CommonMacros.inc | 27 +++ .../ResetVector/Vtf0/DebugDisabled.asm| 21 ++ .../ResetVector/Vtf0/Ia16/Init16.asm | 51 + .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 138 + .../ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm | 108 ++ .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 40 .../ResetVector/Vtf0/Ia32/PageTables64.asm| 25 +++ .../Vtf0/Ia32/SearchForBfvBase.asm| 84 .../Vtf0/Ia32/SearchForSecEntry.asm | 195 ++ .../edk2/UefiCpuPkg/ResetVector/Vtf0/Main.asm | 127 .../ResetVector/Vtf0/Port80Debug.asm | 23 +++ .../UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc | 20 ++ .../ResetVector/Vtf0/ResetVector.uni | Bin 0 -> 780 bytes .../ResetVector/Vtf0/ResetVectorExtra.uni | Bin 0 -> 682 bytes .../ResetVector/Vtf0/SerialDebug.asm | 127 .../edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf | 37 .../UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb| 67 ++ .../ResetVector/Vtf0/X64/PageTables.asm | 73 +++ 18 files changed, 1163 insertions(+) create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia16/Init16.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForBfvBase.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForSecEntry.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Main.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Port80Debug.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/ResetVector.uni create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/ResetVectorExtra.uni create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/SerialDebug.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc new file mode 100644 index 00..5da472faaa --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc @@ -0,0 +1,27 @@ +;-- +; @file +; Common macros used in the ResetVector VTF module. +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +; Copyright (c) 2008, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-- + +%define ADDR16_OF(x) (0x1 - fourGigabytes + x) +%define ADDR_OF(x) (0x1 - fourGigabytes + x) +%define ADDR_OF_MEM(x) (VIRTUAL4G - fourGigabytes + x) +%define SMM_RESUME_SIGNATURE 0x55AABB66 +%macro OneTimeCall 1 +jmp %1 +%1 %+ OneTimerCallReturn: +%endmacro + +%macro OneTimeCallRet 1 +jmp %1 %+ OneTimerCallReturn +%endmacro + +StartOfResetVectorCode: + +%define ADDR_OF_START_OF_RESET_CODE ADDR_OF(StartOfResetVectorCode) + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm new file mode
[edk2-devel] [PATCH V2 19/32] AMD/VanGoghBoard: Check in PcatRealTimeClockRuntimeDxe module
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
This driver provides GetTime, SetTime, GetWakeupTime, SetWakeupTime services
to Runtime Service Table.
It will install a tagging protocol with gEfiRealTimeClockArchProtocolGuid.
Signed-off-by: Ken Yao
Cc: Eric Xing
Cc: Duke Zhai
Cc: Igniculus Fu
Cc: Abner Chang
---
.../PcatRealTimeClockRuntimeDxe/PcRtc.c | 1341 +
.../PcatRealTimeClockRuntimeDxe/PcRtc.h | 374 +
.../PcatRealTimeClockRuntimeDxe/PcRtc.uni | 17 +
.../PcatRealTimeClockRuntimeDxe/PcRtcEntry.c | 171 +++
.../PcRtcExtra.uni| 15 +
.../PcatRealTimeClockRuntimeDxe.inf | 77 +
6 files changed, 1995 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.uni
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcExtra.uni
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
diff --git
a/Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
b/Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
new file mode 100644
index 00..4e42d9d2ad
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/Override/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
@@ -0,0 +1,1341 @@
+/** @file
+ RTC Architectural Protocol GUID as defined in DxeCis 0.96.
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PcRtc.h"
+
+//
+// Days of month.
+//
+UINTN mDayOfMonth[] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+//
+// The name of NV variable to store the timezone and daylight saving
information.
+//
+CHAR16 mTimeZoneVariableName[] = L"RTC";
+
+/**
+ Compare the Hour, Minute and Second of the From time and the To time.
+
+ Only compare H/M/S in EFI_TIME and ignore other fields here.
+
+ @param From the first time
+ @param To the second time
+
+ @return >0 The H/M/S of the From time is later than those of To time
+ @return ==0 The H/M/S of the From time is same as those of To time
+ @return <0 The H/M/S of the From time is earlier than those of To time
+**/
+INTN
+CompareHMS (
+ IN EFI_TIME *From,
+ IN EFI_TIME *To
+ );
+
+/**
+ To check if second date is later than first date within 24 hours.
+
+ @param From the first date
+ @param To the second date
+
+ @retval TRUE From is previous to To within 24 hours.
+ @retval FALSE From is later, or it is previous to To more than 24 hours.
+**/
+BOOLEAN
+IsWithinOneDay (
+ IN EFI_TIME *From,
+ IN EFI_TIME *To
+ );
+
+/**
+ Read RTC content through its registers.
+
+ @param Address Address offset of RTC. It is recommended to use macros such
as
+ RTC_ADDRESS_SECONDS.
+
+ @return The data of UINT8 type read from RTC.
+**/
+UINT8
+RtcRead (
+ IN UINT8 Address
+ )
+{
+ IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8)(Address | (UINT8)(IoRead8
(PCAT_RTC_ADDRESS_REGISTER) & 0x80)));
+ return IoRead8 (PCAT_RTC_DATA_REGISTER);
+}
+
+/**
+ Write RTC through its registers.
+
+ @param Address Address offset of RTC. It is recommended to use macros such
as
+ RTC_ADDRESS_SECONDS.
+ @param Data The content you want to write into RTC.
+
+**/
+VOID
+RtcWrite (
+ IN UINT8 Address,
+ IN UINT8 Data
+ )
+{
+ IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8)(Address | (UINT8)(IoRead8
(PCAT_RTC_ADDRESS_REGISTER) & 0x80)));
+ IoWrite8 (PCAT_RTC_DATA_REGISTER, Data);
+}
+
+/**
+ Initialize RTC.
+
+ @param GlobalFor global use inside this module.
+
+ @retval EFI_DEVICE_ERROR Initialization failed due to device error.
+ @retval EFI_SUCCESS Initialization successful.
+
+**/
+EFI_STATUS
+PcRtcInit (
+ IN PC_RTC_MODULE_GLOBALS *Global
+ )
+{
+ EFI_STATUS Status;
+ RTC_REGISTER_B RegisterB;
+ EFI_TIMETime;
+ UINTN DataSize;
+ UINT32 TimerVar;
+ BOOLEAN Enabled;
+ BOOLEAN Pending;
+
+ //
+ // Acquire RTC Lock to make access to RTC atomic
+ //
+ if (!EfiAtRuntime ()) {
+EfiAcquireLock (>RtcLock);
[edk2-devel] [PATCH V2 17/32] AMD/VanGoghBoard: Check in Smm access module
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial AMD Smm access module.
Contains description files for ACPI SMM Platform handler module.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../Smm/AcpiSmm/AcpiSmmPlatform.c | 183
.../Smm/AcpiSmm/AcpiSmmPlatform.h | 50 ++
.../Smm/AcpiSmm/AcpiSmmPlatform.inf | 57 +++
.../Smm/SmmAccessPei/SmmAccessPei.c | 436 ++
.../Smm/SmmAccessPei/SmmAccessPei.inf | 43 ++
5 files changed, 769 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.inf
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/SmmAccessPei.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/SmmAccessPei.inf
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
new file mode 100644
index 00..20a0ed6cb7
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatform.c
@@ -0,0 +1,183 @@
+/** @file
+ACPISMM Driver implementation file.
+
+This is QNC Smm platform driver
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2019 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+
+/**
+ Allocate EfiACPIMemoryNVS below 4G memory address.
+
+ This function allocates EfiACPIMemoryNVS below 4G memory address.
+
+ @param[in] Size Size of memory to allocate.
+
+ @return Allocated address for output.
+
+**/
+VOID *
+AllocateAcpiNvsMemoryBelow4G (
+ IN UINTN Size
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUSStatus;
+ VOID *Buffer;
+
+ Pages = EFI_SIZE_TO_PAGES (Size);
+ Address = 0x;
+
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+
+ );
+ if (EFI_ERROR (Status)) {
+return NULL;
+ }
+
+ Buffer = (VOID *)(UINTN)Address;
+ ZeroMem (Buffer, Size);
+
+ return Buffer;
+}
+
+/**
+ Reserved S3 memory for InstallS3Memory
+
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to complete
function.
+ @retval EFI_SUCCESS Function has completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+ReservedS3Memory (
+ UINTN SystemMemoryLength
+
+ )
+
+{
+ VOID*GuidHob;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;
+ VOID*AcpiReservedBase;
+
+ UINTN TsegIndex;
+ UINTN TsegSize;
+ UINTN TsegBase;
+ RESERVED_ACPI_S3_RANGE *AcpiS3Range;
+
+ DEBUG ((DEBUG_INFO, "ReservedS3Memory, SystemMemoryLength: 0x%08X\n",
SystemMemoryLength));
+ //
+ // Get Hob list for SMRAM desc
+ //
+ GuidHob = GetFirstGuidHob ();
+ ASSERT (GuidHob != NULL);
+ DEBUG ((DEBUG_INFO, "gEfiSmmPeiSmramMemoryReserveGuid: 0x%X \n",
(UINTN)GuidHob));
+ DescriptorBlock = GET_GUID_HOB_DATA (GuidHob);
+ ASSERT (DescriptorBlock != NULL);
+
+ //
+ // Use the hob to get SMRAM capabilities
+ //
+ TsegIndex = DescriptorBlock->NumberOfSmmReservedRegions - 1;
+ DEBUG ((DEBUG_INFO, "DescriptorBlock->NumberOfSmmReservedRegions: 0x%X\n",
DescriptorBlock->NumberOfSmmReservedRegions));
+ DEBUG ((DEBUG_INFO, "TsegIndex: 0x%X\n", TsegIndex));
+ ASSERT (TsegIndex <= (MAX_SMRAM_RANGES - 1));
+ TsegBase = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalStart;
+ TsegSize = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalSize;
+
+ DEBUG ((DEBUG_INFO, "SMM Base: %08X\n", TsegBase));
+ DEBUG ((DEBUG_INFO, "SMM Size: %08X\n", TsegSize));
+
+ //
+ // Now find the location of the data structure that is used to store the
address
+ // of the S3 reserved memory.
+ //
+ AcpiS3Range = (RESERVED_ACPI_S3_RANGE *)(UINTN)(TsegBase +
RESERVED_ACPI_S3_RANGE_OFFSET);
+ DEBUG ((DEBUG_INFO, "AcpiS3Range: %08X\n", (UINTN)AcpiS3Range));
+ //
+ // Allocate reserved ACPI memory for S3 resume. Pointer to this region is
+ // stored in SMRAM in the first page of TSEG.
+ //
+ AcpiReservedBase = AllocateAcpiNvsMemoryBelow4G (PcdGet32
(PcdS3AcpiReservedMemorySize));
+ DEBUG ((DEBUG_INFO, "AcpiReservedBase: %08X\n", (UINTN)AcpiReservedBase));
+ ASSERT (AcpiReservedBase != NULL);
+ if
[edk2-devel] [PATCH V2 15/32] AMD/VanGoghBoard: Check in SpiFlashDeviceLib
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial AMD SpiFlashDeviceLib for Chachani board flash IC.
Chachani board use the W25Q256JW as flash IC.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../SpiFlashDeviceLib/SpiFlashDeviceLib.c | 42 +++
.../SpiFlashDeviceLib/SpiFlashDeviceLib.inf | 29 +
2 files changed, 71 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
new file mode 100644
index 00..49636f6a89
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.c
@@ -0,0 +1,42 @@
+/** @file
+ Implements SpiFlashDeviceLib.c
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+
+SPI_INIT_TABLE mSpiInitTable[] = {
+ { // W25Q256JW/W74M25JW
+SF_VENDOR_ID_WINBOND,
+SF_DEVICE_ID0_W25Q256JW,
+SF_DEVICE_ID1_W25Q256JW,
+{
+ SPI_COMMAND_WRITE_ENABLE,
+ SPI_COMMAND_WRITE_S_EN
+},
+{
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_JEDEC_ID,
EnumSpiOperationJedecId},
+ { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_WRITE_S,
EnumSpiOperationWriteStatus},
+ { EnumSpiOpcodeWrite,SPI_COMMAND_WRITE,
EnumSpiOperationProgramData_1_Byte },
+ { EnumSpiOpcodeRead, SPI_COMMAND_READ,
EnumSpiOperationReadData },
+ { EnumSpiOpcodeWrite,SPI_COMMAND_ERASE,
EnumSpiOperationErase_4K_Byte },
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_READ_S,
EnumSpiOperationReadStatus },
+ { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_CHIP_ERASE,
EnumSpiOperationFullChipErase },
+ { EnumSpiOpcodeRead, SPI_COMMAND_READ_SFDP,
EnumSpiOperationReadData },
+ { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_RPMC_OP1,
EnumSpiOperationOther },
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_RPMC_OP2,
EnumSpiOperationReadData },
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Enter_4Byte_Addr,
EnumSpiOperationOther },
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Exit_4Byte_Addr,
EnumSpiOperationOther }
+},
+0,
+0x200 // BIOS image size in flash
+ }
+};
+
+//
+// The total number of support flash part
+//
+UINT8 mNumSpiFlashMax = sizeof (mSpiInitTable) / sizeof (mSpiInitTable[0]);
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
new file mode 100644
index 00..951cf6c480
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SpiFlashDeviceLib/SpiFlashDeviceLib.inf
@@ -0,0 +1,29 @@
+## @file
+# SpiFlashDeviceLib
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 0x00010005
+ BASE_NAME = SpiFlashDeviceLib
+ FILE_GUID = D5A903A8-4D19-4E4C-AAF4-07C5D10D5939
+ MODULE_TYPE= BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SpiFlashDeviceLib
+
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ SpiFlashDeviceLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ VanGoghCommonPkg/AmdCommonPkg.dec
+
+[LibraryClasses]
+ SpiFlashDeviceLib
--
2.31.1
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[edk2-devel] [PATCH V2 16/32] AMD/VanGoghBoard: Check in BaseTscTimerLib
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Provides basic TSC timer calibration based on the ACPI timer hardware.
The performance counter features are provided by the processors time stamp
counter.
Signed-off-by: Ken Yao
Cc: Eric Xing
Cc: Duke Zhai
Cc: Igniculus Fu
Cc: Abner Chang
---
.../Library/TscTimerLib/BaseTscTimerLib.c | 23 ++
.../Library/TscTimerLib/BaseTscTimerLib.inf | 43 +++
.../Library/TscTimerLib/DxeTscTimerLib.c | 80 ++
.../Library/TscTimerLib/DxeTscTimerLib.inf| 62 +
.../Library/TscTimerLib/PeiTscTimerLib.c | 53
.../Library/TscTimerLib/PeiTscTimerLib.inf| 56
.../Library/TscTimerLib/TscTimerLibInternal.h | 53
.../Library/TscTimerLib/TscTimerLibShare.c| 255 ++
8 files changed, 625 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.inf
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/PeiTscTimerLib.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/PeiTscTimerLib.inf
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/TscTimerLibInternal.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/TscTimerLibShare.c
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
new file mode 100644
index 00..7dfef490e9
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.c
@@ -0,0 +1,23 @@
+/** @file
+ ACPI Timer implements one instance of Timer Library.
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "TscTimerLibInternal.h"
+
+/** Get TSC frequency.
+
+ @return The number of TSC counts per second.
+
+**/
+UINT64
+InternalGetTscFrequency (
+ VOID
+ )
+{
+ return InternalCalculateTscFrequency ();
+}
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
new file mode 100644
index 00..d6c4e2e1d6
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTscTimerLib.inf
@@ -0,0 +1,43 @@
+## @file
+# BaseTscTimerLib
+# Provides basic timer support using the ACPI timer hardware. The performance
+# counter features are provided by the processors time stamp counter.
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 0x00010005
+ BASE_NAME = BaseTscTimerLib
+ FILE_GUID = D29338B9-50FE-4e4f-B7D4-A150A2C1F4FB
+ MODULE_TYPE= BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib
+
+
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources.common]
+ TscTimerLibShare.c
+ BaseTscTimerLib.c
+ TscTimerLibInternal.h
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AgesaPublic/AgesaPublic.dec
+
+
+[LibraryClasses]
+ PcdLib
+ PciLib
+ IoLib
+ BaseLib
+
+[Pcd.common]
+ gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
new file mode 100644
index 00..5a374665c3
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTscTimerLib.c
@@ -0,0 +1,80 @@
+/** @file
+ ACPI Timer implements one instance of Timer Library.
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) Microsoft Corporation.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include "TscTimerLibInternal.h"
+
+UINT64 mTscFrequency;
+
+/** The constructor function determines the actual TSC frequency.
+
+ First, Get TSC frequency from system
[edk2-devel] [PATCH V2 14/32] AMD/VanGoghBoard: Check in SmbiosLib
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Provides library functions for common SMBIOS operations. Only available to DXE
and UEFI module types.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../Include/Library/SmbiosLib.h | 171 ++
.../Library/SmbiosLib/SmbiosLib.c | 322 ++
.../Library/SmbiosLib/SmbiosLib.inf | 41 +++
3 files changed, 534 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SmbiosLib/SmbiosLib.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/SmbiosLib/SmbiosLib.inf
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
new file mode 100644
index 00..314f0448fd
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SmbiosLib.h
@@ -0,0 +1,171 @@
+/** @file
+ Implements AMD SmbiosLib.h
+ Provides library functions for common SMBIOS operations. Only available to
DXE
+ and UEFI module types.
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2012, Apple Inc. All rights reserved. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SMBIOS_LIB_H___
+#define SMBIOS_LIB_H___
+
+#include
+#include
+
+///
+/// Cache copy of the SMBIOS Protocol pointer
+///
+extern EFI_SMBIOS_PROTOCOL *gSmbios;
+
+///
+/// Template for SMBIOS table initialization.
+/// The SMBIOS_TABLE_STRING types in the formated area must match the
+/// StringArray sequene.
+///
+typedef struct {
+ //
+ // formatted area of a given SMBIOS record
+ //
+ SMBIOS_STRUCTURE*Entry;
+ //
+ // NULL terminated array of ASCII strings to be added to the SMBIOS record.
+ //
+ CHAR8 **StringArray;
+} SMBIOS_TEMPLATE_ENTRY;
+
+/**
+ Create an initial SMBIOS Table from an array of SMBIOS_TEMPLATE_ENTRY
+ entries. SMBIOS_TEMPLATE_ENTRY.NULL indicates the end of the table.
+
+ @param[in] Template Array of SMBIOS_TEMPLATE_ENTRY entries.
+
+ @retval EFI_SUCCESS New SMBIOS tables were created.
+ @retval EFI_OUT_OF_RESOURCES New SMBIOS tables were not created.
+**/
+EFI_STATUS
+EFIAPI
+SmbiosLibInitializeFromTemplate (
+ IN SMBIOS_TEMPLATE_ENTRY *Template
+ );
+
+/**
+ Create SMBIOS record.
+
+ Converts a fixed SMBIOS structure and an array of pointers to strings into
+ an SMBIOS record where the strings are cat'ed on the end of the fixed record
+ and terminated via a double NULL and add to SMBIOS table.
+
+ @param[in] SmbiosEntry Fixed SMBIOS structure
+ @param[in] StringArray Array of strings to convert to an SMBIOS string
pack.
+NULL is OK.
+
+ @retval EFI_SUCCESS New SmbiosEntry was added to SMBIOS table.
+ @retval EFI_OUT_OF_RESOURCES SmbiosEntry was not added.
+**/
+EFI_STATUS
+EFIAPI
+SmbiosLibCreateEntry (
+ IN SMBIOS_STRUCTURE *SmbiosEntry,
+ IN CHAR8 **StringArray
+ );
+
+/**
+ Update the string associated with an existing SMBIOS record.
+
+ This function allows the update of specific SMBIOS strings. The number of
valid strings for any
+ SMBIOS record is defined by how many strings were present when Add() was
called.
+
+ @param[in]SmbiosHandleSMBIOS Handle of structure that will have its
string updated.
+ @param[in]StringNumberThe non-zero string number of the string to
update.
+ @param[in]String Update the StringNumber string with String.
+
+ @retval EFI_SUCCESS SmbiosHandle had its StringNumber String
updated.
+ @retval EFI_INVALID_PARAMETER SmbiosHandle does not exist. Or String is
invalid.
+ @retval EFI_UNSUPPORTED String was not added because it is longer than
the SMBIOS Table supports.
+ @retval EFI_NOT_FOUND The StringNumber.is not valid for this SMBIOS
record.
+**/
+EFI_STATUS
+EFIAPI
+SmbiosLibUpdateString (
+ IN EFI_SMBIOS_HANDLESmbiosHandle,
+ IN SMBIOS_TABLE_STRING StringNumber,
+ IN CHAR8*String
+ );
+
+/**
+ Update the string associated with an existing SMBIOS record.
+
+ This function allows the update of specific SMBIOS strings. The number of
valid strings for any
+ SMBIOS record is defined by how many strings were present when Add() was
called.
+
+ @param[in]SmbiosHandleSMBIOS Handle of structure that will have its
string updated.
+ @param[in]StringNumberThe non-zero string number of the string to
update.
+ @param[in]String Update the StringNumber string
[edk2-devel] [PATCH V2 13/32] AMD/VanGoghBoard: Check in PlatformFlashAccessLib
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial AMD PlatformFlashAccessLib, It provides flash access protocol for
other modules.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../Include/Library/SpiFlashDeviceLib.h | 59 ++
.../VanGoghCommonPkg/Include/Protocol/Spi.h | 346
.../Include/Protocol/SpiCommon.h | 247
.../Include/Protocol/SpiFlashUpdate.h | 152 +
.../PlatformFlashAccessLib.c | 528 ++
.../PlatformFlashAccessLib.inf| 64 +++
6 files changed, 1396 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/SpiCommon.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/SpiFlashUpdate.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.inf
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
new file mode 100644
index 00..a6ec077f05
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Library/SpiFlashDeviceLib.h
@@ -0,0 +1,59 @@
+/** @file
+ Implements SpiFlashDevice.h
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_FLASH_DEVICE_LIB_H__
+#define SPI_FLASH_DEVICE_LIB_H__
+
+#include
+
+//
+// Provides mSpiInitTable and the total number of flash part in mSpiInitTable
for other modules.
+//
+extern SPI_INIT_TABLE mSpiInitTable[];
+extern UINT8 mNumSpiFlashMax;
+
+//
+// Flash Device commands
+//
+// If a supported device uses a command different from the list below, a
device specific command
+// will be defined just below it's JEDEC id section.
+//
+#define SPI_COMMAND_WRITE 0x02
+#define SPI_COMMAND_WRITE_AAI 0xAD
+#define SPI_COMMAND_READ 0x03
+#define SPI_COMMAND_ERASE 0x20
+#define SPI_COMMAND_WRITE_DISABLE 0x04
+#define SPI_COMMAND_READ_S0x05
+#define SPI_COMMAND_WRITE_ENABLE 0x06
+#define SPI_COMMAND_READ_ID 0xAB
+#define SPI_COMMAND_JEDEC_ID 0x9F
+#define SPI_COMMAND_WRITE_S_EN0x50
+#define SPI_COMMAND_WRITE_S 0x01
+#define SPI_COMMAND_CHIP_ERASE0xC7
+#define SPI_COMMAND_BLOCK_ERASE 0xD8
+#define SPI_COMMAND_READ_SFDP 0x5A
+#define SPI_COMMAND_RPMC_OP1 0x9B
+#define SPI_COMMAND_RPMC_OP2 0x96
+#define SPI_COMMAND_Enter_4Byte_Addr 0xB7
+#define SPI_COMMAND_Exit_4Byte_Addr 0xE9
+
+//
+// Winbond 256Mbit parts
+//
+#define SF_VENDOR_ID_WINBOND 0xEF
+#define SF_DEVICE_ID1_W25Q256JW 0x19 // Capacity 256Mbit
+#define SF_DEVICE_ID0_W25Q256JW 0x60
+
+//
+// index for prefix opcodes
+//
+#define SPI_WREN_INDEX 0 // Prefix Opcode 0:
SPI_COMMAND_WRITE_ENABLE
+#define SPI_EWSR_INDEX 1 // Prefix Opcode 1:
SPI_COMMAND_WRITE_S_EN
+#define BIOS_CTRL 0xDC
+
+#endif
diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
new file mode 100644
index 00..c7c3591479
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Include/Protocol/Spi.h
@@ -0,0 +1,346 @@
+/** @file
+ Implements AMD Spi
+ This file defines the EFI SPI Protocol which implements the
+ Intel(R) ICH SPI Host Controller Compatibility Interface.
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_H__
+#define SPI_H__
+
+#include
+
+//
+// Define the SPI protocol GUID
+//
+// EDK and EDKII have different GUID formats
+//
+#if !defined (EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x0002)
+#define EFI_SPI_PROTOCOL_GUID \
+ { \
+0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13
\
+ }
+#define EFI_SMM_SPI_PROTOCOL_GUID \
+ { \
+0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85
\
+ }
+#else
+#define EFI_SPI_PROTOCOL_GUID \
+ { \
+0x1156efc6, 0xea32, 0x4396, \
+{ \
+ 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3,
[edk2-devel] [PATCH V2 12/32] AMD/VanGoghBoard: Check in AMD BaseSerialPortLib
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial FCH UART port for Serial log output.
Chachani board uses this UART for outputting debug log.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../BaseSerialPortLib16550AmdFchUart.c| 463 ++
.../BaseSerialPortLib16550AmdFchUart.inf | 40 ++
2 files changed, 503 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.inf
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
new file mode 100644
index 00..665f47f703
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/BaseSerialPortLib16550AmdFchUart/BaseSerialPortLib16550AmdFchUart.c
@@ -0,0 +1,463 @@
+/** @file
+ 16550 UART Serial Port library functions
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2014 Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF 0
+#define R_UART_TXBUF 0
+#define R_UART_BAUD_LOW 0
+#define R_UART_BAUD_HIGH 1
+#define R_UART_FCR 2
+#define B_UART_FCR_FIFOE BIT0
+#define B_UART_FCR_FIFO64 BIT5
+#define R_UART_LCR 3
+#define B_UART_LCR_DLABBIT7
+#define R_UART_MCR 4
+#define B_UART_MCR_RTS BIT1
+#define R_UART_LSR 5
+#define B_UART_LSR_RXRDY BIT0
+#define B_UART_LSR_TXRDY BIT5
+#define B_UART_LSR_TEMTBIT6
+#define R_UART_MSR 6
+#define B_UART_MSR_CTS BIT4
+#define B_UART_MSR_DSR BIT5
+
+/**
+ Read an 8-bit 16550 register. The parameter Offset is added to the base
address of the
+ 16550 registers that is specified by PcdSerialRegisterBase.
+ @param Offset The offset of the 16550 register to read.
+ @return The value read from the 16550 register.
+**/
+UINT8
+SerialPortReadRegister (
+ UINTN Offset
+ )
+{
+ return MmioRead8 ((UINTN)PcdGet64 (PcdSerialRegisterBase) + Offset * 4);
+}
+
+/**
+ Write an 8-bit 16550 register. The parameter Offset is added to the base
address of the
+ 16550 registers that is specified by PcdSerialRegisterBase.
+ @param Offset The offset of the 16550 register to write.
+ @param Value The value to write to the 16550 register specified by Offset.
+ @return The value written to the 16550 register.
+**/
+UINT8
+SerialPortWriteRegister (
+ UINTN Offset,
+ UINT8 Value
+ )
+{
+ return MmioWrite8 ((UINTN)PcdGet64 (PcdSerialRegisterBase) + Offset * 4,
Value);
+}
+
+/**
+ Return whether the hardware flow control signal allows writing.
+
+ @retval TRUE The serial port is writable.
+ @retval FALSE The serial port is not writable.
+**/
+BOOLEAN
+SerialPortWritable (
+ VOID
+ )
+{
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+if (PcdGetBool (PcdSerialDetectCable)) {
+ //
+ // Wait for both DSR and CTS to be set
+ // DSR is set if a cable is connected.
+ // CTS is set if it is ok to transmit data
+ //
+ // DSR CTS Description Action
+ // === ===
+ //00 No cable connected. Wait
+ //01 No cable connected. Wait
+ //10 Cable connected, but not clear to send. Wait
+ //11 Cable connected, and clear to send. Transmit
+ //
+ return (BOOLEAN)((SerialPortReadRegister (R_UART_MSR) & (B_UART_MSR_DSR
| B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
+} else {
+ //
+ // Wait for both DSR and CTS to be set OR for DSR to be clear.
+ // DSR is set if a cable is connected.
+ // CTS is set if it is ok to transmit data
+ //
+ // DSR CTS Description Action
+ // === ===
+ //00 No cable connected. Transmit
+ //01 No cable connected. Transmit
+
[edk2-devel] [PATCH V2 11/32] AMD/VanGoghBoard: Check in FvbServices
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial FvbServices module. It describes platform flash IC information
for FlashUpdate module to send command correctly.
Different flash ICs may use the different Opcodes.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../VanGoghCommonPkg/FvbServices/FvbInfo.c| 120 ++
.../FvbServices/FwBlockService.c | 1285 +
.../FvbServices/FwBlockService.h | 515 +++
.../FvbServices/PlatformSmmSpi.inf| 68 +
4 files changed, 1988 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/PlatformSmmSpi.inf
diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
new file mode 100644
index 00..c0be635864
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FvbInfo.c
@@ -0,0 +1,120 @@
+/** @file
+Defines data structure that is the volume header found.These data is intent
+to decouple FVB driver with FV header.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include
+#include
+#include
+#include
+#include
+//
+// The Library classes this module consumes
+//
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#define FVB_MEDIA_BLOCK_SIZE (0x0001)
+
+#define SYSTEM_NV_BLOCK_NUM ((FixedPcdGet32(PcdFlashNvStorageVariableSize)+
FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) +
FixedPcdGet32(PcdFlashNvStorageFtwSpareSize))/ FVB_MEDIA_BLOCK_SIZE)
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ EFI_FIRMWARE_VOLUME_HEADERFvbInfo;
+ //
+ // EFI_FV_BLOCK_MAP_ENTRYExtraBlockMap[n];//n=0
+ //
+ EFI_FV_BLOCK_MAP_ENTRYEnd[1];
+} EFI_FVB2_MEDIA_INFO;
+
+EFI_FVB2_MEDIA_INFO mPlatformFvbMediaInfo =
+ //
+ // Systen NvStorage FVB
+ //
+{
+ 0,
+ {
+{
+ 0,
+},// ZeroVector[16]
+EFI_SYSTEM_NV_DATA_FV_GUID,
+FVB_MEDIA_BLOCK_SIZE *SYSTEM_NV_BLOCK_NUM,
+EFI_FVH_SIGNATURE,
+EFI_FVB2_MEMORY_MAPPED |
+EFI_FVB2_READ_ENABLED_CAP |
+EFI_FVB2_READ_STATUS |
+EFI_FVB2_WRITE_ENABLED_CAP |
+EFI_FVB2_WRITE_STATUS |
+EFI_FVB2_ERASE_POLARITY |
+EFI_FVB2_ALIGNMENT_16,
+sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+0xFBFF,// CheckSum
+0, // ExtHeaderOffset
+{
+ 0,
+},// Reserved[1]
+2,// Revision
+{
+ {
+SYSTEM_NV_BLOCK_NUM,
+FVB_MEDIA_BLOCK_SIZE,
+ }
+}
+ },
+ {
+{
+ 0,
+ 0
+}
+ }
+};
+
+/**
+ Get Fvb information.
+
+ @param[in] BaseAddressThe base address compare with NvStorageVariable
base address.
+ @param[out] FvbInfoFvb information.
+
+ @retval EFI_SUCCESS Get Fvb information successfully.
+ @retval EFI_NOT_FOUND Not find Fvb information.
+
+**/
+EFI_STATUS
+EFIAPI
+GetFvbInfo (
+ IN UINT64 BaseAddress,
+ OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo
+ )
+{
+ mPlatformFvbMediaInfo.BaseAddress = PcdGet32 (PcdFlashNvStorageVariableBase);
+
+ if (mPlatformFvbMediaInfo.BaseAddress == BaseAddress) {
+*FvbInfo =
+return EFI_SUCCESS;
+ }
+
+ return EFI_NOT_FOUND;
+}
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
new file mode 100644
index 00..f514ad772a
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FvbServices/FwBlockService.c
@@ -0,0 +1,1285 @@
+/** @file
+ Implements FvbServicesSmm
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013-2016 Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef _MSC_VER
+ #pragma optimize( "", off )
+#endif
+
+#ifdef __GNUC__
+ #ifndef __clang__
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+ #else
+#pragma clang optimize off
+ #endif
+#endif
+
+#include "FwBlockService.h"
+
+#define EFI_FVB2_STATUS
[edk2-devel] [PATCH V2 10/32] AMD/VanGoghBoard: Check in FlashUpdate
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Initial FlashUpdate module for Chachani platform flash IC.
It provides mEfiSpiFlashUpdateProtocol for other module to access flash.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../FlashUpdate/FlashUpdateCommon.h | 143 +
.../FlashUpdate/FlashUpdateSmm.c | 512 ++
.../FlashUpdate/FlashUpdateSmm.h | 123 +
.../FlashUpdate/FlashUpdateSmm.inf| 59 ++
.../FlashUpdate/FlashUpdateSmmRuntimeDxe.c| 407 ++
.../FlashUpdate/FlashUpdateSmmRuntimeDxe.inf | 48 ++
.../VanGoghCommonPkg/FlashUpdate/PcRtc.h | 375 +
7 files changed, 1667 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmm.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmm.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmm.inf
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmmRuntimeDxe.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateSmmRuntimeDxe.inf
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/PcRtc.h
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
new file mode 100644
index 00..616035b82d
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/FlashUpdate/FlashUpdateCommon.h
@@ -0,0 +1,143 @@
+/** @file
+ Implements AMD FlashUpdateCommon.h
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef FLASH_UPDATE_COMMON_H__
+#define FLASH_UPDATE_COMMON_H__
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+
+#include
+
+#define SPI_SMM_COMM_ID_GET_FLASH_SIZE_BLOCK_SIZE 0x0 // ID for get
flash size and block size
+#define SPI_SMM_COMM_ID_READ_FLASH 0x1 // ID for Read
Flash
+#define SPI_SMM_COMM_ID_WRITE_FALSH0x2 // ID for Write
Flash
+#define SPI_SMM_COMM_ID_ERASE_FALSH0x3 // ID for Erase
Flash
+
+//
+// SMM communication common buffer
+//
+typedef struct _FLASH_UPDATE_SMM_COMMUNICATION_CMN {
+ UINT32id; // Function ID of smm communication buffer
+} FLASH_UPDATE_SMM_COMMUNICATION_CMN;
+
+#pragma pack(1)
+
+//
+// SMM communication common buffer
+//
+typedef struct _SMM_COMM_RWE_FLASH {
+ UINT32id; // ID of smm communication buffer
+ UINTN FlashAddress;// Flash devicd physical flash
address
+ UINTN NumBytes;// Number in byte
+ EFI_STATUSReturnStatus;// Return status
+ UINT8 Buffer[1]; // Buffer start
+} SMM_COMM_RWE_FLASH;
+
+//
+// SMM communication common buffer
+//
+typedef struct _SMM_COMM_GET_FLASH_SIZE_BLOCK_SIZE {
+ UINT32id; // ID of smm communication buffer
+ UINTN FlashSize;// Flash size
+ UINTN BlockSize;// Block size of flash device
+ EFI_STATUSReturnStatus; // Return status
+} SMM_COMM_GET_FLASH_SIZE_BLOCK_SIZE;
+
+#pragma pack()
+
+#define SMM_COMMUNICATE_HEADER_SIZE (OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER,
Data))
+#define SMM_COMM_RWE_FLASH_SIZE (OFFSET_OF (SMM_COMM_RWE_FLASH, Buffer))
+
+/**
+ Read data from flash device.
+
+ @param[in] FlashAddressPhysical flash address.
+ @param[in] NumBytesNumber in Byte.
+ @param[out] Buffer Buffer contain the read data.
+
+ @retval EFI_SUCCESS Read successfully.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval others Some error occurs when executing
this routine.
+
+**/
+EFI_STATUS
+EFIAPI
+SfuProtocolFlashFdRead (
+ IN UINTN FlashAddress,
+ IN UINTN NumBytes,
+ OUT VOID *Buffer
+ );
+
+/**
+ Erase flash region according to input in a block size.
+
+ @param[in] FlashAddress Physical flash address.
+ @param[in] NumBytes Number in Byte, a block size in
flash device.
+
+ @retval EFI_SUCCESS Erase successfully.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval others
[edk2-devel] [PATCH V2 09/32] AMD/VanGoghBoard: Check in Flash_AB
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[edk2-devel] [PATCH V2 08/32] AMD/VanGoghBoard: Check in UDKFlashUpdate
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
UDKFlashUpdate is a uefi tool for BIOS binary updating. It depends on EDK2's
flash access protocol.
UDKFlashUpdate needs to run under EDK2 BIOS.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../UDKFlashUpdate/SpiFlashDevice.c | 37 +
.../UDKFlashUpdate/SpiFlashDevice.h | 62 ++
.../UDKFlashUpdate/UDKFlashUpdate.c | 671 ++
.../UDKFlashUpdate/UDKFlashUpdate.h | 48 ++
.../UDKFlashUpdate/UDKFlashUpdate.inf | 51 ++
5 files changed, 869 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/UDKFlashUpdate.c
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/UDKFlashUpdate.h
create mode 100644
Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/UDKFlashUpdate.inf
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
new file mode 100644
index 00..d4f5b12f41
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.c
@@ -0,0 +1,37 @@
+/** @file
+ Implements SpiFlashDevice.c
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SpiFlashDevice.h"
+
+SPI_INIT_TABLE mSpiInitTable[] = {
+ { // W25Q256JW/W74M25JW
+SF_VENDOR_ID_WINBOND,
+SF_DEVICE_ID0_W25Q256JW,
+SF_DEVICE_ID1_W25Q256JW,
+{
+ SPI_COMMAND_WRITE_ENABLE,
+ SPI_COMMAND_WRITE_S_EN
+},
+{
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_JEDEC_ID,
EnumSpiOperationJedecId},
+ { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_WRITE_S,
EnumSpiOperationWriteStatus},
+ { EnumSpiOpcodeWrite,SPI_COMMAND_WRITE,
EnumSpiOperationProgramData_1_Byte },
+ { EnumSpiOpcodeRead, SPI_COMMAND_READ,
EnumSpiOperationReadData },
+ { EnumSpiOpcodeWrite,SPI_COMMAND_ERASE,
EnumSpiOperationErase_4K_Byte },
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_READ_S,
EnumSpiOperationReadStatus },
+ { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_CHIP_ERASE,
EnumSpiOperationFullChipErase },
+ { EnumSpiOpcodeRead, SPI_COMMAND_READ_SFDP,
EnumSpiOperationReadData },
+ { EnumSpiOpcodeWriteNoAddr,SPI_COMMAND_RPMC_OP1,
EnumSpiOperationOther },
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_RPMC_OP2,
EnumSpiOperationReadData },
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Enter_4Byte_Addr,
EnumSpiOperationOther },
+ { EnumSpiOpcodeReadNoAddr,SPI_COMMAND_Exit_4Byte_Addr,
EnumSpiOperationOther }
+},
+0,
+0x200 // BIOS image size in flash
+ }
+};
diff --git
a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
new file mode 100644
index 00..fe4d99e82c
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Application/UDKFlashUpdate/SpiFlashDevice.h
@@ -0,0 +1,62 @@
+/** @file
+ Implements SpiFlashDevice.h
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_FLASH_DEVICE_H__
+#define SPI_FLASH_DEVICE_H__
+
+#include
+#include
+#include
+
+//
+// Supported SPI Flash Devices
+//
+typedef enum {
+ EnumSpiFlashW25Q256JW,
+ EnumSpiFlashMax
+} SPI_FLASH_TYPES_SUPPORTED;
+
+// Flash Device commands
+//
+// If a supported device uses a command different from the list below, a
device specific command
+// will be defined just below it's JEDEC id section.
+//
+#define SPI_COMMAND_WRITE 0x02
+#define SPI_COMMAND_WRITE_AAI 0xAD
+#define SPI_COMMAND_READ 0x03
+#define SPI_COMMAND_ERASE 0x20
+#define SPI_COMMAND_WRITE_DISABLE 0x04
+#define SPI_COMMAND_READ_S0x05
+#define SPI_COMMAND_WRITE_ENABLE 0x06
+#define SPI_COMMAND_READ_ID 0xAB
+#define SPI_COMMAND_JEDEC_ID 0x9F
+#define SPI_COMMAND_WRITE_S_EN0x50
+#define SPI_COMMAND_WRITE_S 0x01
+#define SPI_COMMAND_CHIP_ERASE
[edk2-devel] [PATCH V2 06/32] AMD/VanGoghBoard: Check in AmdIdsExtLib
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
A small part of Chachani platform code and FSPWrapperPkg needs IdsHookExtLib.
Initial AmdIdsHookExtLibNull for ChachaniBoardPkg module.
Signed-off-by: Ken Yao
Cc: Duke Zhai
Cc: Eric Xing
Cc: Igniculus Fu
Cc: Abner Chang
---
.../AmdIdsExtLibNull/AmdIdsHookExtLibNull.c | 33
.../AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf | 39 +++
2 files changed, 72 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
new file mode 100644
index 00..f59b5beea1
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.c
@@ -0,0 +1,33 @@
+/** @file
+ Implements AmdIdsHookExtLibNull.c
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+
+typedef enum {
+ IDS_HOOK_UNSUPPORTED = 1
+} IDS_HOOK_STATUS;
+
+IDS_HOOK_STATUS
+IdsHookExtEntry (
+ UINT32 HookId,
+ VOID*Handle,
+ VOID*Data
+ )
+{
+ return IDS_HOOK_UNSUPPORTED;
+}
+
+IDS_HOOK_STATUS
+GetIdsNvTable (
+ IN OUT VOID*IdsNvTable,
+ IN OUT UINT32 *IdsNvTableSize
+ )
+{
+ return IDS_HOOK_UNSUPPORTED;
+}
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
new file mode 100644
index 00..354c19dd19
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf
@@ -0,0 +1,39 @@
+## @file
+# Amd Ids Hook Ext Lib Module INF file
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 0x00010006
+ BASE_NAME = AmdIdsHookExtLibNull.inf
+ FILE_GUID = CB364A1C-793D-46CE-B80A-0AB5FCB16D76
+ MODULE_TYPE= BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = AmdIdsHookExtLib
+
+[Sources.common]
+ AmdIdsHookExtLibNull.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+
+[Guids]
+
+[Protocols]
+
+[Ppis]
+
+[FeaturePcd]
+
+[Pcd]
+
+[Depex]
+ TRUE
+
+[BuildOptions]
+
--
2.31.1
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[edk2-devel] [PATCH V2 07/32] AMD/VanGoghBoard: Check in PciPlatform
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
BIOS detects current IGPU device ID and install corresponding VBIOS.
Inital PciPlatform module to load VBIOS and to provide interface for
other option ROMs if necessary.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../Include/Protocol/GlobalNvsArea.h | 63 ++
.../PciPlatform/CommonHeader.h| 27 +++
.../PciPlatform/PciPlatform.c | 183 ++
.../PciPlatform/PciPlatform.h | 89 +
.../PciPlatform/PciPlatform.inf | 51 +
5 files changed, 413 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.h
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.inf
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
new file mode 100644
index 00..e844932cc0
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvsArea.h
@@ -0,0 +1,63 @@
+/** @file
+Definition of the global NVS area protocol. This protocol
+publishes the address and format of a global ACPI NVS buffer
+used as a communications buffer between SMM code and ASL code.
+The format is derived from the ACPI reference code, version 0.95.
+Note: Data structures defined in this protocol are not naturally aligned.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef GLOBAL_NVS_AREA_H__
+#define GLOBAL_NVS_AREA_H__
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE 1
+#define GLOBAL_NVS_DEVICE_DISABLE 0
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc} }
+
+//
+// Revision id - Added TPM related fields
+//
+#define GLOBAL_NVS_AREA_RIVISION_1 1
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#pragma pack (1)
+typedef struct {
+ //
+ // Miscellaneous Dynamic Values, the definitions below need to be matched
+ // GNVS definitions in Platform.ASL
+ //
+ UINT32TopOfMem; // TOPM
+ UINT8 NbIoApic; // NAPC
+ UINT32PcieBaseAddress;// PCBA
+ UINT32PcieBaseLimit; // PCBL
+} EFI_GLOBAL_NVS_AREA;
+#pragma pack ()
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+ EFI_GLOBAL_NVS_AREA*Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
new file mode 100644
index 00..f4e6461206
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h
@@ -0,0 +1,27 @@
+/** @file
+ Implements CommonHeader.h
+ This file includes package header files, library classes and protocol, PPI &
GUID definitions.
+
+ Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef COMMON_HEADER_H___
+#define COMMON_HEADER_H___
+
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#endif
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
new file mode 100644
index 00..aa0a133b1f
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c
@@ -0,0 +1,183 @@
+/** @file
+ Implements PciPlatform.c
+ Registers onboard PCI ROMs with PCI.IO
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CommonHeader.h"
+
+#include "PciPlatform.h"
+
+PCI_OPTION_ROM_TABLE mPciOptionRomTable[] = {
+ { ONBOARD_SPH_VIDEO_OPTION_ROM_FILE_GUID, 0x1002, 0x1435 },
+ { NULL_ROM_FILE_GUID, 0x, 0x
[edk2-devel] [PATCH V2 03/32] AMD/VanGoghBoard: Check in Capsule update
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Chachani board supports "Capsule on Disk (CoD)" feature defined in UEFI
Spec chapter 8.5.5 "Delivery of Capsules via file on Mass Storage Device".
The BIOS capsule image is saved in hard disk as default setting.
Signed-off-by: Ken Yao
Cc: Duke Zhai
Cc: Eric Xing
Cc: Igniculus Fu
Cc: Abner Chang
---
.../SystemFirmwareDescriptor.aslc | 85 ++
.../SystemFirmwareDescriptor.inf | 39 +
.../SystemFirmwareDescriptorPei.c | 64 +
.../Include/Library/CapsuleHookLib.h | 40 +
.../Capsule/CapsuleHookLib/CapsuleHookLib.c | 1153 +
.../Capsule/CapsuleHookLib/CapsuleHookLib.inf | 56 +
.../PlatformBootManager.c | 794
.../PlatformBootManager.h | 150 +++
.../PlatformBootManagerLib.inf| 89 ++
.../PlatformBootManagerLib/PlatformConsole.c | 495 +++
.../PlatformBootManagerLib/PlatformConsole.h | 69 +
.../PlatformBootManagerLib/PlatformData.c | 39 +
.../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 122 ++
.../CapsuleRuntimeDxe/CapsuleService.c| 461 +++
.../CapsuleRuntimeDxe/CapsuleService.h| 73 ++
15 files changed, 3729 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Library/CapsuleHookLib.h
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/CapsuleHookLib/CapsuleHookLib.c
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/CapsuleHookLib/CapsuleHookLib.inf
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformBootManager.c
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformBootManager.h
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformBootManagerLib.inf
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformConsole.c
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformConsole.h
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/Capsule/PlatformBootManagerLib/PlatformData.c
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleService.c
create mode 100644
Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleService.h
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
new file mode 100644
index 00..2e05a523c7
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
@@ -0,0 +1,85 @@
+/** @file
+ System firmware Descriptor file
+ System Firmware descriptor.
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+
+#define PACKAGE_VERSION 0x
+#define PACKAGE_VERSION_STRING L"Unknown"
+
+#define CURRENT_FIRMWARE_VERSION0x3818
+#define CURRENT_FIRMWARE_VERSION_STRING L"3818"
+#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x0001
+
+#define IMAGE_IDSIGNATURE_64('C', 'H', 'A', 'C',
'H', 'A','N','I')
+#define IMAGE_ID_STRING L"ChachaniFD"
+
+// PcdSystemFmpCapsuleImageTypeIdGuid
+#define IMAGE_TYPE_ID_GUID { 0x38663fe6, 0x934f, 0x42a1, {
0xbc, 0xb0, 0xf7, 0x9e, 0x62, 0xec, 0xbe, 0x80 } }
+
+typedef struct {
+ EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
+ // real string data
+ CHAR16
ImageIdNameStr[sizeof(IMAGE_ID_STRING)/sizeof(CHAR16)];
+ CHAR16
VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING)/sizeof(CHAR16)];
+
[edk2-devel] [PATCH V2 05/32]AMD/VanGoghBoard: Check in PlatformSecLib
From: Duke Zhai BZ #:4640 In V2: Improve coding style. 1.Remove the leading underscore and use double underscore at trailing in C header files. 2.Remove old tianocore licenses and redundant license description. 3.Improve coding style. For example: remove space between @param. In V1: Chachani board jump to PlatformSec function after x86 releasing. This module provides the SEC entry function, which does platform-related early initialization. Signed-off-by: Ken Yao Cc: Duke Zhai Cc: Eric Xing Cc: Igniculus Fu Cc: Abner Chang --- .../Library/PlatformSecLib/Ia32/Flat32.nasm | 534 ++ .../Library/PlatformSecLib/Ia32/Platform.inc | 53 ++ .../Library/PlatformSecLib/PlatformSecLib.c | 196 +++ .../Library/PlatformSecLib/PlatformSecLib.inf | 61 ++ .../PlatformSecLib/PlatformSecLibModStrs.uni | 19 + 5 files changed, 863 insertions(+) create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.c create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm new file mode 100644 index 00..5638c411e3 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm @@ -0,0 +1,534 @@ +;/** @file +; AMD VanGoghBoard PlatformSecLib +; This is the code that goes from real-mode to protected mode. +; It consumes the reset vector, configures the stack. +; +; Copyright (c) 2013-2015 Intel Corporation. All rights reserved. +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;**/ + +; +; Include processor definitions +; +%use masm + + +%include "Platform.inc" + +; +; CR0 cache control bit definition +; +CR0_CACHE_DISABLE EQU 04000h +CR0_NO_WRITEEQU 02000h +BSP_STACK_BASE_ADDR EQU FixedPcdGet32 (PcdPeiCorePeiPreMemoryStackBaseAddress) ; Base address for core 0 stack +PRE_MEM_STACK_SIZE EQU FixedPcdGet32 (PcdPeiCorePeiPreMemoryStackSize) +PCIEX_LENGTH_BIT_SETTING EQU 011000b + +MSR_IA32_EFER EQU 0c080h ; Extended Feature Enable Register +MSR_IA32_EFER_LME EQU 8; Long Mode Enable + +MSR_SMM_BASEEQU 0c0010111h ; SMBASE Register + +SMM_BASE_DEFAULTEQU 3h ; reset value of MSR MSR_SMM_BASE + +SMMMASK_ADDRESS EQU 0c0010113h ; SMM TSeg Base Address +SMMMASK_ADDRESS_AE EQU 0; Aseg Address Range Enable +SMMMASK_ADDRESS_TE EQU 1; Tseg Address Range Enable + +; +; In Modified Conventional Resume S3 Design: +; With Modified Conventional Resume path, the x86 resumes from sleep, +; begins executing code from a predefined SMM resume vector and then +; jump to ROM code to continue conventional resume. +; EDX is filled with special signature "0x55AABB66" when jump to Sec, +; this signature can be used to identify if resume back from SMM resume. +; +SMM_RESUME_SIGNATUREEQU 055AABB66h + +PCAT_RTC_ADDRESS_REGISTER EQU 0x70 +PCAT_RTC_DATA_REGISTER EQU 0x71 + +NMI_DISABLE_BIT EQU 0x80 + +RTC_ADDRESS_REGISTER_A EQU 0x0A ; R/W[0..6] R0[7] +RTC_ADDRESS_REGISTER_B EQU 0x0B ; R/W +RTC_ADDRESS_REGISTER_C EQU 0x0C ; RO +RTC_ADDRESS_REGISTER_D EQU 0x0D ; R/W + +; +; External and public declarations +; TopOfStack is used by C code +; SecStartup is the entry point to the C code +; Neither of these names can be modified without +; updating the C code. +; +extern ASM_PFX(SecStartup) + +SECTION .text +; +; Protected mode portion initializes stack, configures cache, and calls C entry point +; + +; +; +; Procedure:ProtectedModeEntryPoint +; +; Input:Executing in 32 Bit Protected (flat) mode +;cs: 0-4GB +;ds: 0-4GB +;es: 0-4GB +;fs: 0-4GB +;gs: 0-4GB +;ss: 0-4GB +; +; Output: This function never returns +; +; Destroys: +; ecx +; edi +;esi +;esp +; +; Description: +;Perform any essential early platform initilaisation +; Setup a stack +; Call the main EDKII Sec C code +; +; + +global ASM_PFX(_ModuleEntryPoint)
[edk2-devel] [PATCH V2 02/32] AMD/VanGoghBoard: Check in ACPI tables
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[edk2-devel] [PATCH V2 04/32] AMD/VanGoghBoard: Check in AgesaPublic pkg
From: Duke Zhai
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Chachani board platform code depends on some AGESA-related PCDs/GUIDs.
Add AgesaPublicPkg for AGESA-related PCDs/GUIDs to support platfrom build.
Signed-off-by: Duke Zhai
Cc: Eric Xing
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../VanGoghBoard/AgesaPublic/AgesaPublic.dec | 61 +
.../VanGoghBoard/AgesaPublic/Include/AGESA.h | 35 +++
.../VanGoghBoard/AgesaPublic/Include/AMD.h| 189 +
.../AgesaPublic/Include/AmdPspDirectory.h | 55
.../AgesaPublic/Include/FchRegistersCommon.h | 23 ++
.../Include/Guid/AmdMemoryInfoHob.h | 51
.../Include/Library/AmdPspBaseLibV2.h | 248 ++
.../Include/Library/AmdPspCommonLib.h | 29 ++
.../Include/Library/AmdPspFtpmLib.h | 94 +++
.../AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h | 80 ++
.../Include/Protocol/AmdPspFtpmProtocol.h | 112
11 files changed, 977 insertions(+)
create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/Include/AGESA.h
create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/Include/AMD.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/AmdPspDirectory.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/FchRegistersCommon.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Guid/AmdMemoryInfoHob.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspBaseLibV2.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspCommonLib.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspFtpmLib.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Protocol/AmdPspFtpmProtocol.h
diff --git a/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
b/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
new file mode 100644
index 00..e987b9b603
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
@@ -0,0 +1,61 @@
+## @file
+# EDK II AgesaPublic.dec file
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = AgesaPublic
+ PACKAGE_GUID = EA54B0FA-908C-43DE-95A5-5E821A893CA4
+ PACKAGE_VERSION= 0.1
+
+[Includes]
+ Include
+
+[Guids]
+ gEfiAmdAgesaModulePkgTokenSpaceGuid = { 0x7788adf0, 0x9788, 0x4a3f, {
0x83, 0xfa, 0xcb, 0x51, 0x2e, 0x7c, 0xf8, 0xdd } }
+ gEfiAmdAgesaPkgTokenSpaceGuid= { 0xd4d8435f, 0xfffb, 0x4acb, {
0xa0, 0x4d, 0xff, 0x0f, 0xad, 0x67, 0x7f, 0xe9 } }
+ gAmdCpmPkgTokenSpaceGuid = { 0x916e0ddd, 0x2bd2, 0x4704, {
0x93, 0xb9, 0x59, 0x4b, 0x01, 0xa5, 0xfa, 0x9f } }
+ gAmdResourceSizeForEachRbGuid= { 0x542b8f2f, 0xbd52, 0x4233, {
0x8c, 0x3d, 0x66, 0x53, 0x0d, 0xe8, 0xa3, 0x69 } }
+ gAmdPbsSystemConfigurationGuid = { 0xa339d746, 0xf678, 0x49b3, {
0x9f, 0xc7, 0x54, 0xce, 0x0f, 0x9d, 0xf2, 0x26 } }
+ gAmdTotalNumberOfRootBridgesGuid = { 0xfb5703f5, 0xf8a7, 0xf401, {
0x18, 0xb4, 0x3f, 0x10, 0x8d, 0xeb, 0x26, 0x12 } }
+ gApSyncFlagNvVariableGuid= { 0xad3f6761, 0xf0a3, 0x46c8, {
0xa4, 0xcb, 0x19, 0xb7, 0x0f, 0xfd, 0xb3, 0x05 } }
+ gAmdMemoryInfoHobGuid= { 0x1bce3d14, 0xa5fe, 0x4a0b, {
0x9a, 0x8d, 0x69, 0xca, 0x5d, 0x98, 0x38, 0xd3 } }
+ gAmdPspApobHobGuid = { 0x30b174f3, 0x7712, 0x4cca, {
0xbd, 0x13, 0xd0, 0xb8, 0xa8, 0x80, 0x19, 0x97 } }
+
+[Protocols]
+ gPspFlashAccSmmCommReadyProtocolGuid = { 0x9f373486, 0xda76, 0x4c9f, {
0x81, 0x55, 0x6c, 0xcd, 0xdb, 0x0b, 0x0b, 0x04 } }
+ gAmdPspFtpmProtocolGuid = { 0xac234e04, 0xb036, 0x476c, {
0x91, 0x66, 0xbe, 0x47, 0x52, 0xa0, 0x95, 0x09 } }
+ gFchInitDonePolicyProtocolGuid = { 0xc63c0c73, 0xf612, 0x4c02, {
0x84, 0xa3, 0xc6, 0x40, 0xad, 0x0b, 0xa6, 0x22 } }
+ gAmdCapsuleSmmHookProtocolGuid = { 0x4fc43bbe, 0x1433, 0x4951, {
0xac, 0x2d, 0x0d, 0x01, 0xfe, 0xc0, 0x0e, 0xb1 } }
+ gAmdCpmAllPciIoProtocolsInstalledProtocolGuid = { 0x676D7012, 0x139B,
0x485A, { 0x96, 0xF1, 0x98, 0x6F, 0xC4, 0x8A, 0x86, 0x4B } }
+ gAmdFspSetupTableInitDoneGuid= { 0xef5394c6, 0x566d, 0x440f, {
0x9d, 0x05, 0xc0, 0xa3, 0x2c, 0xb9, 0x33, 0x58 } }
+
+[Ppis]
+ gAmdMemoryInfoHobPpiGuid = { 0xba16e587, 0x1d66, 0x41b7, {
0x9b, 0x52, 0xca, 0x4f, 0x2c, 0xad, 0x0d, 0xc8 } }
+
[edk2-devel] [PATCH V2 01/32] AMD/AmdPlatformPkg: Check in AMD S3 logo
From: Duke Zhai
BZ #:4640
In V2: Improve coding style
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
LogoDxe module displays boot logo.
S3LogoDxe module is based on EDK2 LogoDxe module and update AMD S3 logo.
Signed-off-by: Eric Xing
Cc: Duke Zhai
Cc: Ken Yao
Cc: Igniculus Fu
Cc: Abner Chang
---
.../AmdPlatformPkg/Universal/LogoDxe/Logo.c | 198 ++
.../Universal/LogoDxe/S3Logo.bmp | Bin 0 -> 964114 bytes
.../Universal/LogoDxe/S3Logo.idf | 9 +
.../Universal/LogoDxe/S3LogoDxe.inf | 55 +
4 files changed, 262 insertions(+)
create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.bmp
create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.idf
create mode 100644 Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3LogoDxe.inf
diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
new file mode 100644
index 00..4463ba58eb
--- /dev/null
+++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c
@@ -0,0 +1,198 @@
+/**
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+**/
+
+/** @file
+ Logo DXE Driver, install Edk2 Platform Logo protocol.
+
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "Logo.h"
+
+EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+EFI_HII_HANDLE mHiiHandle;
+LOGO_ENTRY mLogos[] = {
+ {
+IMAGE_TOKEN (IMG_LOGO),
+EdkiiPlatformLogoDisplayAttributeCenter,
+0,
+0
+ }
+};
+
+/**
+ Load a platform logo image and return its data and attributes.
+
+ @param[in] This The pointer to this protocol instance.
+ @param[in, out] Instance The visible image instance is found.
+ @param[out] Image Points to the image.
+ @param[out] Attribute The display attributes of the image
returned.
+ @param[out] OffsetX The X offset of the image regarding the
Attribute.
+ @param[out] OffsetY The Y offset of the image regarding the
Attribute.
+
+ @retval EFI_SUCCESSThe image was fetched successfully.
+ @retval EFI_NOT_FOUND The specified image could not be found.
+ @retval EFI_INVALID_PARAMETER One of the given input parameters are
incorrect
+**/
+EFI_STATUS
+EFIAPI
+GetImage (
+ IN EDKII_PLATFORM_LOGO_PROTOCOL*This,
+ IN OUT UINT32 *Instance,
+ OUT EFI_IMAGE_INPUT*Image,
+ OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+ OUT INTN *OffsetX,
+ OUT INTN *OffsetY
+ )
+{
+ UINT32 Current;
+
+ if ((Instance == NULL) || (Image == NULL) ||
+ (Attribute == NULL) || (OffsetX == NULL) || (OffsetY == NULL))
+ {
+return EFI_INVALID_PARAMETER;
+ }
+
+ Current = *Instance;
+ if (Current >= ARRAY_SIZE (mLogos)) {
+return EFI_NOT_FOUND;
+ }
+
+ (*Instance)++; // Advance to next logo.
+ *Attribute = mLogos[Current].Attribute;
+ *OffsetX = mLogos[Current].OffsetX;
+ *OffsetY = mLogos[Current].OffsetY;
+ return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
mLogos[Current].ImageId, Image);
+}
+
+EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+ GetImage
+};
+
+// AMD_EDKII_OVERRIDE START
+
+/**
+ After console ready before boot option event callback
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] ContextPointer to the context data registered to the Event.
+**/
+VOID
+EFIAPI
+LogoDxeDisplayEventCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ DEBUG ((DEBUG_INFO, "AMD logo is displaying.\n"));
+
+ BootLogoEnableLogo ();
+ gBS->CloseEvent (Event);
+}
+
+/**
+ Entrypoint of this module.
+
+ This function is the entrypoint of this module. It installs the Edkii
+ Platform Logo protocol.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+ IN EFI_HANDLEImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+ EFI_HII_DATABASE_PROTOCOL*HiiDatabase;
+ EFI_HANDLE Handle;
+ EFI_EVENTAfterConsoleReadyBeforeBootOptionEvent;
+
+ Status =
[edk2-devel] [PATCH V2 00/32] Introduce AMD Vangogh platform reference code
From: Duke Zhai In V2: Improve coding style. 1.Remove the leading underscore and use double underscore at trailing in C header files. 2.Remove old tianocore licenses and redundant license description. 3.Improve coding style. For example: remove space between @param. In V1: This AMD reference platform BIOS supports AMD Vangogh B0 SOC and Chachani board. Duke Zhai (32): AMD/AmdPlatformPkg: Check in AMD S3 logo AMD/VanGoghBoard: Check in ACPI tables AMD/VanGoghBoard: Check in Capsule update AMD/VanGoghBoard: Check in AgesaPublic pkg AMD/VanGoghBoard: Check in PlatformSecLib AMD/VanGoghBoard: Check in AmdIdsExtLib AMD/VanGoghBoard: Check in PciPlatform AMD/VanGoghBoard: Check in UDKFlashUpdate AMD/VanGoghBoard: Check in Flash_AB AMD/VanGoghBoard: Check in FlashUpdate AMD/VanGoghBoard: Check in FvbServices AMD/VanGoghBoard: Check in AMD BaseSerialPortLib AMD/VanGoghBoard: Check in PlatformFlashAccessLib AMD/VanGoghBoard: Check in SmbiosLib AMD/VanGoghBoard: Check in SpiFlashDeviceLib AMD/VanGoghBoard: Check in BaseTscTimerLib AMD/VanGoghBoard: Check in Smm access module AMD/VanGoghBoard: Check in PciHostBridge module AMD/VanGoghBoard: Check in PcatRealTimeClockRuntimeDxe module AMD/VanGoghBoard: Check in FTPM module AMD/VanGoghBoard: Check in SignedCapsule AMD/VanGoghBoard: Check in Vtf0 AMD/VanGoghBoard: Check in AcpiPlatform AMD/VanGoghBoard: Check in FchSpi module AMD/VanGoghBoard: Check in PlatformInitPei module AMD/VanGoghBoard: Check in Smbios platform dxe drivers AMD/VanGoghBoard: Check in Fsp2WrapperPkg AMD/VanGoghBoard: Check in SmmCpuFeaturesLibCommon module AMD/VanGoghBoard: Check in SmramSaveState module AMD/VanGoghBoard: Check in EDK2 override files AMD/VanGoghBoard: Check in AMD SmmControlPei module AMD/VanGoghBoard: Check in Chachani board project files and build script .../AmdPlatformPkg/Universal/LogoDxe/Logo.c | 198 + .../Universal/LogoDxe/S3Logo.bmp | Bin 0 -> 964114 bytes .../Universal/LogoDxe/S3Logo.idf |9 + .../Universal/LogoDxe/S3LogoDxe.inf | 55 + .../VanGoghBoard/AgesaPublic/AgesaPublic.dec | 61 + .../VanGoghBoard/AgesaPublic/Include/AGESA.h | 35 + .../VanGoghBoard/AgesaPublic/Include/AMD.h| 189 + .../AgesaPublic/Include/AmdPspDirectory.h | 55 + .../AgesaPublic/Include/FchRegistersCommon.h | 23 + .../Include/Guid/AmdMemoryInfoHob.h | 51 + .../Include/Library/AmdPspBaseLibV2.h | 248 + .../Include/Library/AmdPspCommonLib.h | 29 + .../Include/Library/AmdPspFtpmLib.h | 94 + .../AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h | 80 + .../Include/Protocol/AmdPspFtpmProtocol.h | 112 + .../Acpi/AcpiTables/AcpiTables.inf| 33 + .../Acpi/AcpiTables/Dsdt/CPU.asl | 22 + .../Acpi/AcpiTables/Dsdt/Dsdt.asl | 36 + .../Acpi/AcpiTables/Dsdt/FchShang.asi | 927 ++ .../Acpi/AcpiTables/Dsdt/GloblNvs.asl | 17 + .../Acpi/AcpiTables/Dsdt/HOST_BUS.ASL | 209 + .../Acpi/AcpiTables/Dsdt/LINK.ASL | 481 ++ .../Acpi/AcpiTables/Dsdt/Lpc0.asl | 168 + .../Acpi/AcpiTables/Dsdt/PciTree.asl | 776 ++ .../Acpi/AcpiTables/Dsdt/Platform.asl | 135 + .../Acpi/AcpiTables/Dsdt/_PR.asl | 36 + .../Acpi/AcpiTables/Facs/Facs.h | 31 + .../Acpi/AcpiTables/Facs/Facs50.aslc | 68 + .../Acpi/AcpiTables/Fadt/Fadt.h | 64 + .../Acpi/AcpiTables/Fadt/Fadt50.aslc | 159 + .../Acpi/AcpiTables/Hpet/Hpet.h | 70 + .../Acpi/AcpiTables/Hpet/Hpet50.aslc | 58 + .../Acpi/AcpiTables/Madt/Madt.h | 114 + .../Acpi/AcpiTables/Madt/Madt50.aslc | 327 + .../Acpi/AcpiTables/Mcfg/Mcfg.h | 61 + .../Acpi/AcpiTables/Mcfg/Mcfg50.aslc | 61 + .../BIOSImageDirectory32M.xml | 63 + .../VanGoghBoard/ChachaniBoardPkg/Board.env | 23 + .../ChachaniBoardPkg/BuildPspImage.bat| 126 + .../SystemFirmwareDescriptor.aslc | 85 + .../SystemFirmwareDescriptor.inf | 39 + .../SystemFirmwareDescriptorPei.c | 64 + .../ChachaniBoardPkg/Conf/ReadMe.txt | 14 + .../ChachaniBoardPkg/Conf/build_rule.txt | 654 ++ .../ChachaniBoardPkg/Conf/target.txt | 73 + .../ChachaniBoardPkg/Conf/tools_def.txt | 7571 + .../ChachaniBoardPkg/FlashABImage32M.py | 102 + .../ChachaniBoardPkg/GenCapsule.bat | 81 + .../ChachaniBoardPkg/GenFlashABImage.bat | 39 + .../ChachaniBoardPkg/GoZ_ChachaniExt.bat | 81 + .../Include/Library/CapsuleHookLib.h | 40 + .../Include/Protocol/GlobalNvsArea.h | 63 + .../AmdIdsExtLibNull/AmdIdsHookExtLibNull.c | 33 + .../AmdIdsExtLibNull/AmdIdsHookExtLibNull.inf | 39 +
[edk2-devel] [Patch V3] BaseTools: VfrCompiler Adds DefaultValueError
Add --catch_default option to raise a DefaultValueError when
encountering VFR default definitions to help remove default variables.
Signed-off-by: Yuting Yang
Cc: Rebecca Cran
Cc: Liming Gao
Cc: Bob Feng
Cc: Christine Chen
Cc: Zifeng Zhang
Signed-off-by: Yuting Yang
---
BaseTools/Source/C/VfrCompile/VfrCompiler.cpp | 8 +-
BaseTools/Source/C/VfrCompile/VfrCompiler.h | 1 +
BaseTools/Source/C/VfrCompile/VfrError.cpp| 3 +-
BaseTools/Source/C/VfrCompile/VfrError.h | 3 +-
BaseTools/Source/C/VfrCompile/VfrFormPkg.h| 1 +
BaseTools/Source/C/VfrCompile/VfrSyntax.g | 238 ++
6 files changed, 150 insertions(+), 104 deletions(-)
diff --git a/BaseTools/Source/C/VfrCompile/VfrCompiler.cpp
b/BaseTools/Source/C/VfrCompile/VfrCompiler.cpp
index 5f4d262d85..4031af6e39 100644
--- a/BaseTools/Source/C/VfrCompile/VfrCompiler.cpp
+++ b/BaseTools/Source/C/VfrCompile/VfrCompiler.cpp
@@ -78,6 +78,7 @@ CVfrCompiler::OptionInitialization (
mOptions.WarningAsError= FALSE;
mOptions.AutoDefault = FALSE;
mOptions.CheckDefault = FALSE;
+ mOptions.IsCatchDefaultEnable = FALSE;
memset (, 0, sizeof (EFI_GUID));
if (Argc == 1) {
@@ -95,6 +96,8 @@ CVfrCompiler::OptionInitialization (
Version ();
SET_RUN_STATUS (STATUS_DEAD);
return;
+} else if (stricmp(Argv[Index], "--catch_default") == 0){
+ mOptions.IsCatchDefaultEnable = TRUE;
} else if (stricmp(Argv[Index], "-l") == 0) {
mOptions.CreateRecordListFile = TRUE;
gCIfrRecordInfoDB.TurnOn ();
@@ -179,7 +182,6 @@ CVfrCompiler::OptionInitialization (
goto Fail;
}
strcpy (mOptions.VfrFileName, Argv[Index]);
-
if (mOptions.OutputDirectory == NULL) {
mOptions.OutputDirectory = (CHAR8 *) malloc (1);
if (mOptions.OutputDirectory == NULL) {
@@ -679,7 +681,7 @@ CVfrCompiler::Compile (
DebugError (NULL, 0, 0001, "Error opening the input file", "%s",
InFileName);
goto Fail;
}
-
+ InputInfo.IsCatchDefaultEnable = mOptions.IsCatchDefaultEnable;
if (mOptions.HasOverrideClassGuid) {
InputInfo.OverrideClassGuid =
} else {
@@ -937,5 +939,3 @@ main (
return GetUtilityStatus ();
}
-
-
diff --git a/BaseTools/Source/C/VfrCompile/VfrCompiler.h
b/BaseTools/Source/C/VfrCompile/VfrCompiler.h
index b6e207d2ce..974f37c4eb 100644
--- a/BaseTools/Source/C/VfrCompile/VfrCompiler.h
+++ b/BaseTools/Source/C/VfrCompile/VfrCompiler.h
@@ -52,6 +52,7 @@ typedef struct {
BOOLEAN WarningAsError;
BOOLEAN AutoDefault;
BOOLEAN CheckDefault;
+ BOOLEAN IsCatchDefaultEnable;
} OPTIONS;
typedef enum {
diff --git a/BaseTools/Source/C/VfrCompile/VfrError.cpp
b/BaseTools/Source/C/VfrCompile/VfrError.cpp
index 65bb8e34fd..8a706f929b 100644
--- a/BaseTools/Source/C/VfrCompile/VfrError.cpp
+++ b/BaseTools/Source/C/VfrCompile/VfrError.cpp
@@ -49,7 +49,8 @@ static SVFR_WARNING_HANDLE VFR_WARNING_HANDLE_TABLE [] = {
{ VFR_WARNING_DEFAULT_VALUE_REDEFINED, ": default value re-defined with
different value"},
{ VFR_WARNING_ACTION_WITH_TEXT_TWO, ": Action opcode should not have TextTwo
part"},
{ VFR_WARNING_OBSOLETED_FRAMEWORK_OPCODE, ": Not recommend to use obsoleted
framework opcode"},
- { VFR_WARNING_CODEUNDEFINED, ": undefined Warning Code" }
+ { VFR_WARNING_CODEUNDEFINED, ": undefined Warning Code" },
+ { VFR_WARNING_UNSUPPORTED, ": pls remove the default values if necessary" }
};
CVfrErrorHandle::CVfrErrorHandle (
diff --git a/BaseTools/Source/C/VfrCompile/VfrError.h
b/BaseTools/Source/C/VfrCompile/VfrError.h
index 7d16bd5f74..1b4bc173d2 100644
--- a/BaseTools/Source/C/VfrCompile/VfrError.h
+++ b/BaseTools/Source/C/VfrCompile/VfrError.h
@@ -47,7 +47,8 @@ typedef enum {
VFR_WARNING_DEFAULT_VALUE_REDEFINED = 0,
VFR_WARNING_ACTION_WITH_TEXT_TWO,
VFR_WARNING_OBSOLETED_FRAMEWORK_OPCODE,
- VFR_WARNING_CODEUNDEFINED
+ VFR_WARNING_CODEUNDEFINED,
+ VFR_WARNING_UNSUPPORTED
} EFI_VFR_WARNING_CODE;
typedef struct _SVFR_ERROR_HANDLE {
diff --git a/BaseTools/Source/C/VfrCompile/VfrFormPkg.h
b/BaseTools/Source/C/VfrCompile/VfrFormPkg.h
index 9ef6f07787..d8fada3bcb 100644
--- a/BaseTools/Source/C/VfrCompile/VfrFormPkg.h
+++ b/BaseTools/Source/C/VfrCompile/VfrFormPkg.h
@@ -96,6 +96,7 @@ struct SBufferNode {
typedef struct {
EFI_GUID *OverrideClassGuid;
+ BOOLEAN IsCatchDefaultEnable;
} INPUT_INFO_TO_SYNTAX;
class CFormPkg {
diff --git a/BaseTools/Source/C/VfrCompile/VfrSyntax.g
b/BaseTools/Source/C/VfrCompile/VfrSyntax.g
index 55fd067f8a..5daf1c423c 100644
--- a/BaseTools/Source/C/VfrCompile/VfrSyntax.g
+++ b/BaseTools/Source/C/VfrCompile/VfrSyntax.g
@@ -50,6 +50,7 @@ VfrParserStart (
{
ParserBlackBox VfrParser(File);
VfrParser.parser()->SetOverrideClassGuid (InputInfo->OverrideClassGuid);
+ VfrParser.parser()->SetIsCatchDefaultEnable(InputInfo->IsCatchDefaultEnable);
return VfrParser.parser()->vfrProgram();
}
>>
@@ -386,8 +387,8 @@
Re: [edk2-devel] [PATCH v2 1/2] MdeModulePkg: rename PcdUse5LevelPageTable to PcdEnable5LevelPageTable
Hi Gerd, For the PCD, it current has below usage. 1) for 32-bit PEI and 64-bit DXE, this PCD will decide if use 5 level paging in DXE. 2) for 64-bit PEI and DXE, reset vector chooses if use 5 level paging in early phase. But BIOS can still switch paging mode based on this PCD later. Since this PCD can be dynamic, we can let user to choose different paging mode in BIOS setup menu, and use this paging mode on reboot. You may want to use one BIOS to support machine with different la57 capability, I assume two possible ways: 1) make the PCD as dynamic, and set it based on la57 capability. 2) Remove the ASSERT in DxeIpl Both are fine for me. Thanks Zhiguang > -Original Message- > From: devel@edk2.groups.io On Behalf Of Gerd > Hoffmann > Sent: Thursday, January 25, 2024 8:17 PM > To: Ni, Ray > Cc: devel@edk2.groups.io; Liming Gao ; László > Érsek ; Oliver Steffen > Subject: Re: [edk2-devel] [PATCH v2 1/2] MdeModulePkg: rename > PcdUse5LevelPageTable to PcdEnable5LevelPageTable > > On Thu, Jan 25, 2024 at 12:01:46PM +, Ni, Ray wrote: > > Rename an existing PCD might break lots of platform builds. > > > > When 5-level paging capability was added to ResetVector, I also > > considered to remove the PcdUse5LevelPageTable reference from C code. > > > > Let me think about it... > > Purging this completely from the source code is fine with me too. > > From OVMF point of view this is not needed, all backward compatibility > concerns for old guests without 5-level paging support can be solved by just > removing la57 capability from the vCPU (qemu -cpu host,la57=off). > > take care, > Gerd > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114491): https://edk2.groups.io/g/devel/message/114491 Mute This Topic: https://groups.io/mt/103950404/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-redfish-client][PATCH V3] RedfishClientPkg/FeatureDriver: ComputerSystem_1_13_0 driver
Reviewed-by: Nickle Wang
Regards,
Nickle
> -Original Message-
> From: abner.ch...@amd.com
> Sent: Friday, January 26, 2024 10:32 AM
> To: devel@edk2.groups.io
> Cc: Nickle Wang ; Igor Kulchytskyy
> Subject: [edk2-redfish-client][PATCH V3] RedfishClientPkg/FeatureDriver:
> ComputerSystem_1_13_0 driver
>
> External email: Use caution opening links or attachments
>
>
> From: Abner Chang
>
> Initial version of edk2 Redfish feature of
> Redfish schema ComputerSystem_1_13_0. This driver
> handles ComputerSystem Boot properties but not all.
>
> Signed-off-by: Abner Chang
> Cc: Nickle Wang
> Cc: Igor Kulchytskyy
> ---
> .../v1_13_0/Dxe/ComputerSystemDxe.inf | 53 ++
> .../v1_13_0/Common/ComputerSystemCommon.h | 29 +
> .../v1_13_0/Common/ComputerSystemCommon.c | 899
> ++
> .../v1_13_0/Dxe/ComputerSystemDxe.c | 702 ++
> 4 files changed, 1683 insertions(+)
> create mode 100644
> RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.
> inf
> create mode 100644
> RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyste
> mCommon.h
> create mode 100644
> RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyste
> mCommon.c
> create mode 100644
> RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.
> c
>
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemD
> xe.inf
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemD
> xe.inf
> new file mode 100644
> index 00..be1c2164d8
> --- /dev/null
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemD
> xe.inf
> @@ -0,0 +1,53 @@
> +## @file
> +#
> +# (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
> +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = ComputerSystemDxe
> + FILE_GUID = D94362A1-C358-4059-B014-F07D1AE04F16
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING= 1.0
> + ENTRY_POINT = RedfishResourceEntryPoint
> + UNLOAD_IMAGE = RedfishResourceUnload
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + RedfishPkg/RedfishPkg.dec
> + RedfishClientPkg/RedfishClientPkg.dec
> +
> +[Sources]
> + ../Common/ComputerSystemCommon.h
> + ../Common/ComputerSystemCommon.c
> + ComputerSystemDxe.c
> +
> +[LibraryClasses]
> + BaseMemoryLib
> + DebugLib
> + EdkIIRedfishResourceConfigLib
> + RedfishLib
> + RedfishFeatureUtilityLib
> + RedfishResourceIdentifyLib
> + UefiLib
> + UefiDriverEntryPoint
> + RedfishAddendumLib
> + RedfishHttpCacheLib
> +
> +[Protocols]
> + gEdkIIRedfishConfigHandlerProtocolGuid ## PRODUCED
> + gEfiRestJsonStructureProtocolGuid ## CONSUMED
> + gEdkIIRedfishResourceConfigProtocolGuid ## PRODUCED
> +
> +[Pcd]
> + gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaStringSize
> + gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaVersionSize
> +
> +[Depex]
> + TRUE
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.h
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.h
> new file mode 100644
> index 00..7b83d2939c
> --- /dev/null
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.h
> @@ -0,0 +1,29 @@
> +/** @file
> +
> + Redfish feature driver implementation - internal header file
> + (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
> + Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights
> reserved.
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef EFI_REDFISH_COMPUTERSYSTEM_COMMON_H_
> +#define EFI_REDFISH_COMPUTERSYSTEM_COMMON_H_
> +
> +#include
> >
> +#include
> +
> +//
> +// Schema information.
> +//
> +#define RESOURCE_SCHEMA "ComputerSystem"
> +#define RESOURCE_SCHEMA_MAJOR"1"
> +#define RESOURCE_SCHEMA_MINOR"13"
> +#define RESOURCE_SCHEMA_ERRATA "0"
> +#define RESOURCE_SCHEMA_VERSION "v1_13_0"
> +#define REDPATH_ARRAY_PATTERNL"/Systems/\\{.*\\}/"
> +#define REDPATH_ARRAY_PREFIX L"/Systems/"
> +#define RESOURCE_SCHEMA_FULL "x-uefi-redfish-
> ComputerSystem.v1_13_0"
> +
> +#endif
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.c
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.c
> new file mode 100644
> index 00..cee6c8bf9b
> --- /dev/null
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.c
> @@ -0,0 +1,899 @@
> +/** @file
> + Redfish feature driver implementation - common functions
> +
> + (C) Copyright 2020-2022 Hewlett
Re: [edk2-devel] [edk2-redfish-client][PATCH V2] RedfishClientPkg/FeatureDriver: ComputerSystem_1_5_0 driver
Reviewed-by: Nickle Wang
Regards,
Nickle
> -Original Message-
> From: abner.ch...@amd.com
> Sent: Friday, January 26, 2024 10:29 AM
> To: devel@edk2.groups.io
> Cc: Nickle Wang ; Igor Kulchytskyy
> Subject: [edk2-redfish-client][PATCH V2] RedfishClientPkg/FeatureDriver:
> ComputerSystem_1_5_0 driver
>
> External email: Use caution opening links or attachments
>
>
> From: Abner Chang
>
> Update Redfish ComputerSystem_1_5_0 feature driver to align the
> implementation with latest code. This driver handles all of ComputerSystem
> v1_5_0 properties and incorporate with Redfish simualtor.
>
> Signed-off-by: Abner Chang
> Cc: Nickle Wang
> Cc: Igor Kulchytskyy
> ---
> .../v1_5_0/Dxe/ComputerSystemDxe.inf | 1 +
> .../v1_5_0/Common/ComputerSystemCommon.c | 347 --
> .../v1_5_0/Dxe/ComputerSystemDxe.c| 64 ++--
> 3 files changed, 271 insertions(+), 141 deletions(-)
>
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDx
> e.inf
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDx
> e.inf
> index 36cbe06211..4e7dc5c7c5 100644
> ---
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDx
> e.inf
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystem
> +++ Dxe.inf
> @@ -37,6 +37,7 @@
>RedfishResourceIdentifyLib
>UefiLib
>UefiDriverEntryPoint
> + RedfishAddendumLib
>RedfishHttpCacheLib
>
> [Protocols]
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSyste
> mCommon.c
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSyste
> mCommon.c
> index 3ace03bd4c..a67ef3dac2 100644
> ---
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSyste
> mCommon.c
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSys
> +++ temCommon.c
> @@ -53,7 +53,7 @@ RedfishConsumeResourceCommon (
>(EFI_REST_JSON_STRUCTURE_HEADER
> **)
>);
>if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_ERROR, "%a, ToStructure() failed: %r\n", __func__,
> Status));
> +DEBUG ((DEBUG_ERROR, "%a: ToStructure() failed: %r\n", __func__,
> + Status));
> return Status;
>}
>
> @@ -66,8 +66,8 @@ RedfishConsumeResourceCommon (
> //
> // No change
> //
> -DEBUG ((DEBUG_MANAGEABILITY, "%a, ETAG: %s has no change, ignore
> consume action\n", __func__, Private->Uri));
> -Status = EFI_ALREADY_STARTED;
> +DEBUG ((DEBUG_MANAGEABILITY, "%a: ETAG: %s has no change, ignore
> consume action\n", __func__, Private->Uri));
> +Status = EFI_SUCCESS;
> goto ON_RELEASE;
>}
>
> @@ -154,12 +154,12 @@ RedfishConsumeResourceCommon (
> if (ConfigureLang != NULL) {
>Status = ApplyFeatureSettingsStringArrayType (RESOURCE_SCHEMA,
> RESOURCE_SCHEMA_VERSION, ConfigureLang, ComputerSystemCs->Boot-
> >BootOrder);
>if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
> __func__,
> ConfigureLang, Status));
> +DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
> + __func__, ConfigureLang, Status));
>}
>
>FreePool (ConfigureLang);
> } else {
> - DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI:
> %s\n",
> __func__, Private->Uri));
> + DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI:
> + %s\n", __func__, Private->Uri));
> }
>}
>
> @@ -174,12 +174,12 @@ RedfishConsumeResourceCommon (
> if (ConfigureLang != NULL) {
>Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
> RESOURCE_SCHEMA_VERSION, ConfigureLang, ComputerSystemCs->Boot-
> >BootSourceOverrideEnabled);
>if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
> __func__,
> ConfigureLang, Status));
> +DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
> + __func__, ConfigureLang, Status));
>}
>
>FreePool (ConfigureLang);
> } else {
> - DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI:
> %s\n",
> __func__, Private->Uri));
> + DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI:
> + %s\n", __func__, Private->Uri));
> }
>}
>
> @@ -194,12 +194,12 @@ RedfishConsumeResourceCommon (
> if (ConfigureLang != NULL) {
>Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
> RESOURCE_SCHEMA_VERSION, ConfigureLang, ComputerSystemCs->Boot-
> >BootSourceOverrideMode);
>if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
> __func__,
> ConfigureLang, Status));
> +DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
> + __func__, ConfigureLang, Status));
>}
>
>FreePool (ConfigureLang);
> } else {
> - DEBUG ((DEBUG_ERROR, "%a, can
Re: [edk2-devel] [edk2-redfish-client][PATCH V2] RedfishClientPkg/FeatureDriver: ComputerSystem_1_13_0 driver
[AMD Official Use Only - General] Thanks Nickle, I just sent out the updates. Abner > -Original Message- > From: Nickle Wang > Sent: Friday, January 26, 2024 10:21 AM > To: devel@edk2.groups.io; Chang, Abner > Cc: Igor Kulchytskyy > Subject: RE: [edk2-devel] [edk2-redfish-client][PATCH V2] > RedfishClientPkg/FeatureDriver: ComputerSystem_1_13_0 driver > > Caution: This message originated from an External Source. Use proper caution > when opening attachments, clicking links, or responding. > > > Hi Abner, > > Same minor issue as 1_5_0. Please add "%a:" to below DEBUG call. > > > + DEBUG ((DEBUG_MANAGEABILITY, " No platform Redfish > ConfigureLang > > found for %s\n", __func__, Private->Uri)); > > Regards, > Nickle > > > -Original Message- > > From: devel@edk2.groups.io On Behalf Of Chang, > Abner > > via groups.io > > Sent: Friday, January 26, 2024 9:00 AM > > To: devel@edk2.groups.io > > Cc: Nickle Wang ; Igor Kulchytskyy > > Subject: [edk2-devel] [edk2-redfish-client][PATCH V2] > > RedfishClientPkg/FeatureDriver: ComputerSystem_1_13_0 driver > > > > External email: Use caution opening links or attachments > > > > > > From: Abner Chang > > > > Initial version of edk2 Redfish feature of > > Redfish schema ComputerSystem_1_13_0. This driver > > handles ComputerSystem Boot properties but not all. > > > > Signed-off-by: Abner Chang > > Cc: Nickle Wang > > Cc: Igor Kulchytskyy > > --- > > .../v1_13_0/Dxe/ComputerSystemDxe.inf | 53 ++ > > .../v1_13_0/Common/ComputerSystemCommon.h | 29 + > > .../v1_13_0/Common/ComputerSystemCommon.c | 899 > > ++ > > .../v1_13_0/Dxe/ComputerSystemDxe.c | 702 ++ > > 4 files changed, 1683 insertions(+) > > create mode 100644 > > > RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystem > Dxe. > > inf > > create mode 100644 > > > RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerS > yste > > mCommon.h > > create mode 100644 > > > RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerS > yste > > mCommon.c > > create mode 100644 > > > RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystem > Dxe. > > c > > > > diff --git > > > a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSyste > mD > > xe.inf > > > b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSyst > emD > > xe.inf > > new file mode 100644 > > index 00..6bc5cb358e > > --- /dev/null > > +++ > > > b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSyst > emD > > xe.inf > > @@ -0,0 +1,53 @@ > > +## @file > > +# > > +# (C) Copyright 2020-2022 Hewlett Packard Enterprise Development > LP > > +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights > reserved. > > +# > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > +# > > +## > > + > > + > > +[Defines] > > + INF_VERSION = 0x00010005 > > + BASE_NAME = ComputerSystemDxe > > + FILE_GUID = D94362A1-C358-4059-B014-F07D1AE04F16 > > + MODULE_TYPE = DXE_DRIVER > > + VERSION_STRING= 1.0 > > + ENTRY_POINT = RedfishResourceEntryPoint > > + UNLOAD_IMAGE = RedfishResourceUnload > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + MdeModulePkg/MdeModulePkg.dec > > + RedfishPkg/RedfishPkg.dec > > + RedfishClientPkg/RedfishClientPkg.dec > > + > > +[Sources] > > + ../Common/ComputerSystemCommon.h > > + ../Common/ComputerSystemCommon.c > > + ComputerSystemDxe.c > > + > > +[LibraryClasses] > > + BaseMemoryLib > > + DebugLib > > + EdkIIRedfishResourceConfigLib > > + RedfishLib > > + RedfishFeatureUtilityLib > > + RedfishResourceIdentifyLib > > + UefiLib > > + UefiDriverEntryPoint > > + RedfishAddendumLib > > + RedfishHttpCacheLib > > + > > +[Protocols] > > + gEdkIIRedfishConfigHandlerProtocolGuid ## PRODUCED > > + gEfiRestJsonStructureProtocolGuid ## CONSUMED > > + gEdkIIRedfishResourceConfigProtocolGuid ## PRODUCED > > + > > +[Pcd] > > + gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaStringSize > > + gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaVersionSize > > + > > +[Depex] > > + TRUE > > diff --git > > > a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/Compute > rSyst > > emCommon.h > > > b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/Compute > rSyst > > emCommon.h > > new file mode 100644 > > index 00..c9c8512881 > > --- /dev/null > > +++ > > > b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/Compute > rSyst > > emCommon.h > > @@ -0,0 +1,29 @@ > > +/** @file > > + > > + Redfish feature driver implementation - internal header file > > + (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP > > + Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights > > reserved. > > + > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef
[edk2-devel] [edk2-redfish-client][PATCH V3] RedfishClientPkg/FeatureDriver: ComputerSystem_1_13_0 driver
From: Abner Chang
Initial version of edk2 Redfish feature of
Redfish schema ComputerSystem_1_13_0. This driver
handles ComputerSystem Boot properties but not all.
Signed-off-by: Abner Chang
Cc: Nickle Wang
Cc: Igor Kulchytskyy
---
.../v1_13_0/Dxe/ComputerSystemDxe.inf | 53 ++
.../v1_13_0/Common/ComputerSystemCommon.h | 29 +
.../v1_13_0/Common/ComputerSystemCommon.c | 899 ++
.../v1_13_0/Dxe/ComputerSystemDxe.c | 702 ++
4 files changed, 1683 insertions(+)
create mode 100644
RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.inf
create mode 100644
RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.h
create mode 100644
RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.c
create mode 100644
RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.c
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.inf
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.inf
new file mode 100644
index 00..be1c2164d8
--- /dev/null
+++ b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.inf
@@ -0,0 +1,53 @@
+## @file
+#
+# (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ComputerSystemDxe
+ FILE_GUID = D94362A1-C358-4059-B014-F07D1AE04F16
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING= 1.0
+ ENTRY_POINT = RedfishResourceEntryPoint
+ UNLOAD_IMAGE = RedfishResourceUnload
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RedfishPkg/RedfishPkg.dec
+ RedfishClientPkg/RedfishClientPkg.dec
+
+[Sources]
+ ../Common/ComputerSystemCommon.h
+ ../Common/ComputerSystemCommon.c
+ ComputerSystemDxe.c
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ EdkIIRedfishResourceConfigLib
+ RedfishLib
+ RedfishFeatureUtilityLib
+ RedfishResourceIdentifyLib
+ UefiLib
+ UefiDriverEntryPoint
+ RedfishAddendumLib
+ RedfishHttpCacheLib
+
+[Protocols]
+ gEdkIIRedfishConfigHandlerProtocolGuid ## PRODUCED
+ gEfiRestJsonStructureProtocolGuid ## CONSUMED
+ gEdkIIRedfishResourceConfigProtocolGuid ## PRODUCED
+
+[Pcd]
+ gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaStringSize
+ gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaVersionSize
+
+[Depex]
+ TRUE
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.h
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.h
new file mode 100644
index 00..7b83d2939c
--- /dev/null
+++
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.h
@@ -0,0 +1,29 @@
+/** @file
+
+ Redfish feature driver implementation - internal header file
+ (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EFI_REDFISH_COMPUTERSYSTEM_COMMON_H_
+#define EFI_REDFISH_COMPUTERSYSTEM_COMMON_H_
+
+#include
+#include
+
+//
+// Schema information.
+//
+#define RESOURCE_SCHEMA "ComputerSystem"
+#define RESOURCE_SCHEMA_MAJOR"1"
+#define RESOURCE_SCHEMA_MINOR"13"
+#define RESOURCE_SCHEMA_ERRATA "0"
+#define RESOURCE_SCHEMA_VERSION "v1_13_0"
+#define REDPATH_ARRAY_PATTERNL"/Systems/\\{.*\\}/"
+#define REDPATH_ARRAY_PREFIX L"/Systems/"
+#define RESOURCE_SCHEMA_FULL "x-uefi-redfish-ComputerSystem.v1_13_0"
+
+#endif
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.c
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.c
new file mode 100644
index 00..cee6c8bf9b
--- /dev/null
+++
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.c
@@ -0,0 +1,899 @@
+/** @file
+ Redfish feature driver implementation - common functions
+
+ (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "ComputerSystemCommon.h"
+
+CHAR8 ComputerSystemEmptyJson[] = "{\"@odata.id\": \"\", \"@odata.type\":
\"#ComputerSystem.v1_13_0.ComputerSystem\", \"Id\": \"\", \"Name\": \"\",
\"Boot\":{}}";
+
+REDFISH_RESOURCE_COMMON_PRIVATE *mRedfishResourcePrivate = NULL;
+EFI_HANDLE mRedfishResourceConfigProtocolHandle = NULL;
+
+/**
+ Consume resource from given URI.
+
+ @param[in] This
[edk2-devel] [edk2-redfish-client][PATCH V2] RedfishClientPkg/FeatureDriver: ComputerSystem_1_5_0 driver
From: Abner Chang
Update Redfish ComputerSystem_1_5_0 feature
driver to align the implementation with latest
code. This driver handles all of ComputerSystem
v1_5_0 properties and incorporate with Redfish simualtor.
Signed-off-by: Abner Chang
Cc: Nickle Wang
Cc: Igor Kulchytskyy
---
.../v1_5_0/Dxe/ComputerSystemDxe.inf | 1 +
.../v1_5_0/Common/ComputerSystemCommon.c | 347 --
.../v1_5_0/Dxe/ComputerSystemDxe.c| 64 ++--
3 files changed, 271 insertions(+), 141 deletions(-)
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDxe.inf
b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDxe.inf
index 36cbe06211..4e7dc5c7c5 100644
--- a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDxe.inf
+++ b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDxe.inf
@@ -37,6 +37,7 @@
RedfishResourceIdentifyLib
UefiLib
UefiDriverEntryPoint
+ RedfishAddendumLib
RedfishHttpCacheLib
[Protocols]
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSystemCommon.c
b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSystemCommon.c
index 3ace03bd4c..a67ef3dac2 100644
---
a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSystemCommon.c
+++
b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSystemCommon.c
@@ -53,7 +53,7 @@ RedfishConsumeResourceCommon (
(EFI_REST_JSON_STRUCTURE_HEADER
**)
);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, ToStructure() failed: %r\n", __func__, Status));
+DEBUG ((DEBUG_ERROR, "%a: ToStructure() failed: %r\n", __func__, Status));
return Status;
}
@@ -66,8 +66,8 @@ RedfishConsumeResourceCommon (
//
// No change
//
-DEBUG ((DEBUG_MANAGEABILITY, "%a, ETAG: %s has no change, ignore consume
action\n", __func__, Private->Uri));
-Status = EFI_ALREADY_STARTED;
+DEBUG ((DEBUG_MANAGEABILITY, "%a: ETAG: %s has no change, ignore consume
action\n", __func__, Private->Uri));
+Status = EFI_SUCCESS;
goto ON_RELEASE;
}
@@ -154,12 +154,12 @@ RedfishConsumeResourceCommon (
if (ConfigureLang != NULL) {
Status = ApplyFeatureSettingsStringArrayType (RESOURCE_SCHEMA,
RESOURCE_SCHEMA_VERSION, ConfigureLang, ComputerSystemCs->Boot->BootOrder);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
+DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
}
FreePool (ConfigureLang);
} else {
- DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI: %s\n",
__func__, Private->Uri));
+ DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI: %s\n",
__func__, Private->Uri));
}
}
@@ -174,12 +174,12 @@ RedfishConsumeResourceCommon (
if (ConfigureLang != NULL) {
Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
RESOURCE_SCHEMA_VERSION, ConfigureLang,
ComputerSystemCs->Boot->BootSourceOverrideEnabled);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
+DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
}
FreePool (ConfigureLang);
} else {
- DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI: %s\n",
__func__, Private->Uri));
+ DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI: %s\n",
__func__, Private->Uri));
}
}
@@ -194,12 +194,12 @@ RedfishConsumeResourceCommon (
if (ConfigureLang != NULL) {
Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
RESOURCE_SCHEMA_VERSION, ConfigureLang,
ComputerSystemCs->Boot->BootSourceOverrideMode);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
+DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
}
FreePool (ConfigureLang);
} else {
- DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI: %s\n",
__func__, Private->Uri));
+ DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI: %s\n",
__func__, Private->Uri));
}
}
@@ -234,12 +234,12 @@ RedfishConsumeResourceCommon (
if (ConfigureLang != NULL) {
Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
RESOURCE_SCHEMA_VERSION, ConfigureLang,
ComputerSystemCs->Boot->UefiTargetBootSourceOverride);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
+DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
Re: [edk2-devel] [edk2-redfish-client][PATCH V2] RedfishClientPkg/FeatureDriver: ComputerSystem_1_13_0 driver
Hi Abner,
Same minor issue as 1_5_0. Please add "%a:" to below DEBUG call.
> + DEBUG ((DEBUG_MANAGEABILITY, " No platform Redfish ConfigureLang
> found for %s\n", __func__, Private->Uri));
Regards,
Nickle
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Chang, Abner
> via groups.io
> Sent: Friday, January 26, 2024 9:00 AM
> To: devel@edk2.groups.io
> Cc: Nickle Wang ; Igor Kulchytskyy
> Subject: [edk2-devel] [edk2-redfish-client][PATCH V2]
> RedfishClientPkg/FeatureDriver: ComputerSystem_1_13_0 driver
>
> External email: Use caution opening links or attachments
>
>
> From: Abner Chang
>
> Initial version of edk2 Redfish feature of
> Redfish schema ComputerSystem_1_13_0. This driver
> handles ComputerSystem Boot properties but not all.
>
> Signed-off-by: Abner Chang
> Cc: Nickle Wang
> Cc: Igor Kulchytskyy
> ---
> .../v1_13_0/Dxe/ComputerSystemDxe.inf | 53 ++
> .../v1_13_0/Common/ComputerSystemCommon.h | 29 +
> .../v1_13_0/Common/ComputerSystemCommon.c | 899
> ++
> .../v1_13_0/Dxe/ComputerSystemDxe.c | 702 ++
> 4 files changed, 1683 insertions(+)
> create mode 100644
> RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.
> inf
> create mode 100644
> RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyste
> mCommon.h
> create mode 100644
> RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyste
> mCommon.c
> create mode 100644
> RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.
> c
>
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemD
> xe.inf
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemD
> xe.inf
> new file mode 100644
> index 00..6bc5cb358e
> --- /dev/null
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemD
> xe.inf
> @@ -0,0 +1,53 @@
> +## @file
> +#
> +# (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
> +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = ComputerSystemDxe
> + FILE_GUID = D94362A1-C358-4059-B014-F07D1AE04F16
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING= 1.0
> + ENTRY_POINT = RedfishResourceEntryPoint
> + UNLOAD_IMAGE = RedfishResourceUnload
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + RedfishPkg/RedfishPkg.dec
> + RedfishClientPkg/RedfishClientPkg.dec
> +
> +[Sources]
> + ../Common/ComputerSystemCommon.h
> + ../Common/ComputerSystemCommon.c
> + ComputerSystemDxe.c
> +
> +[LibraryClasses]
> + BaseMemoryLib
> + DebugLib
> + EdkIIRedfishResourceConfigLib
> + RedfishLib
> + RedfishFeatureUtilityLib
> + RedfishResourceIdentifyLib
> + UefiLib
> + UefiDriverEntryPoint
> + RedfishAddendumLib
> + RedfishHttpCacheLib
> +
> +[Protocols]
> + gEdkIIRedfishConfigHandlerProtocolGuid ## PRODUCED
> + gEfiRestJsonStructureProtocolGuid ## CONSUMED
> + gEdkIIRedfishResourceConfigProtocolGuid ## PRODUCED
> +
> +[Pcd]
> + gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaStringSize
> + gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaVersionSize
> +
> +[Depex]
> + TRUE
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.h
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.h
> new file mode 100644
> index 00..c9c8512881
> --- /dev/null
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.h
> @@ -0,0 +1,29 @@
> +/** @file
> +
> + Redfish feature driver implementation - internal header file
> + (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
> + Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights
> reserved.
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef EFI_REDFISH_COMPUTERSYSTEM_COMMON_H_
> +#define EFI_REDFISH_COMPUTERSYSTEM_COMMON_H_
> +
> +#include
> >
> +#include
> +
> +//
> +// Schema information.
> +//
> +#define RESOURCE_SCHEMA "ComputerSystem"
> +#define RESOURCE_SCHEMA_MAJOR"1"
> +#define RESOURCE_SCHEMA_MINOR"13"
> +#define RESOURCE_SCHEMA_ERRATA "0"
> +#define RESOURCE_SCHEMA_VERSION "v1_13_0"
> +#define REDPATH_ARRAY_PATTERNL"/Systems/\\{.*\\}/"
> +#define REDPATH_ARRAY_PREFIX L"/Systems/"
> +#define RESOURCE_SCHEMA_FULL "x-uefi-redfish-
> ComputerSystem.v1_13_0"
> +
> +#endif
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.c
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.c
> new file mode 100644
> index 00..bc24c49206
> --- /dev/null
>
Re: [edk2-devel] [edk2-redfish-client][PATCH] RedfishClientPkg/FeatureDriver: ComputerSystem_1_5_0 driver
Hi Abner,
I found one minor issue:
> if (ConfigLangList.Count == 0) {
> + DEBUG ((DEBUG_MANAGEABILITY, " No platform Redfish ConfigureLang
> + found for %s\n", __func__, Private->Uri));
>return EFI_SUCCESS;
"%a:" is missing above.
Regards,
Nickle
> -Original Message-
> From: abner.ch...@amd.com
> Sent: Friday, January 26, 2024 9:15 AM
> To: devel@edk2.groups.io
> Cc: Nickle Wang ; Igor Kulchytskyy
> Subject: [edk2-redfish-client][PATCH] RedfishClientPkg/FeatureDriver:
> ComputerSystem_1_5_0 driver
>
> External email: Use caution opening links or attachments
>
>
> From: Abner Chang
>
> Update Redfish ComputerSystem_1_5_0 feature driver to align the
> implementation with latest code. This driver handles all of ComputerSystem
> v1_5_0 properties and incorporate with Redfish simualtor.
>
> Signed-off-by: Abner Chang
> Cc: Nickle Wang
> Cc: Igor Kulchytskyy
> ---
> .../v1_5_0/Dxe/ComputerSystemDxe.inf | 1 +
> .../v1_5_0/Common/ComputerSystemCommon.c | 347 --
> .../v1_5_0/Dxe/ComputerSystemDxe.c| 64 ++--
> 3 files changed, 271 insertions(+), 141 deletions(-)
>
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDx
> e.inf
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDx
> e.inf
> index 36cbe06211..4e7dc5c7c5 100644
> ---
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDx
> e.inf
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystem
> +++ Dxe.inf
> @@ -37,6 +37,7 @@
>RedfishResourceIdentifyLib
>UefiLib
>UefiDriverEntryPoint
> + RedfishAddendumLib
>RedfishHttpCacheLib
>
> [Protocols]
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSyste
> mCommon.c
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSyste
> mCommon.c
> index 3ace03bd4c..7cd2a6f378 100644
> ---
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSyste
> mCommon.c
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSys
> +++ temCommon.c
> @@ -53,7 +53,7 @@ RedfishConsumeResourceCommon (
>(EFI_REST_JSON_STRUCTURE_HEADER
> **)
>);
>if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_ERROR, "%a, ToStructure() failed: %r\n", __func__,
> Status));
> +DEBUG ((DEBUG_ERROR, "%a: ToStructure() failed: %r\n", __func__,
> + Status));
> return Status;
>}
>
> @@ -66,8 +66,8 @@ RedfishConsumeResourceCommon (
> //
> // No change
> //
> -DEBUG ((DEBUG_MANAGEABILITY, "%a, ETAG: %s has no change, ignore
> consume action\n", __func__, Private->Uri));
> -Status = EFI_ALREADY_STARTED;
> +DEBUG ((DEBUG_MANAGEABILITY, "%a: ETAG: %s has no change, ignore
> consume action\n", __func__, Private->Uri));
> +Status = EFI_SUCCESS;
> goto ON_RELEASE;
>}
>
> @@ -154,12 +154,12 @@ RedfishConsumeResourceCommon (
> if (ConfigureLang != NULL) {
>Status = ApplyFeatureSettingsStringArrayType (RESOURCE_SCHEMA,
> RESOURCE_SCHEMA_VERSION, ConfigureLang, ComputerSystemCs->Boot-
> >BootOrder);
>if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
> __func__,
> ConfigureLang, Status));
> +DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
> + __func__, ConfigureLang, Status));
>}
>
>FreePool (ConfigureLang);
> } else {
> - DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI:
> %s\n",
> __func__, Private->Uri));
> + DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI:
> + %s\n", __func__, Private->Uri));
> }
>}
>
> @@ -174,12 +174,12 @@ RedfishConsumeResourceCommon (
> if (ConfigureLang != NULL) {
>Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
> RESOURCE_SCHEMA_VERSION, ConfigureLang, ComputerSystemCs->Boot-
> >BootSourceOverrideEnabled);
>if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
> __func__,
> ConfigureLang, Status));
> +DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
> + __func__, ConfigureLang, Status));
>}
>
>FreePool (ConfigureLang);
> } else {
> - DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI:
> %s\n",
> __func__, Private->Uri));
> + DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI:
> + %s\n", __func__, Private->Uri));
> }
>}
>
> @@ -194,12 +194,12 @@ RedfishConsumeResourceCommon (
> if (ConfigureLang != NULL) {
>Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
> RESOURCE_SCHEMA_VERSION, ConfigureLang, ComputerSystemCs->Boot-
> >BootSourceOverrideMode);
>if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
> __func__,
> ConfigureLang,
Re: [edk2-devel] [PATCH] MdeModulePkg/SMM: Support to unregister SMI handler inside SMI handler
> Sounds safe enough. I don't know if it conforms to the spec however > (although we might just choose not to care about that). Should be compliant to spec. Or I should say spec does not under which case the Unregister() should succeed. As long as spec allows Unregister() returns a failure status, a very low-quality MmCore could always return failure from Unregister(). Our choice here is to return failure for a special case only (Unregister handler B in handler A). > > Laszlo -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114483): https://edk2.groups.io/g/devel/message/114483 Mute This Topic: https://groups.io/mt/103925794/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/9847357/21656/1706620634/xyzzy [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-redfish-client][PATCH] RedfishClientPkg/FeatureDriver: ComputerSystem_1_5_0 driver
From: Abner Chang
Update Redfish ComputerSystem_1_5_0 feature
driver to align the implementation with latest
code. This driver handles all of ComputerSystem
v1_5_0 properties and incorporate with Redfish simualtor.
Signed-off-by: Abner Chang
Cc: Nickle Wang
Cc: Igor Kulchytskyy
---
.../v1_5_0/Dxe/ComputerSystemDxe.inf | 1 +
.../v1_5_0/Common/ComputerSystemCommon.c | 347 --
.../v1_5_0/Dxe/ComputerSystemDxe.c| 64 ++--
3 files changed, 271 insertions(+), 141 deletions(-)
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDxe.inf
b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDxe.inf
index 36cbe06211..4e7dc5c7c5 100644
--- a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDxe.inf
+++ b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Dxe/ComputerSystemDxe.inf
@@ -37,6 +37,7 @@
RedfishResourceIdentifyLib
UefiLib
UefiDriverEntryPoint
+ RedfishAddendumLib
RedfishHttpCacheLib
[Protocols]
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSystemCommon.c
b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSystemCommon.c
index 3ace03bd4c..7cd2a6f378 100644
---
a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSystemCommon.c
+++
b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSystemCommon.c
@@ -53,7 +53,7 @@ RedfishConsumeResourceCommon (
(EFI_REST_JSON_STRUCTURE_HEADER
**)
);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, ToStructure() failed: %r\n", __func__, Status));
+DEBUG ((DEBUG_ERROR, "%a: ToStructure() failed: %r\n", __func__, Status));
return Status;
}
@@ -66,8 +66,8 @@ RedfishConsumeResourceCommon (
//
// No change
//
-DEBUG ((DEBUG_MANAGEABILITY, "%a, ETAG: %s has no change, ignore consume
action\n", __func__, Private->Uri));
-Status = EFI_ALREADY_STARTED;
+DEBUG ((DEBUG_MANAGEABILITY, "%a: ETAG: %s has no change, ignore consume
action\n", __func__, Private->Uri));
+Status = EFI_SUCCESS;
goto ON_RELEASE;
}
@@ -154,12 +154,12 @@ RedfishConsumeResourceCommon (
if (ConfigureLang != NULL) {
Status = ApplyFeatureSettingsStringArrayType (RESOURCE_SCHEMA,
RESOURCE_SCHEMA_VERSION, ConfigureLang, ComputerSystemCs->Boot->BootOrder);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
+DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
}
FreePool (ConfigureLang);
} else {
- DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI: %s\n",
__func__, Private->Uri));
+ DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI: %s\n",
__func__, Private->Uri));
}
}
@@ -174,12 +174,12 @@ RedfishConsumeResourceCommon (
if (ConfigureLang != NULL) {
Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
RESOURCE_SCHEMA_VERSION, ConfigureLang,
ComputerSystemCs->Boot->BootSourceOverrideEnabled);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
+DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
}
FreePool (ConfigureLang);
} else {
- DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI: %s\n",
__func__, Private->Uri));
+ DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI: %s\n",
__func__, Private->Uri));
}
}
@@ -194,12 +194,12 @@ RedfishConsumeResourceCommon (
if (ConfigureLang != NULL) {
Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
RESOURCE_SCHEMA_VERSION, ConfigureLang,
ComputerSystemCs->Boot->BootSourceOverrideMode);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
+DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
}
FreePool (ConfigureLang);
} else {
- DEBUG ((DEBUG_ERROR, "%a, can not get configure language for URI: %s\n",
__func__, Private->Uri));
+ DEBUG ((DEBUG_ERROR, "%a: can not get configure language for URI: %s\n",
__func__, Private->Uri));
}
}
@@ -234,12 +234,12 @@ RedfishConsumeResourceCommon (
if (ConfigureLang != NULL) {
Status = ApplyFeatureSettingsStringType (RESOURCE_SCHEMA,
RESOURCE_SCHEMA_VERSION, ConfigureLang,
ComputerSystemCs->Boot->UefiTargetBootSourceOverride);
if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "%a, apply setting for %s failed: %r\n",
__func__, ConfigureLang, Status));
+DEBUG ((DEBUG_ERROR, "%a: apply setting for %s failed: %r\n",
[edk2-devel] [edk2-redfish-client][PATCH V2] RedfishClientPkg/FeatureDriver: ComputerSystem_1_13_0 driver
From: Abner Chang
Initial version of edk2 Redfish feature of
Redfish schema ComputerSystem_1_13_0. This driver
handles ComputerSystem Boot properties but not all.
Signed-off-by: Abner Chang
Cc: Nickle Wang
Cc: Igor Kulchytskyy
---
.../v1_13_0/Dxe/ComputerSystemDxe.inf | 53 ++
.../v1_13_0/Common/ComputerSystemCommon.h | 29 +
.../v1_13_0/Common/ComputerSystemCommon.c | 899 ++
.../v1_13_0/Dxe/ComputerSystemDxe.c | 702 ++
4 files changed, 1683 insertions(+)
create mode 100644
RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.inf
create mode 100644
RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.h
create mode 100644
RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.c
create mode 100644
RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.c
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.inf
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.inf
new file mode 100644
index 00..6bc5cb358e
--- /dev/null
+++ b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Dxe/ComputerSystemDxe.inf
@@ -0,0 +1,53 @@
+## @file
+#
+# (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ComputerSystemDxe
+ FILE_GUID = D94362A1-C358-4059-B014-F07D1AE04F16
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING= 1.0
+ ENTRY_POINT = RedfishResourceEntryPoint
+ UNLOAD_IMAGE = RedfishResourceUnload
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RedfishPkg/RedfishPkg.dec
+ RedfishClientPkg/RedfishClientPkg.dec
+
+[Sources]
+ ../Common/ComputerSystemCommon.h
+ ../Common/ComputerSystemCommon.c
+ ComputerSystemDxe.c
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ EdkIIRedfishResourceConfigLib
+ RedfishLib
+ RedfishFeatureUtilityLib
+ RedfishResourceIdentifyLib
+ UefiLib
+ UefiDriverEntryPoint
+ RedfishAddendumLib
+ RedfishHttpCacheLib
+
+[Protocols]
+ gEdkIIRedfishConfigHandlerProtocolGuid ## PRODUCED
+ gEfiRestJsonStructureProtocolGuid ## CONSUMED
+ gEdkIIRedfishResourceConfigProtocolGuid ## PRODUCED
+
+[Pcd]
+ gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaStringSize
+ gEfiRedfishClientPkgTokenSpaceGuid.PcdMaxRedfishSchemaVersionSize
+
+[Depex]
+ TRUE
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.h
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.h
new file mode 100644
index 00..c9c8512881
--- /dev/null
+++
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.h
@@ -0,0 +1,29 @@
+/** @file
+
+ Redfish feature driver implementation - internal header file
+ (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EFI_REDFISH_COMPUTERSYSTEM_COMMON_H_
+#define EFI_REDFISH_COMPUTERSYSTEM_COMMON_H_
+
+#include
+#include
+
+//
+// Schema information.
+//
+#define RESOURCE_SCHEMA "ComputerSystem"
+#define RESOURCE_SCHEMA_MAJOR"1"
+#define RESOURCE_SCHEMA_MINOR"13"
+#define RESOURCE_SCHEMA_ERRATA "0"
+#define RESOURCE_SCHEMA_VERSION "v1_13_0"
+#define REDPATH_ARRAY_PATTERNL"/Systems/\\{.*\\}/"
+#define REDPATH_ARRAY_PREFIX L"/Systems/"
+#define RESOURCE_SCHEMA_FULL "x-uefi-redfish-ComputerSystem.v1_13_0"
+
+#endif
diff --git
a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.c
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.c
new file mode 100644
index 00..bc24c49206
--- /dev/null
+++
b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSystemCommon.c
@@ -0,0 +1,899 @@
+/** @file
+ Redfish feature driver implementation - common functions
+
+ (C) Copyright 2020-2022 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "ComputerSystemCommon.h"
+
+CHAR8 ComputerSystemEmptyJson[] = "{\"@odata.id\": \"\", \"@odata.type\":
\"#ComputerSystem.v1_13_0.ComputerSystem\", \"Id\": \"\", \"Name\": \"\",
\"Boot\":{}}";
+
+REDFISH_RESOURCE_COMMON_PRIVATE *mRedfishResourcePrivate = NULL;
+EFI_HANDLE mRedfishResourceConfigProtocolHandle = NULL;
+
+/**
+ Consume resource from given URI.
+
+ @param[in] This
Re: [edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
Looks good to me. Please get RB by atleast one of the Pkg maintainers.
With that:
Reviewed-by: Sai Chaganty
-Original Message-
From: Kuo, Ted
Sent: Tuesday, January 2, 2024 1:41 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel
; Desimone, Nathaniel L
; Dong, Eric ; S, Ashraf
Ali ; Duggapu, Chinni B ;
Gao, Liming
Subject: [edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support
SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common files to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
...pWrapperPlatformSecLibResetVectorInFsp.inf | 101 +
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 +--
.../X64/PeiCoreEntry.nasm | 202 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 +++
.../Ia32 => Include}/Fsp.h| 6 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 17 +-
12 files changed, 565 insertions(+), 34 deletions(-) create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (79%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..24c18f25b8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file -Copyright (c) 2017, Intel Corporation. All rights
reserved.+Copyright (c) 2017 - 2024, Intel Corporation. All rights
reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6 +10,7
@@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1) +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1 /** Fsp T
Core UPD **/ typedef struct {@@ -34,6 +35,28 @@ typedef struct {
**/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#else+/** Fsp
T Core UPD+**/+typedef struct {++/** Offset 0x0040+**/+ EFI_PHYSICAL_ADDRESS
MicrocodeRegionBase;++/** Offset 0x0048+**/+ UINT64
MicrocodeRegionSize;++/** Offset 0x0050+**/+ EFI_PHYSICAL_ADDRESS
CodeRegionBase;++/** Offset 0x0058+**/+ UINT64
CodeRegionSize;+} FSPT_CORE_UPD;+#endif #pragma pack() diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..0b3f343991 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;-; Copyright (c) 2019, Intel Corporation. All rights reserved.+; Copyright
(c) 2019 - 2024, Intel Corporation. All rights reserved. ;
SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"+#include SECTION .text diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..6806e000ce 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++
Re: [edk2-devel] [PATCH v2 1/4] OvmfPkg/Sec: Setup MTRR early in the boot process.
On 1/25/24 11:52, Pedro Falcato wrote: > On Thu, Jan 25, 2024 at 8:23 AM Gerd Hoffmann wrote: >> >> Specifically before running lzma uncompress of the main firmware volume. >> This is needed to make sure caching is enabled, otherwise the uncompress >> can be extremely slow. >> >> Adapt the ASSERTs and MTRR setup in PlatformInitLib to the changes. >> >> Background: Depending on virtual machine configuration kvm may uses EPT >> memory types to apply guest MTRR settings. In case MTRRs are disabled >> kvm will use the uncachable memory type for all mappings. Here is the >> linux kernel function handling this: > > It might not be wise to blat out GPLv2 source code in a commit message > :) Not that it's a violation of the GPL (we're not linking against it, > neither can the patch be considered a derivative work), but it might > just be a little too grey-area for a !GPL project. > I think you are right. How incredibly annoying. Perhaps we should replace the vmx_get_mt_mask() quote with a link like... https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/arch/x86/kvm/vmx/vmx.c?h=v6.7.1#n7580 This link (including a line number) is stable, because it references a tag. "all problems in computer science can be solved by another layer of indirection" https://en.wikipedia.org/wiki/David_Wheeler_(computer_scientist)#Quotes Funnily enough, Linus would yell at us for this; IIRC he strongly prefers embedding information over linking information, in commit messages. :/ Laszlo -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114479): https://edk2.groups.io/g/devel/message/114479 Mute This Topic: https://groups.io/mt/103950478/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/9847357/21656/1706620634/xyzzy [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 0/2] MdeModulePkg: 5-level paging fixes
On 1/25/24 09:20, Gerd Hoffmann wrote: > - rename PcdUse5LevelPageTable to PcdEnable5LevelPageTable > - relax 5-level paging assert > > Gerd Hoffmann (2): > MdeModulePkg: rename PcdUse5LevelPageTable to PcdEnable5LevelPageTable > MdeModulePkg/VirtualMemory: fix 5-level paging assert > > MdeModulePkg/MdeModulePkg.dec| 2 +- > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 2 +- > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 6 -- > MdeModulePkg/MdeModulePkg.uni| 4 ++-- > 4 files changed, 8 insertions(+), 6 deletions(-) > series Reviewed-by: Laszlo Ersek Feel free to keep the R-b if Ray suggests a different approach for the PCD renaming (e.g., keeping the existing name, or replacing "PcdGetBool (PcdUse5LevelPageTable)" with constant TRUE altogether) Laszlo -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114478): https://edk2.groups.io/g/devel/message/114478 Mute This Topic: https://groups.io/mt/103950405/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/9847357/21656/1706620634/xyzzy [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2 15/15] NetworkPkg: : Adds a SecurityFix.yaml file
This creates / adds a security file that tracks the security fixes found in this package and can be used to find the fixes that were applied. Cc: Saloni Kasbekar Cc: Zachary Clark-williams Signed-off-by: Doug Flick [MSFT] --- NetworkPkg/SecurityFixes.yaml | 123 ++ 1 file changed, 123 insertions(+) create mode 100644 NetworkPkg/SecurityFixes.yaml diff --git a/NetworkPkg/SecurityFixes.yaml b/NetworkPkg/SecurityFixes.yaml new file mode 100644 index ..7e900483fec5 --- /dev/null +++ b/NetworkPkg/SecurityFixes.yaml @@ -0,0 +1,123 @@ +## @file +# Security Fixes for SecurityPkg +# +# Copyright (c) Microsoft Corporation +# SPDX-License-Identifier: BSD-2-Clause-Patent +## +CVE_2023_45229: + commit_titles: +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45229 Patch" +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45229 Unit Tests" + cve: CVE-2023-45229 + date_reported: 2023-08-28 13:56 UTC + description: "Bug 01 - edk2/NetworkPkg: Out-of-bounds read when processing IA_NA/IA_TA options in a DHCPv6 Advertise message" + note: + files_impacted: +- NetworkPkg\Dhcp6Dxe\Dhcp6Io.c +- NetworkPkg\Dhcp6Dxe\Dhcp6Impl.h + links: +- https://bugzilla.tianocore.org/show_bug.cgi?id=4534 +- https://nvd.nist.gov/vuln/detail/CVE-2023-45229 +- http://www.openwall.com/lists/oss-security/2024/01/16/2 +- http://packetstormsecurity.com/files/176574/PixieFail-Proof-Of-Concepts.html +- https://blog.quarkslab.com/pixiefail-nine-vulnerabilities-in-tianocores-edk-ii-ipv6-network-stack.html +CVE_2023_45230: + commit_titles: +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45230 Patch" +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45230 Unit Tests" + cve: CVE-2023-45230 + date_reported: 2023-08-28 13:56 UTC + description: "Bug 02 - edk2/NetworkPkg: Buffer overflow in the DHCPv6 client via a long Server ID option" + note: + files_impacted: +- NetworkPkg\Dhcp6Dxe\Dhcp6Io.c +- NetworkPkg\Dhcp6Dxe\Dhcp6Impl.h + links: +- https://bugzilla.tianocore.org/show_bug.cgi?id=4535 +- https://nvd.nist.gov/vuln/detail/CVE-2023-45230 +- http://www.openwall.com/lists/oss-security/2024/01/16/2 +- http://packetstormsecurity.com/files/176574/PixieFail-Proof-Of-Concepts.html +- https://blog.quarkslab.com/pixiefail-nine-vulnerabilities-in-tianocores-edk-ii-ipv6-network-stack.html +CVE_2023_45231: + commit_titles: +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45231 Patch" +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45231 Unit Tests" + cve: CVE-2023-45231 + date_reported: 2023-08-28 13:56 UTC + description: "Bug 03 - edk2/NetworkPkg: Out-of-bounds read when handling a ND Redirect message with truncated options" + note: + files_impacted: +- NetworkPkg/Ip6Dxe/Ip6Option.c + links: +- https://bugzilla.tianocore.org/show_bug.cgi?id=4536 +- https://nvd.nist.gov/vuln/detail/CVE-2023-45231 +- http://www.openwall.com/lists/oss-security/2024/01/16/2 +- http://packetstormsecurity.com/files/176574/PixieFail-Proof-Of-Concepts.html +- https://blog.quarkslab.com/pixiefail-nine-vulnerabilities-in-tianocores-edk-ii-ipv6-network-stack.html +CVE_2023_45232: + commit_titles: +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45232 Patch" +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45232 Unit Tests" + cve: CVE-2023-45232 + date_reported: 2023-08-28 13:56 UTC + description: "Bug 04 - edk2/NetworkPkg: Infinite loop when parsing unknown options in the Destination Options header" + note: + files_impacted: +- NetworkPkg/Ip6Dxe/Ip6Option.c +- NetworkPkg/Ip6Dxe/Ip6Option.h + links: +- https://bugzilla.tianocore.org/show_bug.cgi?id=4537 +- https://nvd.nist.gov/vuln/detail/CVE-2023-45232 +- http://www.openwall.com/lists/oss-security/2024/01/16/2 +- http://packetstormsecurity.com/files/176574/PixieFail-Proof-Of-Concepts.html +- https://blog.quarkslab.com/pixiefail-nine-vulnerabilities-in-tianocores-edk-ii-ipv6-network-stack.html +CVE_2023_45233: + commit_titles: +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45232 Patch" +- "NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45232 Unit Tests" + cve: CVE-2023-45233 + date_reported: 2023-08-28 13:56 UTC + description: "Bug 05 - edk2/NetworkPkg: Infinite loop when parsing a PadN option in the Destination Options header " + note: This was fixed along with CVE-2023-45233 + files_impacted: +- NetworkPkg/Ip6Dxe/Ip6Option.c +- NetworkPkg/Ip6Dxe/Ip6Option.h + links: +- https://bugzilla.tianocore.org/show_bug.cgi?id=4538 +- https://nvd.nist.gov/vuln/detail/CVE-2023-45233 +- http://www.openwall.com/lists/oss-security/2024/01/16/2 +- http://packetstormsecurity.com/files/176574/PixieFail-Proof-Of-Concepts.html +- https://blog.quarkslab.com/pixiefail-nine-vulnerabilities-in-tianocores-edk-ii-ipv6-network-stack.html +CVE_2023_45234: + commit_titles: +- "NetworkPkg:
[edk2-devel] [PATCH v2 14/15] NetworkPkg: UefiPxeBcDxe: SECURITY PATCH CVE-2023-45235 Unit Tests
From: Doug Flick
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4540
Unit tests to confirm that the bug..
Buffer overflow when handling Server ID option from a DHCPv6 proxy
Advertise message
..has been patched.
This patch contains unit tests for the following functions:
PxeBcRequestBootService
PxeBcDhcp6Discover
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/Test/NetworkPkgHostTest.dsc| 5 +-
.../GoogleTest/PxeBcDhcp6GoogleTest.h | 18 ++
.../GoogleTest/PxeBcDhcp6GoogleTest.cpp | 278 +-
3 files changed, 298 insertions(+), 3 deletions(-)
diff --git a/NetworkPkg/Test/NetworkPkgHostTest.dsc
b/NetworkPkg/Test/NetworkPkgHostTest.dsc
index a0273c431025..fa301a7a52ab 100644
--- a/NetworkPkg/Test/NetworkPkgHostTest.dsc
+++ b/NetworkPkg/Test/NetworkPkgHostTest.dsc
@@ -27,7 +27,10 @@ [Components]
#
NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
- NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.inf
+ NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.inf {
+
+
UefiRuntimeServicesTableLib|MdePkg/Test/Mock/Library/GoogleTest/MockUefiRuntimeServicesTableLib/MockUefiRuntimeServicesTableLib.inf
+ }
# Despite these library classes being listed in [LibraryClasses] below, they
are not needed for the host-based unit tests.
[LibraryClasses]
diff --git a/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.h
b/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.h
index b17c314791c8..0d825e44250a 100644
--- a/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.h
+++ b/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.h
@@ -47,4 +47,22 @@ PxeBcCacheDnsServerAddresses (
IN PXEBC_DHCP6_PACKET_CACHE *Cache6
);
+/**
+ Build and send out the request packet for the bootfile, and parse the reply.
+
+ @param[in] Private The pointer to PxeBc private data.
+ @param[in] Index PxeBc option boot item type.
+
+ @retval EFI_SUCCESS Successfully discovered the boot file.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate resources.
+ @retval EFI_NOT_FOUND Can't get the PXE reply packet.
+ @retval OthersFailed to discover the boot file.
+
+**/
+EFI_STATUS
+PxeBcRequestBootService (
+ IN PXEBC_PRIVATE_DATA *Private,
+ IN UINT32 Index
+ );
+
#endif // PXE_BC_DHCP6_GOOGLE_TEST_H_
diff --git a/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.cpp
b/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.cpp
index 826050dc..bd423ebadfce 100644
--- a/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.cpp
+++ b/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.cpp
@@ -4,7 +4,9 @@
Copyright (c) Microsoft Corporation
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-#include
+#include
+#include
+#include
extern "C" {
#include
@@ -19,7 +21,8 @@ extern "C" {
// Definitions
///
-#define PACKET_SIZE (1500)
+#define PACKET_SIZE(1500)
+#define REQUEST_OPTION_LENGTH (120)
typedef struct {
UINT16OptionCode; // The option code for DHCP6_OPT_SERVER_ID (e.g.,
0x03)
@@ -76,6 +79,26 @@ MockConfigure (
}
// Needed by PxeBcSupport
+EFI_STATUS
+PxeBcDns6 (
+ IN PXEBC_PRIVATE_DATA *Private,
+ IN CHAR16 *HostName,
+ OUT EFI_IPv6_ADDRESS *IpAddress
+ )
+{
+ return EFI_SUCCESS;
+}
+
+UINT32
+PxeBcBuildDhcp6Options (
+ IN PXEBC_PRIVATE_DATA *Private,
+ OUT EFI_DHCP6_PACKET_OPTION **OptList,
+ IN UINT8*Buffer
+ )
+{
+ return EFI_SUCCESS;
+}
+
EFI_STATUS
EFIAPI
QueueDpc (
@@ -159,6 +182,10 @@ TEST_F (PxeBcHandleDhcp6OfferTest, BasicUsageTest) {
ASSERT_EQ (PxeBcHandleDhcp6Offer (&(PxeBcHandleDhcp6OfferTest::Private)),
EFI_DEVICE_ERROR);
}
+///
+// PxeBcCacheDnsServerAddresses Tests
+///
+
class PxeBcCacheDnsServerAddressesTest : public ::testing::Test {
public:
PXEBC_PRIVATE_DATA Private = { 0 };
@@ -298,3 +325,250 @@ TEST_F (PxeBcCacheDnsServerAddressesTest,
MultipleDnsEntries) {
FreePool (Private.DnsServer);
}
}
+
+///
+// PxeBcRequestBootServiceTest Test Cases
+///
+
+class PxeBcRequestBootServiceTest : public ::testing::Test {
+public:
+ PXEBC_PRIVATE_DATA Private = { 0 };
+ EFI_UDP6_PROTOCOL Udp6Read;
+
+protected:
+ // Add any setup code if needed
+ virtual void
+ SetUp (
+)
+ {
+Private.Dhcp6Request = (EFI_DHCP6_PACKET *)AllocateZeroPool (PACKET_SIZE);
+
+// Need to setup the
[edk2-devel] [PATCH v2 11/15] NetworkPkg: UefiPxeBcDxe: SECURITY PATCH CVE-2023-45234 Unit Tests
From: Doug Flick REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4539 Unit tests to that the bug.. Buffer overflow when processing DNS Servers option in a DHCPv6 Advertise message ..has been patched This contains tests for the following functions: PxeBcHandleDhcp6Offer PxeBcCacheDnsServerAddresses Cc: Saloni Kasbekar Cc: Zachary Clark-williams Signed-off-by: Doug Flick [MSFT] --- NetworkPkg/Test/NetworkPkgHostTest.dsc| 1 + .../GoogleTest/UefiPxeBcDxeGoogleTest.inf | 48 +++ .../GoogleTest/PxeBcDhcp6GoogleTest.h | 50 +++ .../GoogleTest/PxeBcDhcp6GoogleTest.cpp | 300 ++ .../GoogleTest/UefiPxeBcDxeGoogleTest.cpp | 19 ++ 5 files changed, 418 insertions(+) create mode 100644 NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.inf create mode 100644 NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.h create mode 100644 NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.cpp create mode 100644 NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.cpp diff --git a/NetworkPkg/Test/NetworkPkgHostTest.dsc b/NetworkPkg/Test/NetworkPkgHostTest.dsc index 7fa7b0f9d5be..a0273c431025 100644 --- a/NetworkPkg/Test/NetworkPkgHostTest.dsc +++ b/NetworkPkg/Test/NetworkPkgHostTest.dsc @@ -27,6 +27,7 @@ [Components] # NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf + NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.inf # Despite these library classes being listed in [LibraryClasses] below, they are not needed for the host-based unit tests. [LibraryClasses] diff --git a/NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.inf b/NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.inf new file mode 100644 index ..301dcdf61109 --- /dev/null +++ b/NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.inf @@ -0,0 +1,48 @@ +## @file +# Unit test suite for the UefiPxeBcDxe using Google Test +# +# Copyright (c) Microsoft Corporation. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## +[Defines] +INF_VERSION= 0x00010005 +BASE_NAME = UefiPxeBcDxeGoogleTest +FILE_GUID = 77D45C64-EC1E-4174-887B-886E89FD1EDF +MODULE_TYPE= HOST_APPLICATION +VERSION_STRING = 1.0 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + UefiPxeBcDxeGoogleTest.cpp + PxeBcDhcp6GoogleTest.cpp + PxeBcDhcp6GoogleTest.h + ../PxeBcDhcp6.c + ../PxeBcSupport.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec + NetworkPkg/NetworkPkg.dec + +[LibraryClasses] + GoogleTestLib + DebugLib + NetLib + PcdLib + +[Protocols] + gEfiDhcp6ServiceBindingProtocolGuid + gEfiDns6ServiceBindingProtocolGuid + gEfiDns6ProtocolGuid + +[Pcd] + gEfiNetworkPkgTokenSpaceGuid.PcdDhcp6UidType + +[Guids] + gZeroGuid diff --git a/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.h b/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.h new file mode 100644 index ..b17c314791c8 --- /dev/null +++ b/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.h @@ -0,0 +1,50 @@ +/** @file + This file exposes the internal interfaces which may be unit tested + for the PxeBcDhcp6Dxe driver. + + Copyright (c) Microsoft Corporation. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PXE_BC_DHCP6_GOOGLE_TEST_H_ +#define PXE_BC_DHCP6_GOOGLE_TEST_H_ + +// +// Minimal includes needed to compile +// +#include +#include "../PxeBcImpl.h" + +/** + Handle the DHCPv6 offer packet. + + @param[in] Private The pointer to PXEBC_PRIVATE_DATA. + + @retval EFI_SUCCESS Handled the DHCPv6 offer packet successfully. + @retval EFI_NO_RESPONSE No response to the following request packet. + @retval EFI_OUT_OF_RESOURCES Failed to allocate resources. + @retval EFI_BUFFER_TOO_SMALL Can't cache the offer pacet. + +**/ +EFI_STATUS +PxeBcHandleDhcp6Offer ( + IN PXEBC_PRIVATE_DATA *Private + ); + +/** + Cache the DHCPv6 Server address + + @param[in] Private The pointer to PXEBC_PRIVATE_DATA. + @param[in] Cache6The pointer to PXEBC_DHCP6_PACKET_CACHE. + + @retvalEFI_SUCCESS Cache the DHCPv6 Server address successfully. + @retvalEFI_OUT_OF_RESOURCES Failed to allocate resources. + @retvalEFI_DEVICE_ERROR Failed to cache the DHCPv6 Server address. +**/ +EFI_STATUS +PxeBcCacheDnsServerAddresses ( + IN PXEBC_PRIVATE_DATA*Private, + IN PXEBC_DHCP6_PACKET_CACHE *Cache6 + ); + +#endif // PXE_BC_DHCP6_GOOGLE_TEST_H_ diff --git a/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.cpp b/NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.cpp new file mode 100644 index ..826050dc --- /dev/null +++
[edk2-devel] [PATCH v2 13/15] NetworkPkg: UefiPxeBcDxe: SECURITY PATCH CVE-2023-45235 Patch
From: Doug Flick
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4540
Bug Details:
PixieFail Bug #7
CVE-2023-45235
CVSS 8.3 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:L/A:H
CWE-119 Improper Restriction of Operations within the Bounds of
a Memory Buffer
Buffer overflow when handling Server ID option from a DHCPv6 proxy
Advertise message
Change Overview:
Performs two checks
1. Checks that the length of the duid is accurate
> + //
> + // Check that the minimum and maximum requirements are met
> + //
> + if ((OpLen < PXEBC_MIN_SIZE_OF_DUID) ||
(OpLen > PXEBC_MAX_SIZE_OF_DUID)) {
> + Status = EFI_INVALID_PARAMETER;
> + goto ON_ERROR;
> + }
2. Ensures that the amount of data written to the buffer is tracked and
never exceeds that
> + //
> + // Check that the option length is valid.
> + //
> + if ((DiscoverLen + OpLen + PXEBC_COMBINED_SIZE_OF_OPT_CODE_AND_LEN)
> DiscoverLenNeeded) {
> + Status = EFI_OUT_OF_RESOURCES;
> + goto ON_ERROR;
> + }
Additional code clean up and fix for memory leak in case Option was NULL
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.h | 17 ++
NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c | 77 ++--
2 files changed, 78 insertions(+), 16 deletions(-)
diff --git a/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.h
b/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.h
index c86f6d391b80..6357d27faefd 100644
--- a/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.h
+++ b/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.h
@@ -34,6 +34,23 @@
#define PXEBC_ADDR_START_DELIMITER'['
#define PXEBC_ADDR_END_DELIMITER ']'
+//
+// A DUID consists of a 2-octet type code represented in network byte
+// order, followed by a variable number of octets that make up the
+// actual identifier. The length of the DUID (not including the type
+// code) is at least 1 octet and at most 128 octets.
+//
+#define PXEBC_MIN_SIZE_OF_DUID (sizeof(UINT16) + 1)
+#define PXEBC_MAX_SIZE_OF_DUID (sizeof(UINT16) + 128)
+
+//
+// This define represents the combineds code and length field from
+// https://datatracker.ietf.org/doc/html/rfc3315#section-22.1
+//
+#define PXEBC_COMBINED_SIZE_OF_OPT_CODE_AND_LEN \
+ (sizeof (((EFI_DHCP6_PACKET_OPTION *)0)->OpCode) + \
+ sizeof (((EFI_DHCP6_PACKET_OPTION *)0)->OpLen))
+
#define GET_NEXT_DHCP6_OPTION(Opt) \
(EFI_DHCP6_PACKET_OPTION *) ((UINT8 *) (Opt) + \
sizeof (EFI_DHCP6_PACKET_OPTION) + (NTOHS ((Opt)->OpLen)) - 1)
diff --git a/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c
b/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c
index 2b2d372889a3..7fd1281c1184 100644
--- a/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c
+++ b/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c
@@ -887,6 +887,7 @@ PxeBcRequestBootService (
EFI_STATUS Status;
EFI_DHCP6_PACKET *IndexOffer;
UINT8*Option;
+ UINTNDiscoverLenNeeded;
PxeBc = >PxeBc;
Request= Private->Dhcp6Request;
@@ -899,7 +900,8 @@ PxeBcRequestBootService (
return EFI_DEVICE_ERROR;
}
- Discover = AllocateZeroPool (sizeof (EFI_PXE_BASE_CODE_DHCPV6_PACKET));
+ DiscoverLenNeeded = sizeof (EFI_PXE_BASE_CODE_DHCPV6_PACKET);
+ Discover = AllocateZeroPool (DiscoverLenNeeded);
if (Discover == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -924,16 +926,34 @@ PxeBcRequestBootService (
DHCP6_OPT_SERVER_ID
);
if (Option == NULL) {
- return EFI_NOT_FOUND;
+ Status = EFI_NOT_FOUND;
+ goto ON_ERROR;
}
//
// Add Server ID Option.
//
OpLen = NTOHS (((EFI_DHCP6_PACKET_OPTION *)Option)->OpLen);
-CopyMem (DiscoverOpt, Option, OpLen + 4);
-DiscoverOpt += (OpLen + 4);
-DiscoverLen += (OpLen + 4);
+
+//
+// Check that the minimum and maximum requirements are met
+//
+if ((OpLen < PXEBC_MIN_SIZE_OF_DUID) || (OpLen > PXEBC_MAX_SIZE_OF_DUID)) {
+ Status = EFI_INVALID_PARAMETER;
+ goto ON_ERROR;
+}
+
+//
+// Check that the option length is valid.
+//
+if ((DiscoverLen + OpLen + PXEBC_COMBINED_SIZE_OF_OPT_CODE_AND_LEN) >
DiscoverLenNeeded) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto ON_ERROR;
+}
+
+CopyMem (DiscoverOpt, Option, OpLen +
PXEBC_COMBINED_SIZE_OF_OPT_CODE_AND_LEN);
+DiscoverOpt += (OpLen + PXEBC_COMBINED_SIZE_OF_OPT_CODE_AND_LEN);
+DiscoverLen += (OpLen + PXEBC_COMBINED_SIZE_OF_OPT_CODE_AND_LEN);
}
while (RequestLen < Request->Length) {
@@ -944,16 +964,24 @@ PxeBcRequestBootService (
(OpCode != DHCP6_OPT_SERVER_ID)
)
{
+ //
+ // Check that the option length is valid.
+ //
+ if (DiscoverLen + OpLen + PXEBC_COMBINED_SIZE_OF_OPT_CODE_AND_LEN >
DiscoverLenNeeded) {
+Status = EFI_OUT_OF_RESOURCES;
+goto ON_ERROR;
+ }
+
//
// Copy all the options except IA option and Server ID
//
- CopyMem
[edk2-devel] [PATCH v2 12/15] MdePkg: Test: Add gRT_GetTime Google Test Mock
This adds support for GetTime Google Test Mock
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Doug Flick [MSFT]
---
.../GoogleTest/Library/MockUefiRuntimeServicesTableLib.h | 7 +++
.../MockUefiRuntimeServicesTableLib.cpp| 5 +++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git
a/MdePkg/Test/Mock/Include/GoogleTest/Library/MockUefiRuntimeServicesTableLib.h
b/MdePkg/Test/Mock/Include/GoogleTest/Library/MockUefiRuntimeServicesTableLib.h
index 241abc55c079..bcc902cb93c2 100644
---
a/MdePkg/Test/Mock/Include/GoogleTest/Library/MockUefiRuntimeServicesTableLib.h
+++
b/MdePkg/Test/Mock/Include/GoogleTest/Library/MockUefiRuntimeServicesTableLib.h
@@ -37,6 +37,13 @@ struct MockUefiRuntimeServicesTableLib {
IN UINTN DataSize,
IN VOID *Data)
);
+
+ MOCK_FUNCTION_DECLARATION (
+EFI_STATUS,
+gRT_GetTime,
+(OUT EFI_TIME*Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL)
+);
};
#endif
diff --git
a/MdePkg/Test/Mock/Library/GoogleTest/MockUefiRuntimeServicesTableLib/MockUefiRuntimeServicesTableLib.cpp
b/MdePkg/Test/Mock/Library/GoogleTest/MockUefiRuntimeServicesTableLib/MockUefiRuntimeServicesTableLib.cpp
index 14296b0ccb88..8d2afd5dd63a 100644
---
a/MdePkg/Test/Mock/Library/GoogleTest/MockUefiRuntimeServicesTableLib/MockUefiRuntimeServicesTableLib.cpp
+++
b/MdePkg/Test/Mock/Library/GoogleTest/MockUefiRuntimeServicesTableLib/MockUefiRuntimeServicesTableLib.cpp
@@ -10,11 +10,12 @@ MOCK_INTERFACE_DEFINITION (MockUefiRuntimeServicesTableLib);
MOCK_FUNCTION_DEFINITION (MockUefiRuntimeServicesTableLib, gRT_GetVariable, 5,
EFIAPI);
MOCK_FUNCTION_DEFINITION (MockUefiRuntimeServicesTableLib, gRT_SetVariable, 5,
EFIAPI);
+MOCK_FUNCTION_DEFINITION (MockUefiRuntimeServicesTableLib, gRT_GetTime, 2,
EFIAPI);
static EFI_RUNTIME_SERVICES localRt = {
- { 0 }, // EFI_TABLE_HEADER
+ { 0 },// EFI_TABLE_HEADER
- NULL, // EFI_GET_TIME
+ gRT_GetTime, // EFI_GET_TIME
NULL, // EFI_SET_TIME
NULL, // EFI_GET_WAKEUP_TIME
NULL, // EFI_SET_WAKEUP_TIME
--
2.43.0
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[edk2-devel] [PATCH v2 10/15] NetworkPkg: UefiPxeBcDxe: SECURITY PATCH CVE-2023-45234 Patch
From: Doug Flick
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4539
Bug Details:
PixieFail Bug #6
CVE-2023-45234
CVSS 8.3 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:L/A:H
CWE-119 Improper Restriction of Operations within the Bounds of
a Memory Buffer
Buffer overflow when processing DNS Servers option in a DHCPv6
Advertise message
Change Overview:
Introduces a function to cache the Dns Server and perform sanitizing
on the incoming DnsServerLen to ensure that the length is valid
> + EFI_STATUS
> + PxeBcCacheDnsServerAddresses (
> + IN PXEBC_PRIVATE_DATA*Private,
> + IN PXEBC_DHCP6_PACKET_CACHE *Cache6
> + )
Additional code cleanup
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c | 71 +---
1 file changed, 65 insertions(+), 6 deletions(-)
diff --git a/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c
b/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c
index 425e0cf8061d..2b2d372889a3 100644
--- a/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c
+++ b/NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c
@@ -3,6 +3,7 @@
(C) Copyright 2014 Hewlett-Packard Development Company, L.P.
Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) Microsoft Corporation
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -1312,6 +1313,65 @@ PxeBcSelectDhcp6Offer (
}
}
+/**
+ Cache the DHCPv6 DNS Server addresses
+
+ @param[in] Private The pointer to PXEBC_PRIVATE_DATA.
+ @param[in] Cache6The pointer to PXEBC_DHCP6_PACKET_CACHE.
+
+ @retvalEFI_SUCCESS Cache the DHCPv6 DNS Server address
successfully.
+ @retvalEFI_OUT_OF_RESOURCES Failed to allocate resources.
+ @retvalEFI_DEVICE_ERROR The DNS Server Address Length provided by a
untrusted
+ option is not a multiple of 16 bytes
(sizeof (EFI_IPv6_ADDRESS)).
+**/
+EFI_STATUS
+PxeBcCacheDnsServerAddresses (
+ IN PXEBC_PRIVATE_DATA*Private,
+ IN PXEBC_DHCP6_PACKET_CACHE *Cache6
+ )
+{
+ UINT16 DnsServerLen;
+
+ DnsServerLen = NTOHS (Cache6->OptList[PXEBC_DHCP6_IDX_DNS_SERVER]->OpLen);
+ //
+ // Make sure that the number is nonzero
+ //
+ if (DnsServerLen == 0) {
+return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Make sure the DnsServerlen is a multiple of EFI_IPv6_ADDRESS (16)
+ //
+ if (DnsServerLen % sizeof (EFI_IPv6_ADDRESS) != 0) {
+return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // This code is currently written to only support a single DNS Server instead
+ // of multiple such as is spec defined (RFC3646, Section 3). The proper
behavior
+ // would be to allocate the full space requested, CopyMem all of the data,
+ // and then add a DnsServerCount field to Private and update additional code
+ // that depends on this.
+ //
+ // To support multiple DNS servers the `AllocationSize` would need to be
changed to DnsServerLen
+ //
+ // This is tracked in https://bugzilla.tianocore.org/show_bug.cgi?id=1886
+ //
+ Private->DnsServer = AllocateZeroPool (sizeof (EFI_IPv6_ADDRESS));
+ if (Private->DnsServer == NULL) {
+return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Intentionally only copy over the first server address.
+ // To support multiple DNS servers, the `Length` would need to be changed to
DnsServerLen
+ //
+ CopyMem (Private->DnsServer,
Cache6->OptList[PXEBC_DHCP6_IDX_DNS_SERVER]->Data, sizeof (EFI_IPv6_ADDRESS));
+
+ return EFI_SUCCESS;
+}
+
/**
Handle the DHCPv6 offer packet.
@@ -1335,6 +1395,7 @@ PxeBcHandleDhcp6Offer (
UINT32SelectIndex;
UINT32Index;
+ ASSERT (Private != NULL);
ASSERT (Private->SelectIndex > 0);
SelectIndex = (UINT32)(Private->SelectIndex - 1);
ASSERT (SelectIndex < PXEBC_OFFER_MAX_NUM);
@@ -1342,15 +1403,13 @@ PxeBcHandleDhcp6Offer (
Status = EFI_SUCCESS;
//
- // First try to cache DNS server address if DHCP6 offer provides.
+ // First try to cache DNS server addresses if DHCP6 offer provides.
//
if (Cache6->OptList[PXEBC_DHCP6_IDX_DNS_SERVER] != NULL) {
-Private->DnsServer = AllocateZeroPool (NTOHS
(Cache6->OptList[PXEBC_DHCP6_IDX_DNS_SERVER]->OpLen));
-if (Private->DnsServer == NULL) {
- return EFI_OUT_OF_RESOURCES;
+Status = PxeBcCacheDnsServerAddresses (Private, Cache6);
+if (EFI_ERROR (Status)) {
+ return Status;
}
-
-CopyMem (Private->DnsServer,
Cache6->OptList[PXEBC_DHCP6_IDX_DNS_SERVER]->Data, sizeof (EFI_IPv6_ADDRESS));
}
if (Cache6->OfferType == PxeOfferTypeDhcpBinl) {
--
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[edk2-devel] [PATCH v2 08/15] NetworkPkg: Ip6Dxe: SECURITY PATCH CVE-2023-45232 Patch
From: Doug Flick
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4537
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4538
Bug Details:
PixieFail Bug #4
CVE-2023-45232
CVSS 7.5 : CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:H
CWE-835 Loop with Unreachable Exit Condition ('Infinite Loop')
Infinite loop when parsing unknown options in the Destination Options
header
PixieFail Bug #5
CVE-2023-45233
CVSS 7.5 : CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:H
CWE-835 Loop with Unreachable Exit Condition ('Infinite Loop')
Infinite loop when parsing a PadN option in the Destination Options
header
Change Overview:
Most importantly this change corrects the following incorrect math
and cleans up the code.
> // It is a PadN option
> //
> - Offset = (UINT8)(Offset + *(Option + Offset + 1) + 2);
> + OptDataLen = ((EFI_IP6_OPTION *)(Option + Offset))->Length;
> + Offset = IP6_NEXT_OPTION_OFFSET (Offset, OptDataLen);
> case Ip6OptionSkip:
> - Offset = (UINT8)(Offset + *(Option + Offset + 1));
> OptDataLen = ((EFI_IP6_OPTION *)(Option + Offset))->Length;
> Offset = IP6_NEXT_OPTION_OFFSET (Offset, OptDataLen);
Additionally, this change also corrects incorrect math where the calling
function was calculating the HDR EXT optionLen as a uint8 instead of a
uint16
> - OptionLen = (UINT8)((*Option + 1) * 8 - 2);
> + OptionLen = IP6_HDR_EXT_LEN (*Option) -
IP6_COMBINED_SIZE_OF_NEXT_HDR_AND_LEN;
Additionally this check adds additional logic to santize the incoming
data
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/Ip6Dxe/Ip6Nd.h | 35
NetworkPkg/Ip6Dxe/Ip6Option.h | 71
NetworkPkg/Ip6Dxe/Ip6Option.c | 76 ++-
3 files changed, 171 insertions(+), 11 deletions(-)
diff --git a/NetworkPkg/Ip6Dxe/Ip6Nd.h b/NetworkPkg/Ip6Dxe/Ip6Nd.h
index 860934a167eb..bf64e9114e13 100644
--- a/NetworkPkg/Ip6Dxe/Ip6Nd.h
+++ b/NetworkPkg/Ip6Dxe/Ip6Nd.h
@@ -56,13 +56,48 @@ VOID
VOID *Context
);
+//
+// Per RFC8200 Section 4.2
+//
+// Two of the currently-defined extension headers -- the Hop-by-Hop
+// Options header and the Destination Options header -- carry a variable
+// number of type-length-value (TLV) encoded "options", of the following
+// format:
+//
+// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+- - - - - - - - -
+// | Option Type | Opt Data Len | Option Data
+// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+- - - - - - - - -
+//
+// Option Type 8-bit identifier of the type of option.
+//
+// Opt Data Len 8-bit unsigned integer. Length of the Option
+// Data field of this option, in octets.
+//
+// Option Data Variable-length field. Option-Type-specific
+// data.
+//
typedef struct _IP6_OPTION_HEADER {
+ ///
+ /// identifier of the type of option.
+ ///
UINT8Type;
+ ///
+ /// Length of the Option Data field of this option, in octets.
+ ///
UINT8Length;
+ ///
+ /// Option-Type-specific data.
+ ///
} IP6_OPTION_HEADER;
STATIC_ASSERT (sizeof (IP6_OPTION_HEADER) == 2, "IP6_OPTION_HEADER is expected
to be exactly 2 bytes long.");
+#define IP6_NEXT_OPTION_OFFSET(offset, length) (offset +
sizeof(IP6_OPTION_HEADER) + length)
+STATIC_ASSERT (
+ IP6_NEXT_OPTION_OFFSET (0, 0) == 2,
+ "The next option is minimally the combined size of the option tag and length"
+ );
+
typedef struct _IP6_ETHE_ADDR_OPTION {
UINT8Type;
UINT8Length;
diff --git a/NetworkPkg/Ip6Dxe/Ip6Option.h b/NetworkPkg/Ip6Dxe/Ip6Option.h
index bd8e223c8a67..fb07c28f5ad7 100644
--- a/NetworkPkg/Ip6Dxe/Ip6Option.h
+++ b/NetworkPkg/Ip6Dxe/Ip6Option.h
@@ -12,6 +12,77 @@
#define IP6_FRAGMENT_OFFSET_MASK (~0x3)
+//
+// For more information see RFC 8200, Section 4.3, 4.4, and 4.6
+//
+// This example format is from section 4.6
+// This does not apply to fragment headers
+//
+// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//| Next Header | Hdr Ext Len | |
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +
+//| |
+//. .
+//. Header-Specific Data .
+//. .
+//| |
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//
+// Next Header 8-bit selector. Identifies the type of
+//header immediately following the extension
+//header. Uses the same values as the IPv4
+//Protocol field [IANA-PN].
+//
+// Hdr Ext Len 8-bit unsigned integer. Length of the
+//
[edk2-devel] [PATCH v2 09/15] NetworkPkg: Ip6Dxe: SECURITY PATCH CVE-2023-45232 Unit Tests
From: Doug Flick
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4537
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4538
Unit tests to confirm that..
Infinite loop when parsing unknown options in the Destination Options
header
and
Infinite loop when parsing a PadN option in the Destination Options
header
... have been patched
This patch tests the following functions:
Ip6IsOptionValid
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
.../Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf| 10 +-
.../Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.h | 40 +++
.../Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp | 278 ++
3 files changed, 324 insertions(+), 4 deletions(-)
create mode 100644 NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.h
diff --git a/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
index 6e4de0745fb5..ba29dbabadb9 100644
--- a/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
+++ b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
@@ -1,13 +1,13 @@
## @file
-# Unit test suite for the Ip6Dxe using Google Test
+# Unit test suite for the Ip6DxeGoogleTest using Google Test
#
# Copyright (c) Microsoft Corporation.
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
[Defines]
INF_VERSION = 0x00010017
- BASE_NAME = Ip6DxeUnitTest
- FILE_GUID = 4F05D17D-D3E7-4AAE-820C-576D46D2D34A
+ BASE_NAME = Ip6DxeGoogleTest
+ FILE_GUID = AE39981C-B7FE-41A8-A9C2-F41910477CA3
VERSION_STRING = 1.0
MODULE_TYPE = HOST_APPLICATION
#
@@ -16,9 +16,11 @@ [Defines]
# VALID_ARCHITECTURES = IA32 X64 AARCH64
#
[Sources]
+ ../Ip6Option.c
+ Ip6OptionGoogleTest.h
Ip6DxeGoogleTest.cpp
Ip6OptionGoogleTest.cpp
- ../Ip6Option.c
+ Ip6OptionGoogleTest.h
[Packages]
MdePkg/MdePkg.dec
diff --git a/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.h
b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.h
new file mode 100644
index ..0509b6ae30d2
--- /dev/null
+++ b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.h
@@ -0,0 +1,40 @@
+/** @file
+ Exposes the functions needed to test the Ip6Option module.
+
+ Copyright (c) Microsoft Corporation
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef IP6_OPTION_HEADER_GOOGLE_TEST_H_
+#define IP6_OPTION_HEADER_GOOGLE_TEST_H_
+
+#include
+#include "../Ip6Impl.h"
+
+/**
+ Validate the IP6 option format for both the packets we received
+ and that we will transmit. It will compute the ICMPv6 error message fields
+ if the option is malformatted.
+
+ @param[in] IpSb The IP6 service data.
+ @param[in] PacketThe to be validated packet.
+ @param[in] OptionThe first byte of the option.
+ @param[in] OptionLen The length of the whole option.
+ @param[in] Pointer Identifies the octet offset within
+the invoking packet where the error was
detected.
+
+
+ @retval TRUE The option is properly formatted.
+ @retval FALSEThe option is malformatted.
+
+**/
+BOOLEAN
+Ip6IsOptionValid (
+ IN IP6_SERVICE *IpSb,
+ IN NET_BUF *Packet,
+ IN UINT8*Option,
+ IN UINT16 OptionLen,
+ IN UINT32 Pointer
+ );
+
+#endif // __IP6_OPTION_HEADER_GOOGLE_TEST_H__
diff --git a/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp
b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp
index f2cd90e1a952..29f8a4a96e4c 100644
--- a/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp
+++ b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp
@@ -12,6 +12,7 @@ extern "C" {
#include
#include "../Ip6Impl.h"
#include "../Ip6Option.h"
+ #include "Ip6OptionGoogleTest.h"
}
/
@@ -127,3 +128,280 @@ TEST_F (Ip6OptionValidationTest,
InvalidPrefixInfoOptionLengthShouldReturnFalse)
EXPECT_FALSE (Ip6IsNDOptionValid (option, optionLen));
}
+
+
+// Ip6IsOptionValid Tests
+
+
+// Define a fixture for your tests if needed
+class Ip6IsOptionValidTest : public ::testing::Test {
+protected:
+ // Add any setup code if needed
+ virtual void
+ SetUp (
+)
+ {
+// Initialize any resources or variables
+ }
+
+ // Add any cleanup code if needed
+ virtual void
+ TearDown (
+)
+ {
+// Clean up any resources or variables
+ }
+};
+
+// Test Description
+// Verify that a NULL option is Invalid
+TEST_F (Ip6IsOptionValidTest, NullOptionShouldReturnTrue) {
+ NET_BUF Packet = { 0 };
+ // we need to define enough of the packet to make the function work
+ // The function being tested will pass IpSb to Ip6SendIcmpError which is
defined above
+ IP6_SERVICE *IpSb = NULL;
+
+ EFI_IPv6_ADDRESS SourceAddress = { 0x20, 0x01, 0x0d,
[edk2-devel] [PATCH v2 07/15] NetworkPkg: Ip6Dxe: SECURITY PATCH CVE-2023-45231 Unit Tests
From: Doug Flick
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4536
Validates that the patch for...
Out-of-bounds read when handling a ND Redirect message with truncated
options
.. has been fixed
Tests the following function to ensure that an out of bounds read does
not occur
Ip6OptionValidation
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/Test/NetworkPkgHostTest.dsc| 1 +
.../Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf| 42 ++
.../Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.cpp| 20 +++
.../Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp | 129 ++
4 files changed, 192 insertions(+)
create mode 100644 NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
create mode 100644 NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.cpp
create mode 100644 NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp
diff --git a/NetworkPkg/Test/NetworkPkgHostTest.dsc
b/NetworkPkg/Test/NetworkPkgHostTest.dsc
index 24dee654df2e..7fa7b0f9d5be 100644
--- a/NetworkPkg/Test/NetworkPkgHostTest.dsc
+++ b/NetworkPkg/Test/NetworkPkgHostTest.dsc
@@ -26,6 +26,7 @@ [Components]
# Build HOST_APPLICATION that tests NetworkPkg
#
NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
+ NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
# Despite these library classes being listed in [LibraryClasses] below, they
are not needed for the host-based unit tests.
[LibraryClasses]
diff --git a/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
new file mode 100644
index ..6e4de0745fb5
--- /dev/null
+++ b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
@@ -0,0 +1,42 @@
+## @file
+# Unit test suite for the Ip6Dxe using Google Test
+#
+# Copyright (c) Microsoft Corporation.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = Ip6DxeUnitTest
+ FILE_GUID = 4F05D17D-D3E7-4AAE-820C-576D46D2D34A
+ VERSION_STRING = 1.0
+ MODULE_TYPE = HOST_APPLICATION
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 AARCH64
+#
+[Sources]
+ Ip6DxeGoogleTest.cpp
+ Ip6OptionGoogleTest.cpp
+ ../Ip6Option.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec
+ NetworkPkg/NetworkPkg.dec
+
+[LibraryClasses]
+ GoogleTestLib
+ DebugLib
+ NetLib
+ PcdLib
+
+[Protocols]
+ gEfiDhcp6ServiceBindingProtocolGuid
+
+[Pcd]
+ gEfiNetworkPkgTokenSpaceGuid.PcdDhcp6UidType
+
+[Guids]
+ gZeroGuid
diff --git a/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.cpp
b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.cpp
new file mode 100644
index ..6ebfd5fdfb70
--- /dev/null
+++ b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.cpp
@@ -0,0 +1,20 @@
+/** @file
+ Acts as the main entry point for the tests for the Ip6Dxe module.
+
+ Copyright (c) Microsoft Corporation
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+
+
+// Run the tests
+
+int
+main (
+ int argc,
+ char *argv[]
+ )
+{
+ testing::InitGoogleTest (, argv);
+ return RUN_ALL_TESTS ();
+}
diff --git a/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp
b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp
new file mode 100644
index ..f2cd90e1a952
--- /dev/null
+++ b/NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp
@@ -0,0 +1,129 @@
+/** @file
+ Tests for Ip6Option.c.
+
+ Copyright (c) Microsoft Corporation
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+
+extern "C" {
+ #include
+ #include
+ #include
+ #include "../Ip6Impl.h"
+ #include "../Ip6Option.h"
+}
+
+/
+// Defines
+///
+
+#define IP6_PREFIX_INFO_OPTION_DATA_LEN32
+#define OPTION_HEADER_IP6_PREFIX_DATA_LEN (sizeof (IP6_OPTION_HEADER) +
IP6_PREFIX_INFO_OPTION_DATA_LEN)
+
+
+// Symbol Definitions
+// These functions are not directly under test - but required to compile
+
+UINT32 mIp6Id;
+
+EFI_STATUS
+Ip6SendIcmpError (
+ IN IP6_SERVICE *IpSb,
+ IN NET_BUF *Packet,
+ IN EFI_IPv6_ADDRESS *SourceAddress OPTIONAL,
+ IN EFI_IPv6_ADDRESS *DestinationAddress,
+ IN UINT8 Type,
+ IN UINT8 Code,
+ IN UINT32*Pointer OPTIONAL
+ )
+{
+ // ..
+ return EFI_SUCCESS;
+}
+
+
+// Ip6OptionValidation Tests
[edk2-devel] [PATCH v2 06/15] NetworkPkg: Ip6Dxe: SECURITY PATCH CVE-2023-45231 Patch
From: Doug Flick
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4536
Bug Overview:
PixieFail Bug #3
CVE-2023-45231
CVSS 6.5 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N
CWE-125 Out-of-bounds Read
Out-of-bounds read when handling a ND Redirect message with truncated
options
Change Overview:
Adds a check to prevent truncated options from being parsed
+ //
+ // Cannot process truncated options.
+ // Cannot process options with a length of 0 as there is no Type
field.
+ //
+ if (OptionLen < sizeof (IP6_OPTION_HEADER)) {
+return FALSE;
+ }
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/Ip6Dxe/Ip6Option.c | 8
1 file changed, 8 insertions(+)
diff --git a/NetworkPkg/Ip6Dxe/Ip6Option.c b/NetworkPkg/Ip6Dxe/Ip6Option.c
index 199eea124dfe..8718d5d8756a 100644
--- a/NetworkPkg/Ip6Dxe/Ip6Option.c
+++ b/NetworkPkg/Ip6Dxe/Ip6Option.c
@@ -137,6 +137,14 @@ Ip6IsNDOptionValid (
return FALSE;
}
+ //
+ // Cannot process truncated options.
+ // Cannot process options with a length of 0 as there is no Type field.
+ //
+ if (OptionLen < sizeof (IP6_OPTION_HEADER)) {
+return FALSE;
+ }
+
Offset = 0;
//
--
2.43.0
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[edk2-devel] [PATCH v2 05/15] NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45229 Unit Tests
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4534
These tests confirm that the report bug...
"Out-of-bounds read when processing IA_NA/IA_TA options in a
DHCPv6 Advertise message"
..has been patched.
The following functions are tested to confirm an out of bounds read is
patched and that the correct statuses are returned:
Dhcp6SeekInnerOptionSafe
Dhcp6SeekStsOption
TCBZ4534
CVE-2023-45229
CVSS 6.5 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N
CWE-125 Out-of-bounds Read
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/Test/NetworkPkgHostTest.dsc| 1 +
.../GoogleTest/Dhcp6DxeGoogleTest.inf | 1 +
.../Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.h | 58 +++
NetworkPkg/Dhcp6Dxe/Dhcp6Io.c | 2 +-
.../Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp | 365 +-
5 files changed, 424 insertions(+), 3 deletions(-)
create mode 100644 NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.h
diff --git a/NetworkPkg/Test/NetworkPkgHostTest.dsc
b/NetworkPkg/Test/NetworkPkgHostTest.dsc
index 20bc90b1728d..24dee654df2e 100644
--- a/NetworkPkg/Test/NetworkPkgHostTest.dsc
+++ b/NetworkPkg/Test/NetworkPkgHostTest.dsc
@@ -16,6 +16,7 @@ [Defines]
SKUID_IDENTIFIER= DEFAULT
!include UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc
+
[Packages]
MdePkg/MdePkg.dec
UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec
diff --git a/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
index 8e9119a37158..12532ed30cb3 100644
--- a/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
+++ b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
@@ -18,6 +18,7 @@ [Defines]
[Sources]
Dhcp6DxeGoogleTest.cpp
Dhcp6IoGoogleTest.cpp
+ Dhcp6IoGoogleTest.h
../Dhcp6Io.c
../Dhcp6Utility.c
diff --git a/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.h
b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.h
new file mode 100644
index ..aed3b890827b
--- /dev/null
+++ b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.h
@@ -0,0 +1,58 @@
+/** @file
+ Acts as header for private functions under test in Dhcp6Io.c
+
+ Copyright (c) Microsoft Corporation
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef DHCP6_IO_GOOGLE_TEST_H_
+#define DHCP6_IO_GOOGLE_TEST_H_
+
+
+// These are the functions that are being unit tested
+
+
+#include
+
+/**
+ Seeks the Inner Options from a DHCP6 Option
+
+ @param[in] IaType The type of the IA option.
+ @param[in] Option The pointer to the DHCP6 Option.
+ @param[in] OptionLen The length of the DHCP6 Option.
+ @param[out] IaInnerOpt The pointer to the IA inner option.
+ @param[out] IaInnerLen The length of the IA inner option.
+
+ @retval EFI_SUCCESS Seek the inner option successfully.
+ @retval EFI_DEVICE_ERRORThe OptionLen is invalid.
+*/
+EFI_STATUS
+Dhcp6SeekInnerOptionSafe (
+ UINT16 IaType,
+ UINT8 *Option,
+ UINT32 OptionLen,
+ UINT8 **IaInnerOpt,
+ UINT16 *IaInnerLen
+ );
+
+/**
+ Seek StatusCode Option in package. A Status Code option may appear in the
+ options field of a DHCP message and/or in the options field of another
option.
+ See details in section 22.13, RFC3315.
+
+ @param[in] InstanceThe pointer to the Dhcp6 instance.
+ @param[in] Packet The pointer to reply messages.
+ @param[out] Option The pointer to status code option.
+
+ @retval EFI_SUCCESS Seek status code option successfully.
+ @retval EFI_DEVICE_ERROR An unexpected error.
+
+**/
+EFI_STATUS
+Dhcp6SeekStsOption (
+ IN DHCP6_INSTANCE*Instance,
+ IN EFI_DHCP6_PACKET *Packet,
+ OUTUINT8 **Option
+ );
+
+#endif // DHCP6_IO_GOOGLE_TEST_H
diff --git a/NetworkPkg/Dhcp6Dxe/Dhcp6Io.c b/NetworkPkg/Dhcp6Dxe/Dhcp6Io.c
index 89d16484a568..3b8feb4a2032 100644
--- a/NetworkPkg/Dhcp6Dxe/Dhcp6Io.c
+++ b/NetworkPkg/Dhcp6Dxe/Dhcp6Io.c
@@ -816,7 +816,7 @@ Dhcp6SeekStsOption (
// IA option to the end of the DHCP6 option area, thus subtract the space
// up until this option
//
- OptionLen = OptionLen - (*Option - Packet->Dhcp6.Option);
+ OptionLen = OptionLen - (UINT32)(*Option - Packet->Dhcp6.Option);
//
// Seek the inner option
diff --git a/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp
b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp
index 7ee40e4af480..7db253a7b87f 100644
--- a/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp
+++ b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp
@@ -13,6 +13,7 @@ extern "C" {
#include
#include "../Dhcp6Impl.h"
#include "../Dhcp6Utility.h"
+ #include "Dhcp6IoGoogleTest.h"
}
[edk2-devel] [PATCH v2 04/15] NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45229 Patch
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4534
Bug Details:
PixieFail Bug #1
CVE-2023-45229
CVSS 6.5 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N
CWE-125 Out-of-bounds Read
Change Overview:
Introduce Dhcp6SeekInnerOptionSafe which performs checks before seeking
the Inner Option from a DHCP6 Option.
>
> EFI_STATUS
> Dhcp6SeekInnerOptionSafe (
> IN UINT16 IaType,
> IN UINT8 *Option,
> IN UINT32 OptionLen,
> OUT UINT8 **IaInnerOpt,
> OUT UINT16 *IaInnerLen
> );
>
Lots of code cleanup to improve code readability.
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h | 138 +++---
NetworkPkg/Dhcp6Dxe/Dhcp6Io.c | 203 +---
2 files changed, 256 insertions(+), 85 deletions(-)
diff --git a/NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h b/NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h
index f2422c2f2827..220e7c68f11b 100644
--- a/NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h
+++ b/NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h
@@ -45,6 +45,20 @@ typedef struct _DHCP6_INSTANCE DHCP6_INSTANCE;
#define DHCP6_SERVICE_SIGNATURE SIGNATURE_32 ('D', 'H', '6', 'S')
#define DHCP6_INSTANCE_SIGNATURE SIGNATURE_32 ('D', 'H', '6', 'I')
+#define DHCP6_PACKET_ALL0
+#define DHCP6_PACKET_STATEFUL 1
+#define DHCP6_PACKET_STATELESS 2
+
+#define DHCP6_BASE_PACKET_SIZE 1024
+
+#define DHCP6_PORT_CLIENT 546
+#define DHCP6_PORT_SERVER 547
+
+#define DHCP_CHECK_MEDIA_WAITING_TIME EFI_TIMER_PERIOD_SECONDS(20)
+
+#define DHCP6_INSTANCE_FROM_THIS(Instance) CR ((Instance), DHCP6_INSTANCE,
Dhcp6, DHCP6_INSTANCE_SIGNATURE)
+#define DHCP6_SERVICE_FROM_THIS(Service)CR ((Service), DHCP6_SERVICE,
ServiceBinding, DHCP6_SERVICE_SIGNATURE)
+
//
// For more information on DHCP options see RFC 8415, Section 21.1
//
@@ -59,12 +73,10 @@ typedef struct _DHCP6_INSTANCE DHCP6_INSTANCE;
//| (option-len octets) |
//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
//
-#define DHCP6_SIZE_OF_OPT_CODE (sizeof(UINT16))
-#define DHCP6_SIZE_OF_OPT_LEN (sizeof(UINT16))
+#define DHCP6_SIZE_OF_OPT_CODE (sizeof (((EFI_DHCP6_PACKET_OPTION
*)0)->OpCode))
+#define DHCP6_SIZE_OF_OPT_LEN (sizeof (((EFI_DHCP6_PACKET_OPTION
*)0)->OpLen))
-//
// Combined size of Code and Length
-//
#define DHCP6_SIZE_OF_COMBINED_CODE_AND_LEN (DHCP6_SIZE_OF_OPT_CODE + \
DHCP6_SIZE_OF_OPT_LEN)
@@ -73,34 +85,122 @@ STATIC_ASSERT (
"Combined size of Code and Length must be 4 per RFC 8415"
);
-//
// Offset to the length is just past the code
-//
-#define DHCP6_OPT_LEN_OFFSET(a) (a + DHCP6_SIZE_OF_OPT_CODE)
+#define DHCP6_OFFSET_OF_OPT_LEN(a) (a + DHCP6_SIZE_OF_OPT_CODE)
STATIC_ASSERT (
- DHCP6_OPT_LEN_OFFSET (0) == 2,
+ DHCP6_OFFSET_OF_OPT_LEN (0) == 2,
"Offset of length is + 2 past start of option"
);
-#define DHCP6_OPT_DATA_OFFSET(a) (a + DHCP6_SIZE_OF_COMBINED_CODE_AND_LEN)
+#define DHCP6_OFFSET_OF_OPT_DATA(a) (a + DHCP6_SIZE_OF_COMBINED_CODE_AND_LEN)
STATIC_ASSERT (
- DHCP6_OPT_DATA_OFFSET (0) == 4,
+ DHCP6_OFFSET_OF_OPT_DATA (0) == 4,
"Offset to option data should be +4 from start of option"
);
+//
+// Identity Association options (both NA (Non-Temporary) and TA (Temporary
Association))
+// are defined in RFC 8415 and are a deriviation of a TLV stucture
+// For more information on IA_NA see Section 21.4
+// For more information on IA_TA see Section 21.5
+//
+//
+// The format of IA_NA and IA_TA option:
+//
+// 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//| OPTION_IA_NA | option-len |
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//|IAID (4 octets)|
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//|T1 (only for IA_NA)|
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//|T2 (only for IA_NA)|
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//| |
+//. IA_NA-options/IA_TA-options .
+//. .
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//
+#define DHCP6_SIZE_OF_IAID (sizeof(UINT32))
+#define DHCP6_SIZE_OF_TIME_INTERVAL (sizeof(UINT32))
-#define DHCP6_PACKET_ALL0
-#define DHCP6_PACKET_STATEFUL 1
-#define DHCP6_PACKET_STATELESS 2
+// Combined size of IAID, T1, and T2
+#define DHCP6_SIZE_OF_COMBINED_IAID_T1_T2 (DHCP6_SIZE_OF_IAID + \
+DHCP6_SIZE_OF_TIME_INTERVAL + \
+
[edk2-devel] [PATCH v2 03/15] NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45230 Unit Tests
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4535
Confirms that reported issue...
"Buffer overflow in the DHCPv6 client via a long Server ID option"
..has been corrected by the provided patch.
Tests the following functions to ensure they appropriately handle
untrusted data (either too long or too small) to prevent a buffer
overflow:
Dhcp6AppendOption
Dhcp6AppendETOption
Dhcp6AppendIaOption
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/Test/NetworkPkgHostTest.dsc| 1 +
.../GoogleTest/Dhcp6DxeGoogleTest.inf | 43 ++
.../GoogleTest/Dhcp6DxeGoogleTest.cpp | 20 +
.../Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp | 478 ++
4 files changed, 542 insertions(+)
create mode 100644 NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
create mode 100644 NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.cpp
create mode 100644 NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp
diff --git a/NetworkPkg/Test/NetworkPkgHostTest.dsc
b/NetworkPkg/Test/NetworkPkgHostTest.dsc
index 1aeca5c5b353..20bc90b1728d 100644
--- a/NetworkPkg/Test/NetworkPkgHostTest.dsc
+++ b/NetworkPkg/Test/NetworkPkgHostTest.dsc
@@ -24,6 +24,7 @@ [Components]
#
# Build HOST_APPLICATION that tests NetworkPkg
#
+ NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
# Despite these library classes being listed in [LibraryClasses] below, they
are not needed for the host-based unit tests.
[LibraryClasses]
diff --git a/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
new file mode 100644
index ..8e9119a37158
--- /dev/null
+++ b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
@@ -0,0 +1,43 @@
+## @file
+# Unit test suite for the Dhcp6Dxe using Google Test
+#
+# Copyright (c) Microsoft Corporation.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = Dhcp6DxeGoogleTest
+ FILE_GUID = 1D2A4C65-38C8-4C2F-BB60-B5FA49625AA9
+ VERSION_STRING = 1.0
+ MODULE_TYPE = HOST_APPLICATION
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 AARCH64
+#
+[Sources]
+ Dhcp6DxeGoogleTest.cpp
+ Dhcp6IoGoogleTest.cpp
+ ../Dhcp6Io.c
+ ../Dhcp6Utility.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec
+ NetworkPkg/NetworkPkg.dec
+
+[LibraryClasses]
+ GoogleTestLib
+ DebugLib
+ NetLib
+ PcdLib
+
+[Protocols]
+ gEfiDhcp6ServiceBindingProtocolGuid
+
+[Pcd]
+ gEfiNetworkPkgTokenSpaceGuid.PcdDhcp6UidType
+
+[Guids]
+ gZeroGuid
diff --git a/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.cpp
b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.cpp
new file mode 100644
index ..9aeced2f9156
--- /dev/null
+++ b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.cpp
@@ -0,0 +1,20 @@
+/** @file
+ Acts as the main entry point for the tests for the Dhcp6Dxe module.
+
+ Copyright (c) Microsoft Corporation
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+
+
+// Run the tests
+
+int
+main (
+ int argc,
+ char *argv[]
+ )
+{
+ testing::InitGoogleTest (, argv);
+ return RUN_ALL_TESTS ();
+}
diff --git a/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp
b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp
new file mode 100644
index ..7ee40e4af480
--- /dev/null
+++ b/NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp
@@ -0,0 +1,478 @@
+/** @file
+ Tests for Dhcp6Io.c.
+
+ Copyright (c) Microsoft Corporation
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include
+
+extern "C" {
+ #include
+ #include
+ #include
+ #include
+ #include "../Dhcp6Impl.h"
+ #include "../Dhcp6Utility.h"
+}
+
+
+// Defines
+
+
+#define DHCP6_PACKET_MAX_LEN 1500
+
+
+
+// Symbol Definitions
+// These functions are not directly under test - but required to compile
+
+
+// This definition is used by this test but is also required to compile
+// by Dhcp6Io.c
+EFI_IPv6_ADDRESS mAllDhcpRelayAndServersAddress = {
+ { 0xFF, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 2 }
+};
+
+EFI_STATUS
+EFIAPI
+UdpIoSendDatagram (
+ IN UDP_IO *UdpIo,
+ IN NET_BUF *Packet,
+ IN UDP_END_POINT*EndPoint OPTIONAL,
+ IN EFI_IP_ADDRESS *Gateway OPTIONAL,
+ IN
[edk2-devel] [PATCH v2 02/15] NetworkPkg: : Add Unit tests to CI and create Host Test DSC
Adds Host Based testing to the NetworkPkg Cc: Saloni Kasbekar Cc: Zachary Clark-williams Signed-off-by: Doug Flick [MSFT] --- NetworkPkg/Test/NetworkPkgHostTest.dsc | 98 ++ NetworkPkg/NetworkPkg.ci.yaml | 7 +- 2 files changed, 104 insertions(+), 1 deletion(-) create mode 100644 NetworkPkg/Test/NetworkPkgHostTest.dsc diff --git a/NetworkPkg/Test/NetworkPkgHostTest.dsc b/NetworkPkg/Test/NetworkPkgHostTest.dsc new file mode 100644 index ..1aeca5c5b353 --- /dev/null +++ b/NetworkPkg/Test/NetworkPkgHostTest.dsc @@ -0,0 +1,98 @@ +## @file +# NetworkPkgHostTest DSC file used to build host-based unit tests. +# +# Copyright (c) Microsoft Corporation. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + PLATFORM_NAME = NetworkPkgHostTest + PLATFORM_GUID = 3b68324e-fc07-4d49-9520-9347ede65879 + PLATFORM_VERSION= 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY= Build/NetworkPkg/HostTest + SUPPORTED_ARCHITECTURES = IA32|X64|AARCH64 + BUILD_TARGETS = NOOPT + SKUID_IDENTIFIER= DEFAULT + +!include UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc +[Packages] + MdePkg/MdePkg.dec + UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec + +[Components] + # + # Build HOST_APPLICATION that tests NetworkPkg + # + +# Despite these library classes being listed in [LibraryClasses] below, they are not needed for the host-based unit tests. +[LibraryClasses] + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf +!ifdef CONTINUOUS_INTEGRATION + BaseCryptLib|CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf + TlsLib|CryptoPkg/Library/TlsLibNull/TlsLibNull.inf +!else + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + +!if $(TOOL_CHAIN_TAG) == VS2019 or $(TOOL_CHAIN_TAG) == VS2022 +[LibraryClasses.X64] + # Provide StackCookie support lib so that we can link to /GS exports for VS builds + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf +!endif + +[LibraryClasses.common.UEFI_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf +[LibraryClasses.common.UEFI_APPLICATION] + DebugLib|MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf +[LibraryClasses.ARM, LibraryClasses.AARCH64] + # + # It is not possible to prevent ARM compiler calls to generic intrinsic functions. + # This library provides the instrinsic functions generated by a given compiler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images. + # +!if
[edk2-devel] [PATCH v2 01/15] NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45230 Patch
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4535
Bug Details:
PixieFail Bug #2
CVE-2023-45230
CVSS 8.3 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:L/A:H
CWE-119 Improper Restriction of Operations within the Bounds
of a Memory Buffer
Changes Overview:
> -UINT8 *
> +EFI_STATUS
> Dhcp6AppendOption (
> - IN OUT UINT8 *Buf,
> - IN UINT16 OptType,
> - IN UINT16 OptLen,
> - IN UINT8 *Data
> + IN OUT EFI_DHCP6_PACKET *Packet,
> + IN OUT UINT8 **PacketCursor,
> + IN UINT16OptType,
> + IN UINT16OptLen,
> + IN UINT8 *Data
>);
Dhcp6AppendOption() and variants can return errors now. All callsites
are adapted accordingly.
It gets passed in EFI_DHCP6_PACKET as additional parameter ...
> + //
> + // Verify the PacketCursor is within the packet
> + //
> + if ( (*PacketCursor < Packet->Dhcp6.Option)
> + || (*PacketCursor >= Packet->Dhcp6.Option +
(Packet->Size - sizeof (EFI_DHCP6_HEADER
> + {
> +return EFI_INVALID_PARAMETER;
> + }
... so it can look at Packet->Size when checking buffer space.
Also to allow Packet->Length updates.
Lots of checks added.
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Signed-off-by: Doug Flick [MSFT]
---
NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h| 43 +++
NetworkPkg/Dhcp6Dxe/Dhcp6Utility.h | 78 +++---
NetworkPkg/Dhcp6Dxe/Dhcp6Io.c | 409 +++--
NetworkPkg/Dhcp6Dxe/Dhcp6Utility.c | 373 +-
4 files changed, 666 insertions(+), 237 deletions(-)
diff --git a/NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h b/NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h
index 0eb9c669b5a1..f2422c2f2827 100644
--- a/NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h
+++ b/NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h
@@ -45,6 +45,49 @@ typedef struct _DHCP6_INSTANCE DHCP6_INSTANCE;
#define DHCP6_SERVICE_SIGNATURE SIGNATURE_32 ('D', 'H', '6', 'S')
#define DHCP6_INSTANCE_SIGNATURE SIGNATURE_32 ('D', 'H', '6', 'I')
+//
+// For more information on DHCP options see RFC 8415, Section 21.1
+//
+// The format of DHCP options is:
+//
+// 0 1 2 3
+// 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//| option-code | option-len |
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//| option-data |
+//| (option-len octets) |
+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//
+#define DHCP6_SIZE_OF_OPT_CODE (sizeof(UINT16))
+#define DHCP6_SIZE_OF_OPT_LEN (sizeof(UINT16))
+
+//
+// Combined size of Code and Length
+//
+#define DHCP6_SIZE_OF_COMBINED_CODE_AND_LEN (DHCP6_SIZE_OF_OPT_CODE + \
+ DHCP6_SIZE_OF_OPT_LEN)
+
+STATIC_ASSERT (
+ DHCP6_SIZE_OF_COMBINED_CODE_AND_LEN == 4,
+ "Combined size of Code and Length must be 4 per RFC 8415"
+ );
+
+//
+// Offset to the length is just past the code
+//
+#define DHCP6_OPT_LEN_OFFSET(a) (a + DHCP6_SIZE_OF_OPT_CODE)
+STATIC_ASSERT (
+ DHCP6_OPT_LEN_OFFSET (0) == 2,
+ "Offset of length is + 2 past start of option"
+ );
+
+#define DHCP6_OPT_DATA_OFFSET(a) (a + DHCP6_SIZE_OF_COMBINED_CODE_AND_LEN)
+STATIC_ASSERT (
+ DHCP6_OPT_DATA_OFFSET (0) == 4,
+ "Offset to option data should be +4 from start of option"
+ );
+
#define DHCP6_PACKET_ALL0
#define DHCP6_PACKET_STATEFUL 1
#define DHCP6_PACKET_STATELESS 2
diff --git a/NetworkPkg/Dhcp6Dxe/Dhcp6Utility.h
b/NetworkPkg/Dhcp6Dxe/Dhcp6Utility.h
index 046454ff4ac2..06947f6c1fcf 100644
--- a/NetworkPkg/Dhcp6Dxe/Dhcp6Utility.h
+++ b/NetworkPkg/Dhcp6Dxe/Dhcp6Utility.h
@@ -160,69 +160,85 @@ Dhcp6OnTransmitted (
);
/**
- Append the appointed option to the buf, and move the buf to the end.
+ Append the option to Buf, update the length of packet, and move Buf to the
end.
- @param[in, out] Buf The pointer to buffer.
- @param[in] OptType The option type.
- @param[in] OptLenThe length of option content.s
- @param[in] Data The pointer to the option content.
-
- @return Buf The position to append the next option.
+ @param[in, out] Packet A pointer to the packet, on success
Packet->Length
+ will be updated.
+ @param[in, out] PacketCursor The pointer in the packet, on success
PacketCursor
+ will be moved to the end of the option.
+ @param[in] OptTypeThe option type.
+ @param[in] OptLen The length of option contents.
+ @param[in] Data The pointer to the option content.
+ @retval EFI_INVALID_PARAMETER An argument provided to the function was
invalid
+ @retval EFI_BUFFER_TOO_SMALL The buffer is too small to append the option.
+
[edk2-devel] [PATCH v2 00/15] Security Patches for EDK II Network Stack
The security patches contained in this series with the exception of
"MdePkg/Test: Add gRT_GetTime Google Test Mock" and
"NetworkPkg: : Adds a SecurityFix.yaml file" have been reviewed
during GHSA-hc6x-cw6p-gj7h infosec review.
This patch series contains the following security patches for the
security vulnerabilities found by QuarksLab in the EDK II Network
Stack:
CVE-2023-45229
CVSS 6.5 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N
CWE-125 Out-of-bounds Read
CVE-2023-45230
CVSS 8.3 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:L/A:H
CWE-119 Improper Restriction of Operations within the Bounds
of a Memory Buffer
CVE-2023-45231
CVSS 6.5 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N
CWE-125 Out-of-bounds Read
CVE-2023-45232
CVSS 7.5 : CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:H
CWE-835 Loop with Unreachable Exit Condition ('Infinite Loop')
CVE-2023-45233
CVSS 7.5 : CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:H
CWE-835 Loop with Unreachable Exit Condition ('Infinite Loop')
CVE-2023-45234
CVSS 8.3 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:L/A:H
CWE-119 Improper Restriction of Operations within the Bounds
of a Memory Buffer
CVE-2023-45235
CVSS 8.3 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:L/A:H
CWE-119 Improper Restriction of Operations within the Bounds
of a Memory Buffer
NetworkPkg:
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
MdePkg:
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Doug Flick (8):
NetworkPkg: Ip6Dxe: SECURITY PATCH CVE-2023-45231 Patch
NetworkPkg: Ip6Dxe: SECURITY PATCH CVE-2023-45231 Unit Tests
NetworkPkg: Ip6Dxe: SECURITY PATCH CVE-2023-45232 Patch
NetworkPkg: Ip6Dxe: SECURITY PATCH CVE-2023-45232 Unit Tests
NetworkPkg: UefiPxeBcDxe: SECURITY PATCH CVE-2023-45234 Patch
NetworkPkg: UefiPxeBcDxe: SECURITY PATCH CVE-2023-45234 Unit Tests
NetworkPkg: UefiPxeBcDxe: SECURITY PATCH CVE-2023-45235 Patch
NetworkPkg: UefiPxeBcDxe: SECURITY PATCH CVE-2023-45235 Unit Tests
Douglas Flick [MSFT] (7):
NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45230 Patch
NetworkPkg: : Add Unit tests to CI and create Host Test DSC
NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45230 Unit Tests
NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45229 Patch
NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45229 Unit Tests
MdePkg: Test: Add gRT_GetTime Google Test Mock
NetworkPkg: : Adds a SecurityFix.yaml file
NetworkPkg/Test/NetworkPkgHostTest.dsc| 105 +++
.../GoogleTest/Dhcp6DxeGoogleTest.inf | 44 +
.../Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf| 44 +
.../GoogleTest/UefiPxeBcDxeGoogleTest.inf | 48 +
.../Library/MockUefiRuntimeServicesTableLib.h | 7 +
NetworkPkg/Dhcp6Dxe/Dhcp6Impl.h | 143 +++
NetworkPkg/Dhcp6Dxe/Dhcp6Utility.h| 78 +-
.../Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.h | 58 ++
.../Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.h | 40 +
NetworkPkg/Ip6Dxe/Ip6Nd.h | 35 +
NetworkPkg/Ip6Dxe/Ip6Option.h | 71 ++
.../GoogleTest/PxeBcDhcp6GoogleTest.h | 68 ++
NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.h | 17 +
NetworkPkg/Dhcp6Dxe/Dhcp6Io.c | 612 -
NetworkPkg/Dhcp6Dxe/Dhcp6Utility.c| 373 ++--
NetworkPkg/Ip6Dxe/Ip6Option.c | 84 +-
NetworkPkg/UefiPxeBcDxe/PxeBcDhcp6.c | 148 ++-
.../MockUefiRuntimeServicesTableLib.cpp | 5 +-
.../GoogleTest/Dhcp6DxeGoogleTest.cpp | 20 +
.../Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp | 839 ++
.../Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.cpp| 20 +
.../Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp | 407 +
NetworkPkg/NetworkPkg.ci.yaml | 7 +-
NetworkPkg/SecurityFixes.yaml | 123 +++
.../GoogleTest/PxeBcDhcp6GoogleTest.cpp | 574
.../GoogleTest/UefiPxeBcDxeGoogleTest.cpp | 19 +
26 files changed, 3650 insertions(+), 339 deletions(-)
create mode 100644 NetworkPkg/Test/NetworkPkgHostTest.dsc
create mode 100644 NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.inf
create mode 100644 NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.inf
create mode 100644
NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.inf
create mode 100644 NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.h
create mode 100644 NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.h
create mode 100644 NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.h
create mode 100644 NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6DxeGoogleTest.cpp
create mode 100644 NetworkPkg/Dhcp6Dxe/GoogleTest/Dhcp6IoGoogleTest.cpp
create mode 100644 NetworkPkg/Ip6Dxe/GoogleTest/Ip6DxeGoogleTest.cpp
create mode 100644 NetworkPkg/Ip6Dxe/GoogleTest/Ip6OptionGoogleTest.cpp
create mode 100644 NetworkPkg/SecurityFixes.yaml
create mode 100644 NetworkPkg/UefiPxeBcDxe/GoogleTest/PxeBcDhcp6GoogleTest.cpp
create mode 100644
NetworkPkg/UefiPxeBcDxe/GoogleTest/UefiPxeBcDxeGoogleTest.cpp
--
2.43.0
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io
Re: [edk2-devel] [Patch v2 1/1] MdeModulePkg/Core/Dxe: Set MemoryTypeInfo bin range from HOB
On 1/24/24 18:46, Kinney, Michael D wrote: > Hi Laszlo, > > Yes. I can add more details in the commit message. > > The impact is for ACPI S4. There are many reasons why the set of > HOBs passed into the DXE Core may change from boot to boot or that > allocations in the early DXE init phase should change where the > memory type information bins are allocated. > > ACPI S4 does do a power cycle and it is possible to do FW updates > or FW setup config changes between an S4 save and S4 resume operation. > > It is even possible for one OS to do S4 save. Reboot the system > to boot a completely different OS. Reboot again and do an S4 resume > of the original OS. > > If a platform chooses to enable this feature, the number of scenarios > that an S4 resume can fail is reduced. Awesome info, I couldn't have imagined. (I never use, or develop for, ACPI S4.) Thanks! Laszlo -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114461): https://edk2.groups.io/g/devel/message/114461 Mute This Topic: https://groups.io/mt/103918464/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/9847357/21656/1706620634/xyzzy [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
