On Thu, Dec 19, 2019 at 11:40 AM Sreenadh S wrote:
>
> We want to port fedora for RISC-V with out compressed (RV64IMAFD)
> instructions.
>
> We are from Centre for Development of Advanced Computing (C-DAC) India.
> We have implemented an Out-of order quad core RISC-V processor on FPGA.
>
> The processor is without compressed instructions.
> We want to port fedora for RISC-V with out compressed instructions.
>
> Please share the link if it is already ported, or give the guidelines on how
> to port.
Hi,
There seems to be a number of people who potentially want to have
Fedora/RISCV with RV64G.
Billa Surendra already started such
efforts, thus you most likely want to join it.
Basically the process should be easy as RV64GC and RV64G share the
same ABI. I checked glibc dynamic loader code at some point and
verified (by code review) that it allows mixing RV64GC and RV64G
shared libraries. Kernel, OpenSBI and U-Boot don't care about
compression instructions. IIRC U-Boot builds with RVC by default, but
there is a config option to disable that. So simply check and rebuild
firmware blobs with RVC disabled. Then load Fedora/RISCV existing disk
image on QEMU RV64GC virt machine or SiFive Unleashed. Find the latest
disk images here:
https://dl.fedoraproject.org/pub/alt/risc-v/disk-images/fedora/rawhide/
Then rebuild toolchain (e.g. GCC) to target RV64G instead of RV64GC.
Finally start building all installed packages until you can reassembly
disk image from them. Once you have that change QEMU or hardware to
RV64G.
david
>
> Regards,
>
> Sreenadh S.
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