etail, reports "REBOOTED" as the cause. That would let
> control plane software understand that these events are from a fake
> reboot.
>
> With regards,
> Daniel
> --
> |: https://berrange.com -o-
> https://www.flickr.com/photos/dberrange :|
> |: https://libvir
Hello Zhenzhong and Daniel,
With this implementation, upon TD reboot, some events
VIR_DOMAIN_EVENT_ID_LIFECYCLE are emitted (STARTED, STOPPED and probably
SHUTDOWN and RESUMED).
For normal VM, only the event VIR_DOMAIN_EVENT_ID_REBOOT is emitted.
Do you think it is good to align the API for TD
Several Intel CPU models with TSX technology (HLE & RTM features) are
affected by the vulnerability TAA[1]. One of the mitigation methods
for TAA is to disable TSX support on the host system. For that purpose,
in 2021, Intel published a microcode update to disable TSX. Linux kernel
also disables TS
(IA32_VMX_PROCBASED_CTLS2)
but has the login to interpret this bit position correctly in the register
raw value.
Libvirt does not have this login and by consequence, does not get the right
bit value.
I would appreciate some feedback on how we can best tackle this.
On Sat, May 31, 2025 at 12:31 AM Hector Cao
amp;item);
}
}
On Sun, Jun 1, 2025 at 11:01 PM Hector Cao wrote:
> I just realized that I should not modify the x86_features.xml file
> directly.
>
> I have to fix this issue elsewhere, probably in
> the sync_qemu_features_i386.py
> script or in the libvirt code tha
On Mon, Jun 2, 2025 at 3:23 PM Jiří Denemark wrote:
> On Mon, Jun 02, 2025 at 14:30:43 +0200, Hector Cao wrote:
> > Hello Jiri,
> >
> > Thanks for the feedback,
> >
> > On Mon, Jun 2, 2025 at 9:30 AM Jiri Denemark
> wrote:
> >
> > > On Mo
On Mon, Jun 16, 2025 at 2:39 PM Jiří Denemark wrote:
> On Mon, Jun 16, 2025 at 02:14:15 +0200, Hector Cao wrote:
> > On Mon, Jun 2, 2025 at 3:23 PM Jiří Denemark
> wrote:
> > > So except for not having the right CPU model in the capabilities XML
> > > (which is
Hello Jiri,
Thanks for the feedback,
On Mon, Jun 2, 2025 at 9:30 AM Jiri Denemark wrote:
> On Mon, Jun 02, 2025 at 01:19:29 +0200, Hector Cao wrote:
> > Several Intel CPU models with TSX technology (HLE & RTM features) are
> > affected by the vulnerability TAA[1]. One of the
ectly detected.
Hector Cao (1):
cpu_map: fix vmx-* features wrong bitmaps
src/cpu_map/x86_features.xml | 136 +--
1 file changed, 68 insertions(+), 68 deletions(-)
--
2.45.2
& 3D): System Programming Guide
Signed-off-by: Hector Cao
---
src/cpu_map/x86_features.xml | 136 +--
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml
index d06d60e230..0f60adb388 10
Hello,
This mail is a Request for Comment.
On recent Intel CPUs, some of the CPU features (mostly vmx-* subfeatures)
are listed and controlled
via the MSRs (Model Specific Registers) instead of the traditional CPUID
instruction method.
Right now, libvirt reads the MSR's values via /dev/cpu/*/cpu
Thanks Daniel,
On Wed, Jul 9, 2025 at 10:17 AM Daniel P. Berrangé
wrote:
> On Wed, Jul 09, 2025 at 10:03:26AM +0200, Hector Cao wrote:
> > Hello,
> >
> > This mail is a Request for Comment.
> >
> > On recent Intel CPUs, some of the CPU features (mostly vmx-
ction will be rendered at : https://libvirt.org/formatcaps.html
Best regards,
Hector
v2:
- wrap lines at 80 characters
Hector Cao (1):
docs : add doc on cpu model and features
docs/formatcaps.rst | 43 +++
1 file changed, 43 insertions(+)
--
2.34.1
From: Hector Cao
Add documentation on the way libvirt displays the Host CPU
model and capabilities (features). There is an implicit
expection from users to get the CPU model name matching the
CPU model they are running on, however, this does not happen
most of the time. As a consequence, having
From: Hector Cao
Hello,
This is a follow-up of the submission:
https://lists.libvirt.org/archives/list/devel@lists.libvirt.org/thread/EZBLO5CIGC3FTI5J72WNVAKWPSNQFLCY/
Based on Jiri's feedback, it is better to tackle this situation by
documentation. You can find here a proposal fo
From: Hector Cao
Add documentation on the way libvirt displays the Host CPU
model and capabilities (features). There is an implicit
expection from users to get the CPU model name matching the
CPU model they are running on, however, this does not happen
most of the time. As a consequence, having
On Wed, Jul 9, 2025 at 12:01 PM Daniel P. Berrangé
wrote:
> On Wed, Jul 09, 2025 at 05:58:03AM -0400, Andrea Bolognani wrote:
> > On Wed, Jul 09, 2025 at 09:53:40AM +0100, Daniel P. Berrangé via Devel
> wrote:
> > > On Wed, Jul 09, 2025 at 10:29:32AM +0200, Hector Cao wrote:
Hello Jiri,
Did you have any chance to take a look at this ?
I would like to know your thoughts on it
Thanks
Hector
PI process to start a guest.
>
>
One thing I'm worried about with modules-load.d approach is that at libvirt
installation, the module
is not actually loaded, a reboot is necessary to make it happen.
>
> With regards,
> Daniel
> --
> |: https://berrange.com -o-
> http
On Fri, Jul 25, 2025 at 11:22 AM Daniel P. Berrangé
wrote:
> On Wed, Jul 23, 2025 at 08:15:25PM +0200, Hector Cao wrote:
> > On Wed, Jul 9, 2025 at 12:01 PM Daniel P. Berrangé
> > wrote:
> >
> > > On Wed, Jul 09, 2025 at 05:58:03AM -0400, Andrea Bolognani wrote:
&
20 matches
Mail list logo
