This brings in a significantly cleaned up version of the remaining
patches on the devel branch and adds support for ZynqMP CGEMs. I have
tested CGEM0 on QEMU and CGEM3 on hardware. I am unable to test on the
BeagleBoneBlack at the moment, so I'd appreciate a double-check to
ensure I haven't broken
This updates sys_arch.c and sys_arch.h to the latest versions from the
upstream repository at hash 9e6ce84f2071bf0fbe3922db1cacf00823b2bdc1 and
updates the modifications to be compliant with how this project handles
modifications to upstream sources.
---
uLan/ports/os/rtems/arch/sys_arch.c | 7
On 6/30/2022 01:34, Sebastian Huber wrote:
On 30/06/2022 07:58, Sebastian Huber wrote:
On 29/06/2022 17:54, Kinsey Moore wrote:
On 6/29/2022 04:34, Sebastian Huber wrote:
On 29/06/2022 11:20, Chris Johns wrote:
On 29 Jun 2022, at 4:42 pm, Sebastian Huber
wrote:
On 29/06/2022 08:40
by:
commit 5fcaf843bdb491e2da14dc1af61806ac6d20bae5
Author: Kinsey Moore
Date: Wed Aug 21 16:34:12 2019 +
Add JSON log generation
Add log formatter hooks and JSON log formatter to the test
infrastructure
for consumption by automated processes or report generators.
I am
On 6/27/2022 01:27, Sebastian Huber wrote:
On 27/06/2022 05:02, Chris Johns wrote:
On 24/6/2022 7:44 pm, Sebastian Huber wrote:
On 20.06.22 04:03, chr...@rtems.org wrote:
From: Chris Johns
---
bsps/include/dev/irq/arm-gicv3.h | 5 +
1 file changed, 5 insertions(+)
diff --git
On 6/26/2022 22:37, Chris Johns wrote:
On 24/6/2022 7:43 pm, Sebastian Huber wrote:
The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4
define) and AArch64 targets. Use the existing WRITE_SR() abstraction to access
the interrupt group 0 and 1 enable registers. This
Looks good.
On 6/13/2022 20:39, chr...@rtems.org wrote:
From: Chris Johns
- Any page tables need to be flushed if the cache is enabled.
Disabling the cache may only be available in secure mode.
---
bsps/aarch64/include/bsp/aarch64-mmu.h | 3 ++-
1 file changed, 2 insertions(+), 1
On 6/15/2022 09:51, Gedare Bloom wrote:
On Tue, Jun 14, 2022 at 6:56 PM Chris Johns wrote:
On 14/6/2022 11:44 pm, Gedare Bloom wrote:
On Mon, Jun 13, 2022 at 7:39 PM wrote:
From: Chris Johns
---
bsps/include/dev/irq/arm-gicv3.h | 18 +++---
1 file changed, 15 insertions(+),
On 6/15/2022 09:48, Gedare Bloom wrote:
This was copied from the ZynqMP, should that also use a 64-bit value
for the ram length?
Probably any 64-bit architecture should do so?
I'd agree with that.
Kinsey
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On 6/12/2022 01:30, Chris Johns wrote:
On 12/6/22 12:59 am, Joel Sherrill wrote:
Should this use that obscure pointer macro Sebastian suggests sometimes?
I looked into that and could not get it to work. This works. If you would like
to try please do?
I've been testing for a little while with
On 5/12/2022 16:30, Vijay Kumar Banerjee wrote:
On Sat, Apr 16, 2022 at 10:48 AM Pavel Pisa wrote:
Hello Joel,
On Saturday 16 of April 2022 17:26:02 Joel Sherrill wrote:
Ok. Any suggestions for a directory name? :)
I am not in the full sync and I have lost the tracks where
are all RTEMS
On 5/24/2022 17:29, Chris Johns wrote:
On 24/5/2022 5:01 pm, Sebastian Huber wrote:
On 24/05/2022 08:43, Sebastian Huber wrote:
On 24/05/2022 02:32, Chris Johns wrote:
On 6/5/2022 4:16 pm, Sebastian Huber wrote:
- aarch64 bsps
These BSPs generated lots of warnings in the testsuite due to
It's possible for an environment to have unicode characters in its
paths. This was recently exposed by the latest newlib update and RSB
fails under Python 2.7 in this situation. This resolves the issue by
ensuring that the paths are encoded and decoded as necessary.
Related issue that caused the
I just discovered this when trying to update my CI that was running
Python 2.7. I have since bumped that to Python 3 to avoid the issue, but
the following patch resolves it.
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On 4/22/2022 07:28, Sebastian Huber wrote:
On 17/03/2022 13:30, Kinsey Moore wrote:
On 3/17/2022 05:00, Sebastian Huber wrote:
Hello,
the current Newlib build fails for aarch64 due to RTEMS-specific
patches:
CC libc/string/libc_a-wcscmp.o
../../../gnu-mirror-gcc-0f001dd/newlib/libc
Start code for most platforms requires hand-coded ASM but some can be
bootstrapped entirely in C, especially for paravirtualized platforms.
This change allows start code to be written in C where possible instead
of requiring architecture-specific ASM to bridge to C.
---
wscript | 6 +-
1 file
Moving forward, each origin directory should have its own top-level
COPYING.origin file to describe its license as well as a ORIGIN.origin
file to describe where the code is sourced from.
---
COPYING.lwip | 25 ++
COPYING.uLan
This expands the ability to substitute variables outside the current
limitation of values in options to asflags, cflags, cppflags, cxxflags,
ldflags, and includes. It is possible for all of these flags to utilize
user-defined information in config.ini, especially for paths to external
resources.
On 4/13/2022 13:38, Sebastian Huber wrote:
On 13/04/2022 20:06, Kinsey Moore wrote:
On 4/13/2022 00:53, Sebastian Huber wrote:
On 12/04/2022 20:55, Kinsey Moore wrote:
This allows options set as defines to the compiler to be used as
targets
for substitution using the syntax
On 4/13/2022 00:48, Sebastian Huber wrote:
On 12/04/2022 20:55, Kinsey Moore wrote:
diff --git a/wscript b/wscript
index 9de9d67b91..e2fc047ea8 100755
--- a/wscript
+++ b/wscript
@@ -276,10 +276,10 @@ class Item(object):
if target is None:
target = os.path.splitext
On 4/13/2022 00:53, Sebastian Huber wrote:
On 12/04/2022 20:55, Kinsey Moore wrote:
This allows options set as defines to the compiler to be used as targets
for substitution using the syntax ${DEFINES:define_target}. These need
special handling since they are not in a form that is trivially
This expands the ability to substitute variables outside the current
limitation of values in options to asflags, cflags, cppflags, cxxflags,
ldflags, and includes. It is possible for all of these flags to utilize
user-defined information in config.ini, especially for paths to external
resources.
This allows options set as defines to the compiler to be used as targets
for substitution using the syntax ${DEFINES:define_target}. These need
special handling since they are not in a form that is trivially consumed
by the mapping code.
---
wscript | 4
1 file changed, 4 insertions(+)
diff
This patch set adds more substitution capabilities to the build system
such that BSP configuration options can be used in flags and include
paths.
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All the content here looks great! Thanks Alan
Kinsey
On 3/18/2022 11:04, Alan Cudmore wrote:
This patch is for the rtems-docs repo. I added details on the procedure I
used to boot RTEMS images on the Xilinx ZCU102 board. I applied this patch,
and generated the HTML docs, and everything looks
These changes look good other than the nit in the first patch.
On 3/18/2022 02:19, Sebastian Huber wrote:
Separate the Interrupt Manager implementation from the generic Arm GICv3
support. Move parts of the Arm GICv3 support into a new header file. This
helps to support systems with a
Nit in the commit message: "dededicated"
On 3/18/2022 02:19, Sebastian Huber wrote:
Separate the Interrupt Manager implementation from the generic Arm GICv3
support. Move parts of the Arm GICv3 support into a new header file. This
helps to support systems with a clustered structure in which
The existing patch fails to build with the latest newlib. This picks up
an updated patch that compiles with both older and newer newlib.
---
rtems/config/tools/rtems-gcc-10-newlib-head.cfg | 4 ++--
rtems/config/tools/rtems-gcc-head-newlib-head.cfg | 4 ++--
2 files changed, 4 insertions(+), 4
On 3/17/2022 10:43, Sebastian Huber wrote:
On 17/03/2022 16:40, Kinsey Moore wrote:
with current newlib (ed32020)
This is not the current Newlib. There are a couple of build system
patches on top of it.
I guess the problem is that one location in the patch uses #include
On 3/17/2022 07:30, Kinsey Moore wrote:
On 3/17/2022 05:00, Sebastian Huber wrote:
Hello,
the current Newlib build fails for aarch64 due to RTEMS-specific
patches:
CC libc/string/libc_a-wcscmp.o
../../../gnu-mirror-gcc-0f001dd/newlib/libc/machine/aarch64/setjmp.S:29:10:
fatal error
On 3/17/2022 08:35, Sebastian Huber wrote:
On 17/03/2022 14:22, Kinsey Moore wrote:
On 3/17/2022 00:39, Sebastian Huber wrote:
Hello Kinsey,
On 16/03/2022 22:57, Kinsey Moore wrote:
Is moving the confdefs instance into a shared library supported and
expected to work?
yes, but the order
On 3/17/2022 00:39, Sebastian Huber wrote:
Hello Kinsey,
On 16/03/2022 22:57, Kinsey Moore wrote:
Is moving the confdefs instance into a shared library supported and
expected to work?
yes, but the order in which the linker resolves the dependencies is
very important. You have to make sure
On 3/17/2022 05:00, Sebastian Huber wrote:
Hello,
the current Newlib build fails for aarch64 due to RTEMS-specific patches:
CC libc/string/libc_a-wcscmp.o
../../../gnu-mirror-gcc-0f001dd/newlib/libc/machine/aarch64/setjmp.S:29:10:
fatal error: ../asmdefs.h: No such file or directory
Hi,
I'm working on porting Deos integration from RTEMS 5 to RTEMS 6. This requires
linking with their shared objects and I've run into a few linking issues with
the testsuite. I've narrowed the problems down to the way that some of the
tests are built: any test that has its confdefs instance in
The AArch64 changes look reasonable and resolve the bug I observed in
both the test case you provided as well as the test where I initially
discovered it.
Thanks,
Kinsey
On 3/8/2022 12:28, Sebastian Huber wrote:
The previous SMP multitasking start assumed that the initial heir thread of a
On 3/8/2022 02:52, Sebastian Huber wrote:
On 28/02/2022 20:18, Kinsey Moore wrote:
On 2/28/2022 12:19, Sebastian Huber wrote:
On 26/02/2022 08:03, Kinsey Moore wrote:
On 2/26/2022 00:53, Sebastian Huber wrote:
On 26/02/2022 00:41, Kinsey Moore wrote:
This may also be an issue for ARM, RISC
Add information about restricted use of device memory for ARM and
AArch64.
---
cpu-supplement/aarch64.rst | 5 +
cpu-supplement/arm.rst | 6 ++
2 files changed, 11 insertions(+)
diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
index 2b3d620..4576663 100644
---
I was looking though the rtems-lwip tree in adding license files and it struck
me that we currently have code with possibly different licenses and from
different external sources merged into the same tree with possibly differing
paths from the original source locations. There is at least one
These are the original COPYING files from the upstream projects.
---
COPYING.lwip | 25 +
COPYING.uLan | 33 +
2 files changed, 58 insertions(+)
create mode 100644 COPYING.lwip
create mode 100644 COPYING.uLan
diff --git a/COPYING.lwip
On 2/28/2022 12:19, Sebastian Huber wrote:
On 26/02/2022 08:03, Kinsey Moore wrote:
On 2/26/2022 00:53, Sebastian Huber wrote:
On 26/02/2022 00:41, Kinsey Moore wrote:
This may also be an issue for ARM, RISC-V and others as it doesn't
appear that ARM saves CPSR during context switch and I
, 2022 at 5:51 PM Kinsey Moore wrote:
Add an architecture-specific implementation for
_CPU_Get_current_per_CPU_control() to reduce overhead for getting the
current CPU's Per_CPU_Control structure.
---
.../cpu/aarch64/include/rtems/score/cpuimpl.h | 23 +++
1 file changed, 23
On 2/26/2022 00:53, Sebastian Huber wrote:
On 26/02/2022 00:41, Kinsey Moore wrote:
This may also be an issue for ARM, RISC-V and others as it doesn't
appear that ARM saves CPSR during context switch and I couldn't tell
that RISC-V does this either, though I'm less familiar
If a task migrates to a newly turned-up CPU as the first task it
executes, no guarantees are made about whether interrupts are enabled
and it is possible for a task to change interrupt enable states during
the migration. This preserves interrupt state across context switches.
---
Add an architecture-specific implementation for
_CPU_Get_current_per_CPU_control() to reduce overhead for getting the
current CPU's Per_CPU_Control structure.
---
.../cpu/aarch64/include/rtems/score/cpuimpl.h | 23 +++
1 file changed, 23 insertions(+)
diff --git
This may also be an issue for ARM, RISC-V and others as it doesn't
appear that ARM saves CPSR during context switch and I couldn't tell
that RISC-V does this either, though I'm less familiar with it.
Kinsey
On 2/25/2022 17:33, Kinsey Moore wrote:
If a task migrates to a newly turned-up CPU
When committed, the MicroBlaze RAM size was hard-coded to 16MB. This
changes the default to 256MB and sets the KCU105 BSPs to 2GB since that
is what the board has on it.
---
.../bsps/microblaze/microblaze_fpga/grp.yml | 2 ++
.../microblaze/microblaze_fpga/linkcmds.yml | 2 +-
Add MicroBlaze support for libdebugger. This uses only software break
type instructions to provide self-hosted GDB debugging support for
applications since internal control of debug hardware is not possible.
Also of note, this implementation for MicroBlaze would typically use the
brki instruction
Exception handling should be enabled at all times during execution to
ensure that exceptions are not ignored which would cause further
problems. This separates use of the exception enable bit from use of the
interrupt enable bit in the machine status register so that they can be
manipulated
This updates behavior of libdebugger to handle debug exceptions in
interrupt context by temporarily removing a software breakpoint,
stepping, and then resuming afterward.
---
cpukit/libdebugger/rtems-debugger-target.c | 105 +++--
cpukit/libdebugger/rtems-debugger-target.h | 5 +
Changes from v2:
* Removed interrupt hooks in favor of step and continue behavior
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Add a capability that allows for implementations that operate purely
using software breaks. Due to this implementation method, software
breaks must not be restored until just before returning control to the
thread itself and will be handled by the implementation through thread
switch and interrupt
It is possible to remove software breaks without actually restoring the
original instruction to memory. When this happens, the original
instruction is lost. This ensures that the original instruction is
restored when a software break is removed.
---
cpukit/libdebugger/rtems-debugger-target.c | 16
On 2/18/2022 14:37, Gedare Bloom wrote:
On Fri, Feb 18, 2022 at 6:50 AM Kinsey Moore wrote:
On 2/17/2022 20:31, Chris Johns wrote:
On 18/2/22 8:58 am, Kinsey Moore wrote:
On 2/17/2022 15:31, Chris Johns wrote:
On 18/2/22 7:12 am, Kinsey Moore wrote:
On 2/17/2022 13:53, Chris Johns wrote
Add MicroBlaze support for libdebugger. This uses only software break
type instructions to provide self-hosted GDB debugging support for
applications since internal control of debug hardware is not possible.
Also of note, this implementation for MicroBlaze would typically use the
brki instruction
The MicroBlaze Machine Status Register (MSR) does not have a flag that
designates the current execution status of the interrupt handler other
than the Interrupt Enable (IE) bit which may be unset for other reasons.
This makes use of R13 to signal the current interrupt nesting
encompassing the
Exception handling should be enabled at all times during execution to
ensure that exceptions are not ignored which would cause further
problems. This separates use of the exception enable bit from use of the
interrupt enable bit in the machine status register so that they can be
manipulated
Add hooks for manipulating system state before and after interrupts are
run. These hooks serve primarily to allow the MicroBlaze libdebugger
backend to prevent software breaks from occurring in interrupt context.
---
cpukit/score/cpu/microblaze/cpu.c | 42 +++
Add a capability that allows for implementations that operate purely
using software breaks. Due to this implementation method, software
breaks must not be restored until just before returning control to the
thread itself and will be handled by the implementation through thread
switch and interrupt
Differences from v1:
* Patch 1/6: Commit message reworded
* Patch 4/6: Added for independent exception control
* Patch 6/6: Reworked to use illegal opcode instead of
architecture-defined software break instruction
___
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It is possible to remove software breaks without actually restoring the
original instruction to memory. When this happens, the original
instruction is lost. This ensures that the original instruction is
restored when a software break is removed.
---
cpukit/libdebugger/rtems-debugger-target.c | 16
On 2/17/2022 20:31, Chris Johns wrote:
On 18/2/22 8:58 am, Kinsey Moore wrote:
On 2/17/2022 15:31, Chris Johns wrote:
On 18/2/22 7:12 am, Kinsey Moore wrote:
On 2/17/2022 13:53, Chris Johns wrote:
Who is setting breaks points in interrupts?
Where I encountered issues was setting breaks
On 2/17/2022 15:31, Chris Johns wrote:
On 18/2/22 7:12 am, Kinsey Moore wrote:
On 2/17/2022 13:53, Chris Johns wrote:
On 16/2/22 7:38 am, Kinsey Moore wrote:
Add hooks for manipulating system state before and after interrupts are
run. These hooks serve primarily to allow the MicroBlaze
On 2/17/2022 13:53, Chris Johns wrote:
On 16/2/22 7:38 am, Kinsey Moore wrote:
Add hooks for manipulating system state before and after interrupts are
run. These hooks serve primarily to allow the MicroBlaze libdebugger
backend to prevent software breaks from occurring in interrupt context.
I
On 2/17/2022 13:17, Chris Johns wrote:
On 16/2/22 7:38 am, Kinsey Moore wrote:
It is possible to remove software breaks without actually restoring the
original instruction to memory. When this happens, the original
instruction is lost.
Should this
This ensures that when a software break
Add MicroBlaze support for libdebugger. This uses only software break
instructions to provide self-hosted GDB debugging support for
applications since internal control of debug hardware is not possible.
---
.../libdebugger/rtems-debugger-microblaze.c | 1440 +
The MicroBlaze Machine Status Register (MSR) does not have a flag that
designates the current execution status of the interrupt handler other
than the Interrupt Enable (IE) bit which may be unset for other reasons.
This makes use of R13 to signal the current interrupt nesting
encompassing the
Add hooks for manipulating system state before and after interrupts are
run. These hooks serve primarily to allow the MicroBlaze libdebugger
backend to prevent software breaks from occurring in interrupt context.
---
cpukit/score/cpu/microblaze/cpu.c | 42 +++
Add a capability that allows for implementations that operate purely
using software breaks. Due to this implementation method, software
breaks must not be restored until just before returning control to the
thread itself and will be handled by the implementation through thread
switch and interrupt
This patch set adds libdebugger support for the MicroBlaze CPU port
along with the support necessary for a pure software-break
implementation of a libdebugger backend. This also fixes a bug
discovered during development.
___
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It is possible to remove software breaks without actually restoring the
original instruction to memory. When this happens, the original
instruction is lost. This ensures that when a software break is removed,
its original instruction is restored.
---
cpukit/libdebugger/rtems-debugger-target.c |
Avoid use of magic numbers in favor of named constants and add MSR to
the interrupt frame so that thread dispatch can occur on exceptions as
well.
---
.../microblaze_fpga/start/_interrupt_handler.S | 4 +++-
cpukit/score/cpu/microblaze/cpu_asm.S| 16
Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and
mark this functionality as available on MicroBlaze.
---
.../cpu/microblaze/include/rtems/score/cpu.h | 38
.../microblaze-exception-extensions.S | 177 ++
.../microblaze-exception-extensions.c
On 2/2/2022 01:22, Sebastian Huber wrote:
Hello Kinsey,
could you please use the _CPU_* and CPU_* prefixes only for items
which are defined by the CPU port interface:
cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
The dispatch code was unnecessarily saving and restoring an extra
interrupt frame. This avoids the extra frame and folds the dispatch call
into a fallthrough to the interrupt frame restoration code.
---
cpukit/score/cpu/microblaze/cpu_asm.S | 48 ++-
1 file changed, 3
This patch adds a vector for debug events along with a hook similar to
the exception framework. The debug vector generates an exception frame
for use by libdebugger.
---
.../start/_debug_sw_break_handler.S | 106 ++
bsps/microblaze/shared/start/start.S | 7 +-
This patch updates the CPU_Exception_frame to include all necessary
registers, combines hardware snd software exception handlers into a
shared vector, provides an architecture-specific hook for taking
control of exception handling, and moves exception handling over to
actually using the
Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and
mark this functionality as available on MicroBlaze.
---
cpukit/score/cpu/microblaze/cpu.c | 133 +
cpukit/score/cpu/microblaze/cpu_asm.S | 137 ++
This patch updates the CPU_Exception_frame to include all necessary
registers, combines hardware snd software exception handlers into a
shared vector, provides an architecture-specific hook for taking
control of exception handling, and moves exception handling over to
actually using the
The dispatch code was unnecessarily saving and restoring an extra
interrupt frame. This avoids the extra frame and folds the dispatch call
into a fallthrough to the interrupt frame restoration code.
---
cpukit/score/cpu/microblaze/cpu_asm.S | 48 ++-
1 file changed, 2
This patch adds a vector for debug events along with a hook similar to
the exception framework. The debug vector generates an exception frame
for use by libdebugger.
---
.../start/_debug_sw_break_handler.S | 106 ++
bsps/microblaze/shared/start/start.S | 7 +-
On 1/27/2022 09:57, Sebastian Huber wrote:
On 27/01/2022 16:37, Kinsey Moore wrote:
+*** TEST STACKCHK02 ***
+ STACK USAGE BY THREAD
+ID NAME LOW HIGH CURRENT AVAIL
USED
+0x09010001 IDLE 0x10104940 0x1010713f
When the stack checker is not enabled, the stack checker reporting
function can still be called. This prevents that call from performing a
null memory access in trying to find the high water mark if the stack
checker was never initialized.
This also introduces a test to ensure this call does not
On 1/27/2022 01:20, Sebastian Huber wrote:
On 26/01/2022 23:07, Kinsey Moore wrote:
diff --git a/cpukit/libmisc/stackchk/check.c
b/cpukit/libmisc/stackchk/check.c
index a2b63345d9..9119f8d940 100644
--- a/cpukit/libmisc/stackchk/check.c
+++ b/cpukit/libmisc/stackchk/check.c
@@ -487,6 +487,12
When the stack checker is not enabled, the stack checker reporting
function can still be called. This prevents that call from performing a
null memory access in trying to find the high water mark if the stack
checker was never initialized.
This also introduces a test to ensure this call does not
On 1/19/2022 09:41, Kinsey Moore wrote:
On 1/19/2022 09:13, Sebastian Huber wrote:
On 19/01/2022 15:42, Kinsey Moore wrote:
On 1/18/2022 10:23, Sebastian Huber wrote:
On 18/01/2022 17:19, Kinsey Moore wrote:
Hardware test results have recently been posted for AArch64.
Closes #4581
On 1/19/2022 09:13, Sebastian Huber wrote:
On 19/01/2022 15:42, Kinsey Moore wrote:
On 1/18/2022 10:23, Sebastian Huber wrote:
On 18/01/2022 17:19, Kinsey Moore wrote:
Hardware test results have recently been posted for AArch64.
Closes #4581
It would be nice if you could run also the new
On 1/18/2022 10:23, Sebastian Huber wrote:
On 18/01/2022 17:19, Kinsey Moore wrote:
Hardware test results have recently been posted for AArch64.
Closes #4581
It would be nice if you could run also the new validation tests on
this branch:
https://git.rtems.org/sebh/rtems.git/log/?h
Hardware test results have recently been posted for AArch64.
Closes #4581
---
config/rtems-bsps-tiers.ini | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/config/rtems-bsps-tiers.ini b/config/rtems-bsps-tiers.ini
index 875c5df..ba9e6b5 100644
---
These changes look good. I'm glad you were able to simplify this a bit.
As for the test failures, they all fall into that category of timing sensitive
tests that QEMU breaks with large bursts of near-simultaneous timer ticks.
Kinsey
-Original Message-
From: devel On Behalf Of Gedare
This was never updated when AArch64 documentation was added.
---
cpu-supplement/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/cpu-supplement/index.rst b/cpu-supplement/index.rst
index 951d6b7..733ffcc 100644
--- a/cpu-supplement/index.rst
+++ b/cpu-supplement/index.rst
@@ -24,6
When this file was brought in, it came from the wrong location or
freebsd-org hash. This corrects the file such that freebsd-to-rtems.py
runs cleanly.
---
freebsd/sys/arm64/include/machine/in_cksum.h | 43 +++-
1 file changed, 6 insertions(+), 37 deletions(-)
diff --git
On 12/15/2021 01:32, Sebastian Huber wrote:
Hello Kinsey,
I didn't work with libbsd for a while and noticed now that there are
changes after calling:
./freebsd-to-rtems.py -R
./freebsd-to-rtems.py
git status
modified: freebsd/sys/arm64/include/machine/in_cksum.h
I don't know how you
On 12/13/2021 19:56, Gedare Bloom wrote:
On Mon, Dec 13, 2021 at 9:55 AM Kinsey Moore wrote:
Everything else looks good. Just one nit below.
On 12/11/2021 10:16, Gedare Bloom wrote:
---
cpukit/score/cpu/aarch64/aarch64-smc.c| 72
.../aarch64/include/rtems/score
Everything else looks good. Just one nit below.
On 12/11/2021 10:16, Gedare Bloom wrote:
---
cpukit/score/cpu/aarch64/aarch64-smc.c| 72
.../aarch64/include/rtems/score/aarch64-smc.h | 83 +++
spec/build/cpukit/cpuaarch64.yml | 2 +
3
The AArch64 cache implementation does not define
rtems_cache_disable_data(), but declares that it does via
CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of
_CPU_cache_disable_data() is sufficient to enable this functionality
without the erroneous cache feature flag.
Closes
When the cadence I2C code was moved to a shared directory, the
references were updated but the install locations weren't. This updates
the install locations to match what out-of-tree applications expect.
---
spec/build/bsps/aarch64/xilinx-zynqmp/objcadencei2c.yml | 4 +++-
These two OAR copyright headers are the only two in the codebase with
a format that differs from the typical OAR copyright header. This makes
all of the OAR copyright headers consistent.
---
cpukit/score/cpu/arm/include/rtems/score/cpu.h | 2 +-
cpukit/score/src/stackallocatorforidle.c | 2
Ensure when both RTEMS_DEBUG is specified and pointers are large that
enough space is allocated to accomodate the Per_CPU_Control structure.
This changes the calculation to be more compositional instead of trying
to list out every permutation of options possible.
---
These lines were accidentally committed with a leading + which resulted
in them being non-functional. This restores them to functionality such
that the patch gets downloaded and applied appropriately.
---
rtems/config/tools/rtems-gcc-10-newlib-head.cfg | 4 ++--
1 file changed, 2 insertions(+), 2
Fixing the debug mask flag broke nested interrupts. This restores that
functionality.
---
bsps/aarch64/include/dev/irq/arm-gic-arch.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/bsps/aarch64/include/dev/irq/arm-gic-arch.h
b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
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