On 08/22/19 22:44, Jordan Justen wrote:
> On 2019-08-22 06:46:07, Laszlo Ersek wrote:
>> On 08/21/19 23:51, Jordan Justen wrote:
>>> On 2019-08-21 07:21:25, Laszlo Ersek wrote:
On 08/19/19 23:35, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> + //
> + // Enable caching
On 2019-08-22 06:46:07, Laszlo Ersek wrote:
> On 08/21/19 23:51, Jordan Justen wrote:
> > On 2019-08-21 07:21:25, Laszlo Ersek wrote:
> >> On 08/19/19 23:35, Lendacky, Thomas wrote:
> >>> From: Tom Lendacky
> >>>
> >>> + //
> >>> + // Enable caching
> >>> + //
> >>> + AsmEnableCache ();
> >>>
On 08/21/19 23:51, Jordan Justen wrote:
> On 2019-08-21 07:21:25, Laszlo Ersek wrote:
>> On 08/19/19 23:35, Lendacky, Thomas wrote:
>>> From: Tom Lendacky
>>>
>>> Currently, the OVMF code relies on the hypervisor to enable the cache
>>> support on the processor in order to improve the boot speed.
On 2019-08-21 07:21:25, Laszlo Ersek wrote:
> On 08/19/19 23:35, Lendacky, Thomas wrote:
> > From: Tom Lendacky
> >
> > Currently, the OVMF code relies on the hypervisor to enable the cache
> > support on the processor in order to improve the boot speed. However,
> > with SEV-ES, the hypervisor
On 8/21/19 9:21 AM, Laszlo Ersek wrote:
> On 08/19/19 23:35, Lendacky, Thomas wrote:
>> From: Tom Lendacky
>>
>> Currently, the OVMF code relies on the hypervisor to enable the cache
>> support on the processor in order to improve the boot speed. However,
>> with SEV-ES, the hypervisor is not
On 08/19/19 23:35, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> Currently, the OVMF code relies on the hypervisor to enable the cache
> support on the processor in order to improve the boot speed. However,
> with SEV-ES, the hypervisor is not allowed to change the CR0 register
> to enable
