On Mon, Jul 15, 2013 at 11:57:29AM -0300, Ezequiel Garcia wrote:
Here's the new MBus DT binding, implementing the changes proposed
by Thomas when we discussed the previous patchset:
http://www.spinics.net/lists/arm-kernel/msg257170.html
As far as I know, this round fixes *all* the
On Sat, Jul 20, 2013 at 06:58:55PM +0200, Andrew Lunn wrote:
On Mon, Jul 15, 2013 at 11:57:29AM -0300, Ezequiel Garcia wrote:
Here's the new MBus DT binding, implementing the changes proposed
by Thomas when we discussed the previous patchset:
http://www.spinics.net/lists/arm-kernel
On Wed, Jul 17, 2013 at 10:09:10AM +0800, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
Convert to use devm_* APIs to avoid resources leak on error handling case.
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
drivers/mtd/nand/orion_nand.c | 29
all DT parsing and uses cpu-of_node instead.
Cc: Andrew Lunn and...@lunn.ch
Cc: Jason Cooper ja...@lakedaemon.net
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
---
drivers/cpufreq/kirkwood-cpufreq.c | 14 --
1
On Mon, Jul 15, 2013 at 08:32:33PM -0300, Ezequiel Garcia wrote:
This patchset introduces a bunch of fixes that removes the direct use of
the shared timer control register, and also removes the need to include
a mach-specific header.
With this changes the driver can be included in
On Tue, Jul 16, 2013 at 09:20:59AM +0200, Thomas Petazzoni wrote:
Dear Andrew Lunn,
On Tue, 16 Jul 2013 08:59:52 +0200, Andrew Lunn wrote:
Maybe i'm missing something here. You are making use of
orion_timer_ctrl_clrset() from time-orion.c. How will this work on
370/XP which has
On Mon, Jul 15, 2013 at 08:32:38PM -0300, Ezequiel Garcia wrote:
Instead of accessing the RSTOUT register directly, this commit
adds a platform memory resource to map this register into the driver.
Hi Ezequiel
Have you looked at:
arch/arm/mach-mvebu/system-controller.c
It is also using this
with shared registers. It has done it before, so I consider it broken
anyway.
I (or somebody else) will take care of proper watchdog later.
- An updated branch can be found on
git://github.com/shesselba/linux-dove.git orion-irqchip-for-v3.11_v4
Hi Sebastian
You can add a
Tested-by: Andrew Lunn
is structured as follows:
1 Adapt mmc_of_parse() to return errors
2-6 Handle errors in current drivers using mmc_of_parse() (compile tested
only)
7-8 Convert mvsdio and respective dts files to mmc_of_parse() (tested on
kirkwood)
Hi Simon
Tested-by: Andrew Lunn and...@lunn.ch
I
{
+ compatible = gpio-leds;
+
+ misc {
+ label = sheevaplug:red:misc;
+ gpios = gpio1 14 1;
+ };
+ };
+};
--
1.7.9.5
Hi Simon
Looks good
Acked-by: Andrew Lunn and...@lunn.ch
qnap_dt_ts219_init(void);
#else
--
1.7.9.5
Acked-by: Andrew Lunn and...@lunn.ch
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devicetree-discuss@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/devicetree-discuss
On Tue, May 07, 2013 at 06:11:44PM +0200, Gregory CLEMENT wrote:
On 05/07/2013 05:52 PM, Valentin Longchamp wrote:
The kirkwood device found in the Prestera SoCs does not have all the
peripherals of its the usual kirkwood SoCs. There are hence missing
clocks in the SoCs.
This patch
On Thu, May 02, 2013 at 09:48:50PM +0200, Sebastian Hesselbarth wrote:
On 05/02/2013 09:35 PM, Jason Gunthorpe wrote:
I have kirkwood HW but I haven't had time to make newer kernels run on
it, otherwise I'd test it too :(
I also have kirkwood HW but that will cut me from email as I use it as
...@linutronix.de
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Gregory Clement gregory.clem
On Wed, Apr 24, 2013 at 12:05:56AM +0200, Arnaud Ebalard wrote:
Signed-off-by: Arnaud Ebalard a...@natisbad.org
Tested-by: Arnaud Ebalard a...@natisbad.org
---
drivers/hwmon/Kconfig | 10 +
drivers/hwmon/Makefile |1 +
drivers/hwmon/g762.c | 1058
Hi Arnaud
+static DEVICE_ATTR(pwm1, S_IWUSR | S_IRUGO, get_pwm, set_pwm);
+static DEVICE_ATTR(pwm1_polarity, S_IWUSR | S_IRUGO,
+get_pwm_polarity, set_pwm_polarity);
+static DEVICE_ATTR(pwm1_mode, S_IWUSR | S_IRUGO,
+get_pwm_mode, set_pwm_mode);
+static
-static int m48t86_rtc_probe(struct platform_device *dev)
+static int m48t86_rtc_probe(struct platform_device *pdev)
{
unsigned char reg;
- struct m48t86_ops *ops = dev-dev.platform_data;
- struct rtc_device *rtc = rtc_device_register(m48t86,
-
Hi all,
So, lets see if i have all this right.
IO space needs to stay where it is, somewhere in the top 1GB, because
it is limited to the 32bit address space.
We must have some SDRAM in the bottom of the 40bit address range in
order that DMA works. Bounce buffers are used for anything which is
On Thu, Mar 21, 2013 at 05:26:15PM +0100, Gregory CLEMENT wrote:
From: Lior Amsalem al...@marvell.com
For mvebu IOs are 32 bits and we have 40 bits memory due to LPAE so
make sure we give 32 bits addresses to the IOs.
Hi Gregory, Lior
I don't really understand what this comment is supposed
/*
- * 4 GB of plug-in RAM modules by default but only 3GB
- * are visible, the amount of memory available can be
- * changed by the bootloader according the size of the
- * module actually plugged
+ * 8 GB of
On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
Could you recommend a document which introduces LPAE.
Only being able to address 7GB seems a bit odd to me. I kind of
expected you set up
Or, better, locate all the internal registers above 8G and use
contiguous DRAM mapping from 0 - 8GB
Wouldn't that get us into a 640KBs is enough for everyone situation?
Why not put the IO at the very top of the 1TB address range?
Andrew
___
+* QNAP Power Off
+
+QNAP NAS devices have a microcontroller controlling the main power
+supply. This microcontroller is connected to UART1 of the Kirkwood and
+Orion5x SoCs. Sending the charactor 'A', at 19200 baud, tells the
+microcontroller to turn the power off. This driver adds a
And don't forget to compile the SPI flash driver, CONFIG_MTD_M25P80=y
Hi Ezequiel
Maybe it makes sense to provide a patch to mvebu_defconfig to add
CONFIG_MTD_M25P80=y ?
Andrew
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devicetree-discuss mailing list
On Mon, Feb 04, 2013 at 01:51:20PM -0300, Ezequiel Garcia wrote:
Hi,
This patchset adds support for the SPI controller
available in Armada 370 and Armada XP SoC.
Hi Ezequiel
Do any of the boards we have with mainline support have any devices on
the SPI busses? Its hard to test otherwise.
On Wed, Jan 30, 2013 at 01:10:35PM -0500, Jason Cooper wrote:
Gregory,
Adding devicetree-discuss.
Guys, how do you prefer to handle plug-in RAM modules? describe the
soldered-in amount, or?
On Wed, Jan 30, 2013 at 06:35:17PM +0100, Gregory CLEMENT wrote:
On 01/30/2013 06:33 PM,
Well in fact it is 4GB RAM but we can only use 3GB (we need the last GB
of address space for peripheral, CPU registers and IOmem).
Hi Gregory
Does the CPU support Large Physical Addressing, LPA? Is that on the
roadmap for Armada?
Andrew
___
On Thu, Jan 31, 2013 at 05:22:54PM +0100, Andrew Lunn wrote:
Well in fact it is 4GB RAM but we can only use 3GB (we need the last GB
of address space for peripheral, CPU registers and IOmem).
Hi Gregory
Does the CPU support Large Physical Addressing, LPA? Is that on the
roadmap
On Wed, Jan 16, 2013 at 12:43:57PM +0100, Stefan Peter wrote:
Hi Andrew
on 15.01.2013 13:51, Andrew Lunn wrote:
On Tue, Jan 15, 2013 at 01:13:12PM +0100, Stefan Peter wrote:
In order to be able to use the ecc-mode, add the bch module to the default
settings for the kirwood boards
On Tue, Jan 15, 2013 at 01:13:12PM +0100, Stefan Peter wrote:
In order to be able to use the ecc-mode, add the bch module to the default
settings for the kirwood boards and enable the activation in orin-nand.c
Signed-off-by: Stefan Peter s.pe...@mpl.ch
---
diff --git
Hi Folks
I'm moving the cpuidle code for Kirkwood into drivers/cpuidle. I'm
following the way cpuidle-calxeda.c instantiates the driver, it uses
module_init(calxeda_cpuidle_init) and calxeda_cpuidle_init() uses
of_machine_is_compatible(calxeda,highbank) so only loading the
driver in a
On Sun, Jan 06, 2013 at 01:41:13PM +, Russell King - ARM Linux wrote:
On Sun, Jan 06, 2013 at 02:18:05PM +0100, Andrew Lunn wrote:
I'm moving the cpuidle code for Kirkwood into drivers/cpuidle. I'm
following the way cpuidle-calxeda.c instantiates the driver, it uses
module_init
,
+ .of_match_table = of_kirkwood_cpuidle_match,
+ },
+};
+
+module_platform_driver(kirkwood_cpuidle_driver);
+
+MODULE_AUTHOR(Andrew Lunn and...@lunn.ch);
+MODULE_DESCRIPTION(Kirkwood cpu idle driver);
+MODULE_LICENSE(GPLv2);
+MODULE_ALIAS(platform:kirkwood-cpuidle);
--
1.7.10.4
On Fri, Dec 28, 2012 at 08:18:42AM -0600, Rob Herring wrote:
On 12/28/2012 06:47 AM, Andrew Lunn wrote:
Move the Kirkwood cpuidle driver out of arch/arm/mach-kirkwood and
into drivers/cpuidle. Convert the driver into a platform driver and
add a device tree binding. Add a DT node
On Fri, Dec 28, 2012 at 03:32:08PM +0100, Florian Fainelli wrote:
Hello Andrew,
Le 12/28/12 13:47, Andrew Lunn a ??crit :
Move the Kirkwood cpuidle driver out of arch/arm/mach-kirkwood and
into drivers/cpuidle. Convert the driver into a platform driver and
add a device tree binding. Add
On Fri, Dec 28, 2012 at 08:55:31AM -0600, Rob Herring wrote:
On 12/28/2012 08:35 AM, Andrew Lunn wrote:
On Fri, Dec 28, 2012 at 08:18:42AM -0600, Rob Herring wrote:
On 12/28/2012 06:47 AM, Andrew Lunn wrote:
Move the Kirkwood cpuidle driver out of arch/arm/mach-kirkwood and
into drivers
The block of registers is for controlling the SDRAM. Its not really a
MFD. The cpuidle code is putting the SDRAM controller into self
refresh mode and then doing a WFI.
It is multi-function in the sense that multiple subsystems needing to
access shared registers. If you have ECC, then
Putting DDR/SDRAM into self refresh means, you no longer have RAM
available to execute and any code CPU needs to execute after that has
to be executed either from lock down cache with no cache evictions or
from some internal on chip memory with caches disabled to avoid accesses
to DDR. Not
Is this single CPU or multi-cpu machine ?
Its a uniprocessor.
Even though the cpu_do_idle()
has just couple of instructions, there can be lot more happening in
background especially with multi masters system. It might be safe if the
single CPU is the only master accessing DDR. In
material.
Acked-by: Andrew Lunn and...@lunn.ch
Andrew
Thanks,
Gregory CLEMENT (2):
arm: mvebu: add RTC support for Armada 370 and Armada XP
rtc: rtc-mv: Add the device tree binding documentation
.../devicetree/bindings/rtc/orion-rtc.txt | 18
On Mon, Dec 10, 2012 at 11:37:23PM +0100, Thomas Petazzoni wrote:
Dear Grant Likely,
On Mon, 10 Dec 2012 21:47:55 +, Grant Likely wrote:
Maybe an explicit status = okay here?
Only necessary if it is typical for the device to get disabled. I don't
add status=okay properties
the top. If its available before Arnd pulls, you can squash
it, otherwise send it upstream as a standalone patch.
Thanks
Andrew
On Mon, Nov 19, 2012 at 10:38:06AM -0700, Stephen Warren wrote:
On 11/17/2012 01:51 AM, Andrew Lunn wrote:
Given appropriate devicetree bindings
On Tue, Nov 20, 2012 at 10:11:18AM -0700, Stephen Warren wrote:
On 11/20/2012 01:37 AM, Andrew Lunn wrote:
Hi Jason
These are good comments from Stephan that i want to address. However,
i also don't want to delay the pull-requests direction arm-soc, the
merge window is getting close
On Tue, Nov 20, 2012 at 02:17:24PM -0700, Stephen Warren wrote:
On 11/20/2012 01:31 PM, Andrew Lunn wrote:
On Tue, Nov 20, 2012 at 10:11:18AM -0700, Stephen Warren wrote:
On 11/20/2012 01:37 AM, Andrew Lunn wrote:
Hi Jason
These are good comments from Stephan that i want to address
On Fri, Nov 16, 2012 at 11:23:35AM -0800, Anton Vorontsov wrote:
On Fri, Nov 16, 2012 at 09:19:47AM -0500, Jason Cooper wrote:
[...]
Is it ok if we take this through the arm-soc tree with your Ack?
Yup. The driver looks good.
Acked-by: Anton Vorontsov cbouatmai...@gmail.com
Hi Anton
On Fri, Nov 16, 2012 at 08:32:50PM +0100, Simon Baatz wrote:
Hi Andrew,
On Tue, Nov 13, 2012 at 04:44:45PM +0100, Andrew Lunn wrote:
Signed-off-by: Andrew Lunn and...@lunn.ch
---
arch/arm/boot/dts/kirkwood-ib62x0.dts |6 ++
arch/arm/mach-kirkwood/board-ib62x0.c | 13
+ * Hold configuration here, cannot be more than one instance of the driver
+ * since pm_power_off itself is global.
+ */
+static int gpio_num = -1;
+static int gpio_active_low;
+
+static void gpio_poweroff_do_poweroff(void)
+{
+ BUG_ON(gpio_num == -1);
+
+ /* drive it
the same scheme.
The driver code was initially developed by Jamie Lentin and extended
to cover the PXA case by Andrew Lunn.
v1 - v2: Moved to drivers/power/reset
v2 - v3: Fixed polarity of IB62x0 GPIO
Increased delay before WARN if the power does not go off.
Andrew Lunn (2):
ARM: Kirkwood
Also enable the gpio-poweroff driver when DT is used.
Signed-off-by: Andrew Lunn and...@lunn.ch
Tested-by: Jamie Lentin j...@lentin.co.uk
---
arch/arm/boot/dts/kirkwood-dnskw.dtsi |5 +
arch/arm/mach-kirkwood/Kconfig|4
arch/arm/mach-kirkwood/board-dnskw.c | 12
Signed-off-by: Andrew Lunn and...@lunn.ch
Tested-by: Simon Baatz gmbno...@gmail.com
---
arch/arm/boot/dts/kirkwood-ib62x0.dts |6 ++
arch/arm/mach-kirkwood/board-ib62x0.c | 13 -
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/kirkwood
From: Jamie Lentin j...@lentin.co.uk
Given appropriate devicetree bindings, this driver registers a
pm_power_off function to set a GPIO line high/low to power down
your board.
Signed-off-by: Jamie Lentin j...@lentin.co.uk
Signed-off-by: Andrew Lunn and...@lunn.ch
Tested-by:Simon Baatz gmbno
to a number of symbols
renamed clk_gate to gate_clk
renamed *-clock-gating to *-gating-clock
Add gating-clock implementation for Armada 370/XP
Add Tested-by from Gregory
Documented required clock property in armada-370-xp-timer.txt
Andrew Lunn (1):
ARM: Kirkwood: switch to DT clock providers
From: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Tested-by Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370.dtsi |7 ++
arch/arm/boot/dts/armada-xp.dtsi| 42
From: Gregory CLEMENT gregory.clem...@free-electrons.com
Add Armada 370/XP specific CPU clocks
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Tested-by Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 +++
From: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Tested-by Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../devicetree/bindings/arm/armada-370-xp-timer.txt |1 +
arch/arm/boot/dts/armada-370-db.dts
a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Signed-off-by: Andrew Lunn and...@lunn.ch
Tested
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
With true DT clock providers available switch Dove clock setup in DT-
enabled boards. While AUXDATA can be removed completely from bus probing,
some devices still don't know about DT at all. Therefore, some clock
aliases are created
Hesselbarth sebastian.hesselba...@gmail.com
+ * Andrew Lunn and...@lunn.ch
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+#include linux/kernel.h
+#include
With true DT clock providers available switch Kirkwood clock setup in
DT- enabled boards. While AUXDATA can be removed completely from bus
probing, some devices still don't know about DT. Therefore, some clkdev
aliases are created until these devices also move to DT.
Signed-off-by: Andrew Lunn
From: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Andrew Lunn and...@lunn.ch
---
arch/arm/boot/dts/armada-370.dtsi |8
arch/arm/boot/dts/armada-xp.dtsi |7 +++
2 files changed, 15
From: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Andrew Lunn and...@lunn.ch
---
.../bindings/clock/mvebu-gated-clock.txt | 43 ++
arch/arm/mach-mvebu/Kconfig
Armarda 370 based mirabox
Armara XP based OpenBlocks
and by Sebastian on:
Dove based Cubox.
Andrew Lunn (1):
ARM: Kirkwood: switch to DT clock providers
Gregory CLEMENT (3):
clk: mvebu: add armada-370-xp CPU specific clocks
clk: armada-370-xp: add support for clock framework
clocksource: time
From: Gregory CLEMENT gregory.clem...@free-electrons.com
Add Armada 370/XP specific CPU clocks
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../devicetree/bindings/clock/mvebu-core-clock.txt | 18 +--
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 +++
From: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370.dtsi |7 ++
arch/arm/boot/dts/armada-xp.dtsi| 42 +++
arch/arm/mach-mvebu/Kconfig |
a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Signed-off-by: Andrew Lunn and...@lunn.ch
From: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
cc: John Stultz johns...@us.ibm.com
---
arch/arm/boot/dts/armada-370-db.dts |4
arch/arm/boot/dts/armada-370-xp.dtsi |1 +
Hesselbarth sebastian.hesselba...@gmail.com
+ * Andrew Lunn and...@lunn.ch
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+#include linux/kernel.h
+#include
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
With true DT clock providers available switch Dove clock setup in DT-
enabled boards. While AUXDATA can be removed completely from bus probing,
some devices still don't know about DT at all. Therefore, some clock
aliases are created
With true DT clock providers available switch Kirkwood clock setup in
DT- enabled boards. While AUXDATA can be removed completely from bus
probing, some devices still don't know about DT. Therefore, some clkdev
aliases are created until these devices also move to DT.
Signed-off-by: Andrew Lunn
I had a quick look and made a few comments, but overall, it looks
really great. I really hope we can get this in 3.8.
Hi Thomas
Thanks for the quick feedback.
It looks like i squashed some patches from Sebastian in the wrong
place. I will fix this and your other comments. I will probably send
Signed-off-by: Andrew Lunn and...@lunn.ch
---
arch/arm/boot/dts/kirkwood-ib62x0.dts |6 ++
arch/arm/mach-kirkwood/board-ib62x0.c | 13 -
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts
b/arch/arm/boot/dts/kirkwood-ib62x0
From: Jamie Lentin j...@lentin.co.uk
Given appropriate devicetree bindings, this driver registers a
pm_power_off function to set a GPIO line high/low to power down
your board.
Signed-off-by: Jamie Lentin j...@lentin.co.uk
Signed-off-by: Andrew Lunn and...@lunn.ch
---
.../devicetree/bindings
the same scheme.
The driver code was initially developed by Jamie Lentin and extended
to cover the PXA case by Andrew Lunn.
v1 - v2: Moved to drivers/power/reset
Andrew Lunn (2):
ARM: Kirkwood: Convert DNSKW to use gpio-poweroff.
ARM: Kirkwood: Convert IB62x0 to use gpio-poweroff.
Jamie Lentin (1
Also enable the gpio-poweroff driver when DT is used.
Signed-off-by: Andrew Lunn and...@lunn.ch
Tested-by: Jamie Lentin j...@lentin.co.uk
---
arch/arm/boot/dts/kirkwood-dnskw.dtsi |5 +
arch/arm/mach-kirkwood/Kconfig|4
arch/arm/mach-kirkwood/board-dnskw.c | 12
On Sun, Nov 11, 2012 at 03:03:49PM -0700, Stephen Warren wrote:
On 11/11/2012 09:21 AM, Andrew Lunn wrote:
From: Jamie Lentin j...@lentin.co.uk
Given appropriate devicetree bindings, this driver registers a
pm_power_off function to set a GPIO line high/low to power down
your board
On Mon, Nov 12, 2012 at 09:17:48AM -0700, Stephen Warren wrote:
On 11/12/2012 01:25 AM, Andrew Lunn wrote:
On Sun, Nov 11, 2012 at 03:03:49PM -0700, Stephen Warren wrote:
On 11/11/2012 09:21 AM, Andrew Lunn wrote:
From: Jamie Lentin j...@lentin.co.uk
Given appropriate devicetree
From: Jamie Lentin j...@lentin.co.uk
Given appropriate devicetree bindings, this driver registers a
pm_power_off function to set a GPIO line high/low to power down
your board.
Signed-off-by: Jamie Lentin j...@lentin.co.uk
Signed-off-by: Andrew Lunn and...@lunn.ch
---
.../devicetree/bindings
Signed-off-by: Andrew Lunn and...@lunn.ch
---
arch/arm/boot/dts/kirkwood-ib62x0.dts |6 ++
arch/arm/mach-kirkwood/board-ib62x0.c | 13 -
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts
b/arch/arm/boot/dts/kirkwood-ib62x0
the same scheme.
The driver code was initially developed by Jamie Lentin and extended
to cover the PXA case by Andrew Lunn.
Andrew Lunn (2):
ARM: Kirkwood: Convert DNSKW to use gpio-poweroff.
ARM: Kirkwood: Convert IB62x0 to use gpio-poweroff.
Jamie Lentin (1):
gpio: Add simple poweroff-gpio
On Sun, Nov 11, 2012 at 05:12:58PM -0800, Anton Vorontsov wrote:
On Mon, Nov 12, 2012 at 02:00:31AM +0100, Linus Walleij wrote:
On Sun, Nov 11, 2012 at 5:21 PM, Andrew Lunn and...@lunn.ch wrote:
From: Jamie Lentin j...@lentin.co.uk
Given appropriate devicetree bindings, this driver
, and currently converting orion5x to DT is low
priority. Adding a phy node later will also not affect backwards
compatibility.
Andrew Lunn (2):
ARM: Kirkwood: ehci-orion: Add device tree binding
ARM: Kirkwood: Convert all DT boards to EHCI via DT.
.../devicetree/bindings/usb/ehci-orion.txt
Based on previous work by Michael Walle and Jason Cooper.
Made their work actually work, which required added interrupt from DT
and auxdata, along with setting the dma_mask, which DT does not
currently do.
Signed-off-by: Andrew Lunn and...@lunn.ch
Tested-by: Sebastian Hesselbarth
Now that the EHCI driver has DT support, drop old style configuration
of it and add DT in its place. Since all the boards enable the EHCI,
enable it by default in kirkwood.dtsi. Any new boards which don't have
USB can specifically disable it.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
arch
I was thinking to add a more generic helper function like this:
static inline void watchdog_get_dttimeout(struct device_node *node,
u32 *timeout)
{
if (node)
of_property_read_u32(node, timeout, wdd-timeout);
}
You forgot to change the function signature.
Also, if
Date: Tue, 2 Oct 2012 18:01:00 +0200
From: Fabio Porcedda fabio.porce...@gmail.com
To: Wim Van Sebroeck w...@iguana.be, linux-watch...@vger.kernel.org,
linux-arm-ker...@lists.infradead.org, Nicolas Ferre
nicolas.fe...@atmel.com, Jean-Christophe PLAGNIOL-VILLARD
On Mon, Oct 01, 2012 at 02:48:01PM +0200, Fabio Porcedda wrote:
On Mon, Oct 1, 2012 at 2:45 PM, Andrew Lunn and...@lunn.ch wrote:
On Mon, Oct 01, 2012 at 02:24:39PM +0200, Fabio Porcedda wrote:
Tested on an at91sam9260 board (evk-pro3)
Signed-off-by: Fabio Porcedda fabio.porce
On Mon, Oct 01, 2012 at 02:54:55PM +0200, Fabio Porcedda wrote:
On Mon, Oct 1, 2012 at 2:48 PM, Fabio Porcedda fabio.porce...@gmail.com
wrote:
On Mon, Oct 1, 2012 at 2:45 PM, Andrew Lunn and...@lunn.ch wrote:
On Mon, Oct 01, 2012 at 02:24:39PM +0200, Fabio Porcedda wrote:
Tested
+Required properties:
+- compatible: must be marvell,orion-ehci
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: The EHCI interrupt
+- phy-version: Can be one of:
+ NA - Don't touch the phy, something else has already configured
Hi Thomas
Hum, which patches are stalling the integration into the Marvell tree?
l2 cache, I think.
The trees Jason built for pull requests in the direction of arm-soc
had the l2 cache patch as the very first in the series. Now that these
patches have run into some trouble, its blocking all
On Thu, Sep 20, 2012 at 03:30:40PM +, Arnd Bergmann wrote:
On Monday 17 September 2012, Linus Walleij wrote:
You found the weak spot between two consolidation tracks.
Getting rid of a broadcast autodetect functions from say
mach/foo-id-probe.h is nominally done by passing the data
So, wouldn't we need a small, architecture-independent, infrastructure,
through which architecture-specific code could register at boot
time which SoC we are running on, and drivers could query this
information from the common infrastructure?
Of course, the major problem is to figure out
thinks that autoprobing is not going to happen,
Tested-by: Andrew Lunn and...@lunn.ch
However, i still think it would be nice to have auto probing.
Andrew
Cc: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Grant Likely
I had a closer look at how kirkwood probes its id. I mentionend kirkwood_id()
earlier but in fact it is kirkwood_pcie_id(). I assume pcie registers are shut
down with pcie clk gated? That would require to have pcie running at least at
boot-time on all boards.
While it is still possible to
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common
binding
+part and usage.
+
+Required properties:
+- compatible:
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -0,0 +1,45 @@
+* Marvell EBU GPIO controller
+
+Required properties:
+
+- compatible : Should be marvell,orion-gpio, marvell,mv78200-gpio
+ or marvell,armadaxp-gpio. marvell,orion-gpio should be used for
+ Orion, Kirkwood,
u32s [Guenter Roeck]
* Don't count GPIOs twice [Andrew Lunn]
* Use of_prop_next_u32 to get records in a more obvious fashion
* Use CONFIG_OF_GPIO instead of CONFIG_OF
* Apply __devinitdata to of_gpio_fan_match [Andrew Lunn]
Signed-off-by: Jamie Lentin j...@lentin.co.uk
---
.../devicetree
Hi Jamie
+static int gpio_fan_get_of_pdata(struct device *dev,
+ struct gpio_fan_platform_data *pdata)
+{
+ struct device_node *node;
+ struct gpio_fan_speed *speed;
+ unsigned *ctrl;
+ unsigned i;
+ u32 u;
+ struct property *prop;
+
On Fri, Sep 07, 2012 at 10:57:01AM -0400, Jason Cooper wrote:
On Mon, Sep 03, 2012 at 06:58:07PM +0200, Andrew Lunn wrote:
Tools like kisskb are good at finding build regressions in the kernel
sources. However, regressions in the DT desscriptions are not found,
because generally these build
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c
b/arch/arm/mach-kirkwood/board-dnskw.c
index 4ab3506..e202a07 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -67,29 +67,6 @@ static unsigned int dnskw_mpp_config[] __initdata = {
0
};
Tools like kisskb are good at finding build regressions in the kernel
sources. However, regressions in the DT desscriptions are not found,
because generally these build systems don't build the DT binary blobs.
Extend the ARM all target to build all enabled DTB files.
Signed-off-by: Andrew Lunn
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