This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar
If the requested reset controller is not yet available, have reset_control_get
and device_reset return -EPROBE_DEFER so the driver can decide to request
probe deferral.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/reset/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Am Dienstag, den 16.07.2013, 09:47 -0600 schrieb Stephen Warren:
On 07/16/2013 12:51 AM, Shawn Guo wrote:
On Tue, Jul 16, 2013 at 09:50:42AM +0800, Shawn Guo wrote:
Hi Philipp,
On Thu, May 30, 2013 at 11:09:00AM +0200, Philipp Zabel wrote:
This driver implements a reset controller
Hi Shawn,
Am Dienstag, den 16.07.2013, 12:10 +0800 schrieb Shawn Guo:
On Mon, Jul 15, 2013 at 09:35:52PM -0600, Stephen Warren wrote:
It's a little bit late to register gpio-reset driver at module_init
time, because gpio-reset provides reset control via gpio for other
devices which are
Am Dienstag, den 16.07.2013, 14:51 +0800 schrieb Shawn Guo:
On Tue, Jul 16, 2013 at 09:50:42AM +0800, Shawn Guo wrote:
Hi Philipp,
On Thu, May 30, 2013 at 11:09:00AM +0200, Philipp Zabel wrote:
This driver implements a reset controller device that toggle a gpio
connected to a reset
Hi Stephen,
Am Montag, den 15.07.2013, 21:35 -0600 schrieb Stephen Warren:
On 07/15/2013 07:50 PM, Shawn Guo wrote:
Hi Philipp,
On Thu, May 30, 2013 at 11:09:00AM +0200, Philipp Zabel wrote:
This driver implements a reset controller device that toggle a gpio
connected to a reset pin
This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar
of the
sram from being part of the pool.
Suggested-by: Rob Herring robherri...@gmail.com
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz ulrich.pr...@googlemail.com
Acked-by: Philipp Zabel p.za...@pengutronix.de
---
Documentation/devicetree/bindings/misc/sram.txt |8
ulrich.pr...@googlemail.com
Acked-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/misc/sram.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c
index d87cc91..afe66571 100644
--- a/drivers/misc/sram.c
+++ b/drivers
Hi Matt,
[Cc: devicetree-discuss@lists.ozlabs.org]
Am Freitag, den 28.06.2013, 23:49 -0500 schrieb Matt Sealey:
On Fri, Jun 28, 2013 at 5:49 PM, Fabio Estevam feste...@gmail.com wrote:
From: Fabio Estevam fabio.este...@freescale.com
Enable Video Processing Unit (VPU) support.
Am Mittwoch, den 26.06.2013, 11:18 +0200 schrieb Heiko Stübner:
Hi Philipp,
Am Dienstag, 25. Juni 2013, 12:17:05 schrieb Philipp Zabel:
Hi Heiko,
Am Dienstag, den 25.06.2013, 10:47 +0200 schrieb Heiko Stübner:
Some SoCs need parts of their sram for special purposes. So while being
Hi Heiko,
Am Dienstag, den 25.06.2013, 10:46 +0200 schrieb Heiko Stübner:
The pool is created thru devm_gen_pool_create, so the call to
gen_pool_destroy is not necessary.
Instead the sram-clock must be turned off again if it exists.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
Hi Heiko,
Am Dienstag, den 25.06.2013, 10:47 +0200 schrieb Heiko Stübner:
Some SoCs need parts of their sram for special purposes. So while being part
of the periphal, it should not be part of the genpool controlling the sram.
Threfore add an option mmio-sram-reserved to keep arbitary
Am Dienstag, den 18.06.2013, 13:00 +0800 schrieb Wei Yongjun:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
Add the missing unlock before return from function coda_stop_streaming()
in the error handling case.
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
Am Freitag, den 07.06.2013, 09:40 +0200 schrieb Markus Niebel:
Am 28.03.2013 16:23, wrote Philipp Zabel:
From: Sascha Hauer s.ha...@pengutronix.de
This adds support for the LVDS Display Bridge contained
in i.MX5 and i.MX6 SoCs.
Bit mapping, data width, and video timings
Hi Shawn,
Am Donnerstag, den 06.06.2013, 23:16 +0800 schrieb Shawn Guo:
On Thu, Mar 28, 2013 at 04:23:30PM +0100, Philipp Zabel wrote:
+static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
+{
+ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+ struct
This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar
Hi Stephen,
Am Mittwoch, den 29.05.2013, 17:19 -0600 schrieb Stephen Warren:
On 05/28/2013 09:06 AM, Philipp Zabel wrote:
This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion
Hi Fabio,
Am Montag, den 27.05.2013, 13:25 -0300 schrieb Fabio Estevam:
On Tue, Feb 26, 2013 at 8:39 AM, Philipp Zabel p.za...@pengutronix.de wrote:
This driver implements a reset controller device that toggles gpios
connected to reset pins of peripheral ICs. The delay between assertion
This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v6
Hi Olof,
Am Donnerstag, den 11.04.2013, 03:35 -0700 schrieb Olof Johansson:
Hi,
On Thu, Mar 28, 2013 at 9:35 AM, Philipp Zabel p.za...@pengutronix.de wrote:
This driver implements a reset controller device that toggles gpios
connected to reset pins of peripheral ICs. The delay between
Hi Greg,
Am Montag, den 08.04.2013, 10:40 -0700 schrieb Greg Kroah-Hartman:
On Mon, Apr 08, 2013 at 06:04:31PM +0200, Philipp Zabel wrote:
Hi,
the following patches allow to use the integrated Television Encoder
(TVEv2) on the i.MX53 SoC as VGA output encoder for the IPU
Am Donnerstag, den 04.04.2013, 09:53 +0200 schrieb Philipp Zabel:
Am Mittwoch, den 03.04.2013, 15:04 -0300 schrieb Fabio Estevam:
Fix typo in 'initially-in-reset' example.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
.../devicetree/bindings/reset/gpio-reset.txt
Hi Rob,
Am Donnerstag, den 04.04.2013, 08:49 -0500 schrieb Rob Herring:
On 03/28/2013 11:35 AM, Philipp Zabel wrote:
From: Stephen Warren swar...@nvidia.com
This binding is intended to represent the hardware reset signals present
internally in most IC (SoC, FPGA, ...) designs
This is needed so the Television Encoder driver can set the rate
on tve_clk and have it propagated up to pll4_sw.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx51-imx53.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx
Hi,
the first two are just cleanups, the following three patches are changes
to the i.MX53 clock tree that are necessary to use the TVEv2 module as
VGA output on the Freescale i.MX53-QSB or TQ MBa53 boards.
regards
Philipp
---
Documentation/devicetree/bindings/clock/imx5-clock.txt | 1 -
Use imx_clk_mux_flags to set the appropriate flags for the TVE
selector clock. This is needed so tve_clk rate changes can propagate
up to pll4_sw.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx51-imx53.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
Remove the tve_di clock from the CCM clock tree. It will be provided
by the Television Encoder driver, as this clock is an output signal
of the TVE module.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Documentation/devicetree/bindings/clock/imx5-clock.txt | 1 -
arch/arm/mach-imx/clk
On i.MX53, there is only tve_ext_sel.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx51-imx53.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c
b/arch/arm/mach-imx/clk-imx51-imx53.c
index 1be5078
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/staging/imx-drm/ipuv3-crtc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c
b/drivers/staging/imx-drm/ipuv3-crtc.c
index b028b0d..620e571 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
Hi,
the following patches allow to use the integrated Television Encoder
(TVEv2) on the i.MX53 SoC as VGA output encoder for the IPU. This is
useful for the Freescale i.MX53-QSB and TQ MBa53 boards, which have
VGA and DVI-I connectors, respectively.
regards
Philipp
---
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/staging/imx-drm/ipu-v3/ipu-dc.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-dc.c
b/drivers/staging/imx-drm/ipu-v3/ipu-dc.c
index 355b8a2..1cb0631 100644
on i.MX53-QSB uses pin7/pin8, and the analog
part of the DVI-I connector on MBa53 connects to pin4/pin6.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/staging/imx-drm/imx-drm-core.c | 15 -
drivers/staging/imx-drm/imx-drm.h | 4 +-
drivers/staging/imx-drm/ipu-v3/imx
Add WRG and WCLK opcodes to the display controller microcode,
and allow multi instruction codes.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/staging/imx-drm/ipu-v3/ipu-dc.c | 39 -
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git
-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/staging/imx-drm/Kconfig | 7 +
drivers/staging/imx-drm/Makefile | 1 +
drivers/staging/imx-drm/imx-tve.c | 755 ++
3 files changed, 763 insertions(+)
create mode 100644 drivers/staging/imx-drm/imx-tve.c
24-bit GBR order is needed on the display interface connected
to the Television Encoder (TVEv2) on i.MX53.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/staging/imx-drm/imx-drm.h | 10 ++
drivers/staging/imx-drm/ipu-v3/ipu-dc.c | 10 ++
2 files changed, 20
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/staging/imx-drm/ipu-v3/ipu-di.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c
b/drivers/staging/imx-drm/ipu-v3/ipu-di.c
index ec340da..26534b7 100644
Hi Fabio,
Am Montag, den 08.04.2013, 12:26 -0300 schrieb Fabio Estevam:
Hi Phiipp,
On Mon, Apr 8, 2013 at 11:46 AM, Philipp Zabel p.za...@pengutronix.de wrote:
Hi,
the first two are just cleanups, the following three patches are changes
to the i.MX53 clock tree that are necessary
: gpio-reset {
compatible = gpio-reset;
reset-gpios = gpio5 0 1; /* active-low */
reset-delays = 1; /* 10 ms */
- initially-in-reset: 1;
+ initially-in-reset = 1;
#reset-cells = 1;
};
Acked-by: Philipp Zabel p.za...@pengutronix.de
thanks
Philipp
Am Donnerstag, den 28.03.2013, 10:54 +0800 schrieb Shawn Guo:
On Wed, Mar 20, 2013 at 11:52:47AM +0100, Philipp Zabel wrote:
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
Acked-by: Grant Likely grant.lik...@secretlab.ca
---
Changes since
Am Donnerstag, den 28.03.2013, 09:41 +0100 schrieb Martin Fuzzey:
On 28/03/13 08:32, Shawn Guo wrote:
On Wed, Mar 27, 2013 at 07:43:40PM +0100, Martin Fuzzey wrote:
Maybe pinctrl entries should also be added?
Generally, the pinctrl entries should be added in board.dts.
Yes sorry I
Am Donnerstag, den 28.03.2013, 15:20 +0800 schrieb Shawn Guo:
On Wed, Mar 27, 2013 at 06:30:38PM +0100, Philipp Zabel wrote:
Query silicon revision to determine clock tree and add post
dividers for newer revisions.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm
Am Donnerstag, den 28.03.2013, 15:51 +0800 schrieb Shawn Guo:
On Wed, Mar 27, 2013 at 06:30:45PM +0100, Philipp Zabel wrote:
From: Steffen Trumtrar s.trumt...@pengutronix.de
Add ldb device tree node and clock lookups.
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
Signed
Am Donnerstag, den 28.03.2013, 14:08 +0800 schrieb Shawn Guo:
On Wed, Mar 27, 2013 at 06:30:35PM +0100, Philipp Zabel wrote:
+config DRM_IMX_LDB
+ tristate Support for LVDS displays
+ help
+ Choose this to enable the internal LVDS Display Bridge (LDB)
+ found on i.MX53
Hi Martin,
Am Mittwoch, den 27.03.2013, 19:40 +0100 schrieb Martin Fuzzey:
Hi Philipp,
On 27/03/13 18:30, Philipp Zabel wrote:
+static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct
Hi Andrew,
thanks for taking care of these patches.
Am Mittwoch, den 27.03.2013, 15:27 -0700 schrieb Andrew Morton:
On Wed, 20 Mar 2013 11:52:45 +0100 Philipp Zabel p.za...@pengutronix.de
wrote:
This driver requests and remaps a memory region as configured in the
device tree. It serves
Am Donnerstag, den 28.03.2013, 22:43 +0800 schrieb Shawn Guo:
On Thu, Mar 28, 2013 at 10:58:00AM +0100, Philipp Zabel wrote:
In the loops in _get_table_maxdiv(), _get_table_div(), and
_get_table_val(), in drivers/clk/clk-divider.c the exit condition
is .div == 0, so there needs
Am Donnerstag, den 28.03.2013, 22:22 +0800 schrieb Shawn Guo:
On Thu, Mar 28, 2013 at 10:05:18AM +0100, Philipp Zabel wrote:
+
+ ocram: ocram@f800 {
+ compatible = fsl,imx-ocram, mmio-sram;
We should probably just drop fsl,imx-ocram
So it can be used in clk-imx6q.c for revision dependent clock tree setup.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-imx6q.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/common.h
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx51-imx53.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx6q.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Steffen Trumtrar s.trumt...@pengutronix.de
Add ldb device tree node and clock lookups.
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v2:
- Removed clocks properties from imx6qdl.dtsi,
those are to be set
Query silicon revision to determine clock tree and add post
dividers for newer revisions.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v2:
- Renamed pll[45]_test_div to pll[45]_post_div
- Renamed pll5_control3 to pll5_video_div
- Reformatted clk_div_tables
- Added
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx53.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 7a6f5a8..b07bbdcc 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53
On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v2:
- Renamed pll5_control3
s.ha...@pengutronix.de
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v2:
- Removed commented out code
- Replaced magic constants
- Select OF_VIDEOMODE
---
.../devicetree/bindings/staging/imx-drm/ldb.txt| 99
drivers/staging/imx-drm/Kconfig
Hi,
the following patches add support for LVDS displays on
i.MX53 and i.MX6q boards. I have reordered the patches,
as Shawn has already applied the now first five patches.
The clock patches are needed because the LVDS serial clock
needs to be in lockstep with the IPU display interface clock
The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk.h | 17
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx51.dtsi| 2 ++
arch/arm/boot/dts/imx53.dtsi| 2 ++
arch/arm/mach-imx/clk-imx51-imx53.c | 7 ---
3 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm
[Added Arnd and Greg to the recipients] I think the first three patches
of this series are candidates to go through Arnd's tree. Arnd, would you
take those patches?
[PATCH v6 1/8] dt: describe base reset signal binding
[PATCH v6 2/8] reset: Add reset controller API
[PATCH
to request a framework API to issue a
reset simply by providing their struct device pointer as the most common
case.
Signed-off-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
Reviewed-by: Marek Vasut ma...@denx.de
This driver implements a reset controller device that toggles gpios
connected to reset pins of peripheral ICs. The delay between assertion
and de-assertion of the reset signal can be configured.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
Reviewed-by: Shawn Guo shawn@linaro.org
Request the System Reset Controller to reset the IPU if
specified via device tree phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
Reviewed-by: Marek Vasut ma...@denx.de
---
.../devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
Reviewed-by: Marek Vasut ma...@denx.de
---
arch/arm/boot/dts/imx6q.dtsi | 1 +
arch/arm/boot/dts/imx6qdl.dtsi | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b
Also, link SRC to IPU via phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
Reviewed-by: Marek Vasut ma...@denx.de
---
arch/arm/boot/dts/imx51.dtsi | 7 +++
arch/arm/boot/dts/imx53.dtsi | 7 +++
2 files changed, 14 insertions
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
Reviewed-by: Marek Vasut ma...@denx.de
---
arch/arm/boot/dts
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren
Am Mittwoch, den 20.03.2013, 11:52 +0100 schrieb Philipp Zabel:
Hi, last time I posted was a bit close to the merge window, so I'm
reposting now. Greg, Arnd, could you take the first two patches?
Ping,
can I do anything to help move this along?
regards
Philipp
These patches add support
Hi Marek,
thanks for the review.
Am Dienstag, den 26.03.2013, 22:13 +0100 schrieb Marek Vasut:
Dear Pavel Machek,
Hi!
The system reset controller (SRC) on i.MX51, i.MX53, and i.MX6q controls
reset lines to the GPU, VPU, IPU, and OpenVG IP modules.
The following patches add a
This patch adds the missing GPU2D and GPU3D mux and gate clocks,
and the graphics arbiter gate clock.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Documentation/devicetree/bindings/clock/imx5-clock.txt | 5 +
arch/arm/mach-imx/clk-imx51-imx53.c| 9 -
2
Hi Martin,
Am Mittwoch, den 27.03.2013, 12:54 +0100 schrieb Martin Fuzzey:
Hi Philipp,
On 26/03/13 15:13, Philipp Zabel wrote:
+static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
+{
+ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+ struct imx_ldb
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx51.dtsi| 2 ++
arch/arm/boot/dts/imx53.dtsi| 2 ++
arch/arm/mach-imx/clk-imx51-imx53.c | 7 ---
3 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx53.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 7a6f5a8..b07bbdcc 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx6q.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx53.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index b07bbdcc..30aed40 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b
Hi,
the following patches add support for LVDS displays on
i.MX53 and i.MX6q boards.
The clock patches are needed because the LVDS serial clock
needs to be in lockstep with the IPU display interface clock
providing the pixel data. A fixed factor of 7:1 (or 3.5:1 in
dual link mode) needs to be
So it can be used in clk-imx6q.c for revision dependent clock tree setup.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-imx6q.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/common.h
From: Steffen Trumtrar s.trumt...@pengutronix.de
Add ldb device tree node and clock lookups.
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx6q.dtsi | 17 +
arch/arm/boot/dts/imx6qdl.dtsi
The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk.h | 17
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx51-imx53.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions
Query silicon revision to determine clock tree and add post
dividers for newer revisions.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx6q.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-imx
s.ha...@pengutronix.de
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v1:
- Added device-tree bindings documentation
- Removed remains of GPIO handling
---
.../devicetree/bindings/staging/imx-drm/ldb.txt| 99
drivers/staging/imx-drm/Kconfig
From: Steffen Trumtrar s.trumt...@pengutronix.de
Add ldb device tree node and clock lookups.
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx6q.dtsi | 17 +
arch/arm/boot/dts/imx6qdl.dtsi
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx51.dtsi| 2 ++
arch/arm/boot/dts/imx53.dtsi| 2 ++
arch/arm/mach-imx/clk-imx51-imx53.c | 7 ---
3 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm
The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk.h | 17
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx53.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 7a6f5a8..b07bbdcc 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53
So it can be used in clk-imx6q.c for revision dependent clock tree setup.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-imx6q.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/common.h
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx51-imx53.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx53.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index b07bbdcc..30aed40 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b
On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx6q.c | 5 +
1
s.ha...@pengutronix.de
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/staging/imx-drm/Kconfig | 7 +
drivers/staging/imx-drm/Makefile | 1 +
drivers/staging/imx-drm/imx-ldb.c | 614 ++
3 files changed, 622 insertions(+)
create mode
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx6q.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Query silicon revision to determine clock tree and add post
dividers for newer revisions.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx6q.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-imx
Hi,
the following patches add support for LVDS displays on
i.MX53 and i.MX6q boards.
The clock patches are needed because the LVDS serial clock
has to be in lockstep with the IPU display interface clock
providing the pixel data. A fixed factor of 7:1 (or 3.5:1 in
dual link mode) needs to be
Hi Thomas,
Am Dienstag, den 26.03.2013, 15:34 +0100 schrieb Thomas Petazzoni:
Dear Philipp Zabel,
On Tue, 26 Mar 2013 15:13:56 +0100, Philipp Zabel wrote:
+/*
+ * For a device declaring compatible = fsl,imx6q-ldb, fsl,imx53-ldb,
+ * of_match_device will walk through this list and take
The system reset controller (SRC) on i.MX51, i.MX53, and i.MX6q controls
reset lines to the GPU, VPU, IPU, and OpenVG IP modules.
The following patches add a simple API for devices to request being reset
by separate reset controller hardware and implements the reset signal
device tree binding
Request the System Reset Controller to reset the IPU if
specified via device tree phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
.../devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt | 3 +++
drivers/staging/imx-drm/ipu-v3
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
arch/arm/mach-imx/Kconfig
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren
1 - 100 of 186 matches
Mail list logo
