Hi Patrick,
> On second thoughts, I wonder if they could be talking about generating
> a "device tree".
Which sounds plausible, thanks. Grant Likely was heavily involved in
Device Tree's addition to Linux on ARM and it's a declarative
description of common hardware on embedded systems so it
On Sun, 23 Feb 2020 11:38:04 +, Ralph Corderoy wrote:
> A test plan that can be executed?
That was my first thought, but I'm not aware of any kind of testing
that might use the abbreviation "DT".
On second thoughts, I wonder if they could be talking about generating
a "device tree".
At
Hi Terry,
> I'm not skilled in the art of PCB design, but my partially informed guess
> would be 'Drilling Template' layer.
Thanks for the informed guess. :-) I think the Gerber file can contain
information about a drilling layer, or if not some other CNC-related
format. And ‘drilling
On Sunday, 23 February 2020 11:14:43 GMT Terry Coles wrote:
> I'm not skilled in the art of PCB design, but my partially informed guess
> would be 'Drilling Template' layer.
On re-reading the original discussion, I see that the reference is to a DT
file, rather than a
DT Layer. In the context
On Sunday, 23 February 2020 10:49:42 GMT Ralph Corderoy wrote:
> Anyway, the point of this email is one of the Q about fifty minutes
> referred to what sounded like a ‘DT layer’ and I don't know what that
> is.
I'm not skilled in the art of PCB design, but my partially informed guess
would be
Hi,
I recently watched ‘Hardware Design for Linux Engineers’, 52 minutes,
https://www.youtube.com/watch?v=ziHhcBoRjQk. It was okay, more
interesting towards the end where the programmer talked about the issues
he'd had with his hardware design, like getting oscillations from his
transparent
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