Re: [Doxygen-users] VHDL: how to include elements of a record (and the associated comment)?

2015-04-28 Thread mkk
I posted Dimitri a patch for this issue checkout and compile the current GIT repository documenting a record should now work. --! \brief description for a type, which actually is a record type my_record_1 is record element_11 : std_logic; --! comment for first element of my_rec

Re: [Doxygen-users] VHDL Blocks

2014-11-18 Thread mkk
try --! \brief This is my process comment.\n --! \n --! Why isn't this in a code block? -- View this message in context: http://doxygen.10944.n7.nabble.com/VHDL-Blocks-tp6910p6923.html Sent from the Doxygen - Users mailing list archive at Nabble.com. --

Re: [Doxygen-users] VHDL: functions only in package body not shown

2014-10-26 Thread mkk
I posted Dimitri a patch for this bug -- View this message in context: http://doxygen.10944.n7.nabble.com/VHDL-functions-only-in-package-body-not-shown-tp6857p6871.html Sent from the Doxygen - Users mailing list archive at Nabble.com. ---

Re: [Doxygen-users] VHDL: comment on first element in package header displayed with package comment

2014-10-26 Thread mkk
I posted Dimitri a patch for this bug -- View this message in context: http://doxygen.10944.n7.nabble.com/VHDL-comment-on-first-element-in-package-header-displayed-with-package-comment-tp6858p6872.html Sent from the Doxygen - Users mailing list archive at Nabble.com. --

Re: [Doxygen-users] Doxygen with Graphviz to document VHDL files

2013-03-16 Thread mkk
--! @dot --! digraph example { --! node [shape=record, fontname=Helvetica, fontsize=10,color="red"]; --! DataExtract [ label="Entity CDR_Top" URL="\ref CDR_Top"]; --! Serial_In -> Ser2Par; --! Ser2Par -> DataExtract; --! } --! @enddot see http://www.stack.nl/~dimitri/doxygen/manual/commands.ht

Re: [Doxygen-users] vhdlflow command

2013-01-29 Thread mkk
1. don't make comments which are starting with --! inside sequential statements ! 2. if you make some comments inside your vhdlflow example try this: PROC_TEST_FLOW : process (p_Clk) --# PROC_TEST_FLOW ... --# p_Clk -> clock begin --# Reset all signals and variables to safe condition

Re: [Doxygen-users] Comments in VHDL Process

2013-01-28 Thread mkk
It is a bug and should be fixed in the next update. --! @brief Process 4to manage reception of nrzi bits --! {ws} --! Gets bits from the data recovery component and performs nrzidecoding. --! {ws} --! @param[in] p_DataClk Clock, used on rising edge a simple white