[Bug 42490] NUTMEG DP to VGA bridge not working

https://bugs.freedesktop.org/show_bug.cgi?id=42490 Alex Deucher changed: What|Removed |Added AssignedTo|xorg-driver-ati at lists.x.org |dri-devel at lists.freedesktop

[Bug 31943] drm EDID checking is too strict

https://bugs.freedesktop.org/show_bug.cgi?id=31943 --- Comment #18 from Kai-Uwe Behrmann 2011-11-02 14:27:16 PDT --- Is this duplicate? https://bugs.freedesktop.org/show_bug.cgi?id=32343 -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this

[Bug 28426] hardware cursor corruption with radeon+kms

https://bugs.freedesktop.org/show_bug.cgi?id=28426 --- Comment #9 from Francesco R 2011-11-02 12:39:09 PDT --- sorry, I've switched to nvidia, cannot test -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are

[PATCH 8/8] drm/ttm: introduce callback for ttm_tt populate & unpopulate

From: Jerome Glisse Move the page allocation and freeing to driver callback and provide ttm code helper function for those. Most intrusive change, is the fact that we now only fully populate an object this simplify some of code designed around the page fault design.

[PATCH 7/8] drm/ttm: merge ttm_backend and ttm_tt

From: Jerome Glisse ttm_backend will exist only and only with a ttm_tt, and ttm_tt will be of interesting use only when bind to a backend. Thus to avoid code & data duplication btw the two merge them. Signed-off-by: Jerome Glisse --- drivers/gpu/drm/nouveau/nouveau_bo.c

[PATCH 6/8] drm/ttm: test for dma_address array allocation failure

From: Jerome Glisse Signed-off-by: Jerome Glisse --- drivers/gpu/drm/ttm/ttm_tt.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 2dd45ca..58ea7dc 100644 ---

[PATCH 5/8] drm/ttm: convert page allocation to use page ptr array instead of list V2

From: Jerome Glisse Use the ttm_tt page ptr array for page allocation, move the list to array unwinding into the page allocation functions. V2 split the fix to use ttm put page as a separate fix properly fill pages array when TTM_PAGE_FLAG_ZERO_ALLOC is not set

[PATCH 4/8] drm/ttm: use ttm put pages function to properly restore cache attribute

From: Jerome Glisse On failure we need to make sure the page we free has wb cache attribute. Do this pas call the proper ttm page helper function. Signed-off-by: Jerome Glisse --- drivers/gpu/drm/ttm/ttm_tt.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-)

[PATCH 3/8] drm/ttm: remove unused backend flags field

From: Jerome Glisse This field is not use by any of the driver just drop it. Signed-off-by: Jerome Glisse Reviewed-by: Konrad Rzeszutek Wilk --- drivers/gpu/drm/radeon/radeon_ttm.c |1 - include/drm/ttm/ttm_bo_driver.h |2 -- 2 files changed, 0 insertions(+),

[PATCH 2/8] drm/ttm: remove split btw highmen and lowmem page

From: Jerome Glisse Split btw highmem and lowmem page was rendered useless by the pool code. Remove it. Note further cleanup would change the ttm page allocation helper to actualy take an array instead of relying on list this could drasticly reduce the number of function call

[PATCH 1/8] drm/ttm: remove userspace backed ttm object support

From: Jerome Glisse This was never use in none of the driver, properly using userspace page for bo would need more code (vma interaction mostly). Removing this dead code in preparation of ttm_tt & backend merge. Signed-off-by: Jerome Glisse Reviewed-by: Konrad Rzeszutek

[RFC] ttm merge ttm_backend & ttm_t V2

Hi, So attached is last batch of patch, i split the ttm put page fix and i fixed a bug in the pages alloc when clear flags wasn't set. I tested them on a bunch of radeon and everythings seems fine (several gl app, firefox, compositor ...). I will do more testing on agp and nouveau tomorrow. The

[Bug 35460] [855GM] Corruptions with linux-2.6.38 & xf-video-intel-2.14.901

https://bugs.freedesktop.org/show_bug.cgi?id=35460 --- Comment #12 from Bruno 2011-11-02 11:24:34 PDT --- (In reply to comment #10 with patch from comment #11) > Created attachment 52920 [details] [review] > > Test-feedback highly appreciated. Running now for two days with the patch, no

[PATCH] drm/radeon/kms: don't poll forever if MC GDDR link training fails

From: Alex Deucher Bail if we hit the timeout limit. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ni.c |7 +-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index

[Bug 41592] [Radeon] The display often freezes with gnome-shell 3.2

https://bugs.freedesktop.org/show_bug.cgi?id=41592 Michel D?nzer changed: What|Removed |Added Status|RESOLVED|VERIFIED --- Comment #18 from Michel

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

On 11/2/11 5:13 PM, Keith Packard wrote: > On Wed, 02 Nov 2011 16:35:51 -0400, Adam Jackson wrote: > >> It is? The DP 1.1a text for lane count is "For Rev.1.1, only the >> following three values are supported. All other values are reserved." > > Yeah, if you look at the MAX_LINK_RATE field, we

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

On 11/2/11 4:05 PM, Keith Packard wrote: > On Wed, 02 Nov 2011 15:36:20 -0400, Adam Jackson wrote: > >> The VBT is going to be crap. > > The only question then is what to do with hardware that doesn't have the > DPCD value -- that's "new" in revision 0x11, after all. It is? The DP 1.1a text for

[Bug 41971] [kms] Muxless radeon takes 20 seconds to fetch rom

https://bugs.freedesktop.org/show_bug.cgi?id=41971 --- Comment #13 from Mike Lothian 2011-11-02 09:02:00 PDT --- Is there a way for switcheroo to detect a muxless laptop and automatically switch it off (if it isn't already) -- Configure bugmail:

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

On 11/2/11 1:31 PM, Keith Packard wrote: > On Wed, 02 Nov 2011 13:13:52 -0400, Adam Jackson wrote: > >> Given the choice of trusting DPCD or the VBT, I'd definitely prefer >> DPCD. > > Except that the DPCD is coded into the monitor while the VBT is done by > the platform. And, it's the platform

[PATCH 1/5] drm: add plane support

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[PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

On Wed, Nov 2, 2011 at 2:54 PM, Keith Packard wrote: > On Tue, ?1 Nov 2011 23:20:26 -0700, Keith Packard > wrote: > >> ? ? ? ? ? ? ? intel_dp = enc_to_intel_dp(encoder); >> - ? ? ? ? ? ? if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { >> + ? ? ? ? ? ? if (intel_dp->base.type ==

[PATCH] drm/radeon/kms: fix DP setup on TRAVIS bridges

From: Alex Deucher Supposedly both NUTMEG and TRAVIS should use the same panel mode, but switching the panel mode for TRAVIS gets things working. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=41569 Signed-off-by: Alex Deucher ---

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

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[Bug 42514] [r300g] EVE online: some shaders are failing

https://bugs.freedesktop.org/show_bug.cgi?id=42514 --- Comment #3 from Pavel Ondra?ka 2011-11-02 06:43:44 PDT --- Forgot to mention, GPU is RV530. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the

[Bug 42514] [r300g] EVE online: some shaders are failing

https://bugs.freedesktop.org/show_bug.cgi?id=42514 --- Comment #2 from Pavel Ondra?ka 2011-11-02 06:42:30 PDT --- Created attachment 53054 --> https://bugs.freedesktop.org/attachment.cgi?id=53054 RADEON_DEBUG=fp log -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email

[Bug 42514] [r300g] EVE online: some shaders are failing

https://bugs.freedesktop.org/show_bug.cgi?id=42514 --- Comment #1 from Pavel Ondra?ka 2011-11-02 06:42:01 PDT --- Created attachment 53053 --> https://bugs.freedesktop.org/attachment.cgi?id=53053 terminal output -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email

[Bug 42514] New: [r300g] EVE online: some shaders are failing

https://bugs.freedesktop.org/show_bug.cgi?id=42514 Bug #: 42514 Summary: [r300g] EVE online: some shaders are failing Classification: Unclassified Product: Mesa Version: git Platform: Other OS/Version: All Status: NEW

[Bug 41971] [kms] Muxless radeon takes 20 seconds to fetch rom

https://bugs.freedesktop.org/show_bug.cgi?id=41971 --- Comment #12 from Alex Deucher 2011-11-02 06:37:47 PDT --- (In reply to comment #11) > > When no module is loaded is the card still drawing power? It depends whether the bios turns it on by default or not. If it's off, you are not drawing

[Bug 41971] [kms] Muxless radeon takes 20 seconds to fetch rom

https://bugs.freedesktop.org/show_bug.cgi?id=41971 --- Comment #11 from Mike Lothian 2011-11-02 06:29:06 PDT --- I've removed the vgaswitcheroo and radeon options from my kernel and my boot time has returned to normal, as I have a muxless laptop not having the card available makes no difference

[Bug 38554] Hibernate broken when KMS enabled on Radeon Mobility M6 LY

https://bugs.freedesktop.org/show_bug.cgi?id=38554 --- Comment #1 from Orion Poplawski 2011-11-02 13:14:53 UTC --- I seem to be hitting exactly the same problem in Fedora 16 with 3.1.0-5.fc16.i686. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

On 11/2/11 12:20 PM, Jesse Barnes wrote: > @@ -766,10 +766,10 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct > drm_display_mode *mode, > continue; > > intel_dp = enc_to_intel_dp(encoder); > - if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)

[RFC] ttm merge ttm_backend & ttm_tt

> > I don't know why it was done that way, but I wrote the TTM DMA code > > to be optimized for that (and it has the code to reverse direction - b/c > > the testcases I used initially had the a,b,c,d,e,f order when doing > > get_pages > > and put_pages) - but I can alter the code to do it in the

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

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[PATCH 5/5] drm/i915: add destination color key support

Add new ioctls for getting and setting the current destination color key. This allows for simple overlay display control by matching a color key value in the primary plane before blending the overlay on top. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_dma.c |2 +

[PATCH 4/5] drm/i915: add SNB and IVB video sprite support

The video sprites support various video surface formats natively and can handle scaling as well. So add support for them using the new DRM core overlay support functions. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/Makefile |1 + drivers/gpu/drm/i915/i915_reg.h |

[PATCH 3/5] drm/i915: rename existing overlay support to "legacy"

The old overlay block has all sorts of quirks and is very different than ILK+ video sprites. So rename it to legacy to make that clear and clash less with core overlay support. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_debugfs.c |2 +- drivers/gpu/drm/i915/i915_drv.h

[PATCH 2/5] drm: add an fb creation ioctl that takes a pixel format

To properly support the various plane formats supported by different hardware, the kernel must know the pixel format of a framebuffer object. So add a new ioctl taking a format argument corresponding to a fourcc name from videodev2.h. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/drm_crtc.c

[PATCH 1/5] drm: add plane support

Planes are a bit like half-CRTCs. They have a location and fb, but don't drive outputs directly. Add support for handling them to the core KMS code. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/drm_crtc.c | 236 +++- drivers/gpu/drm/drm_drv.c |

[PATCH] DRM planes

In response to feedback, I've adjusted the new addfb2 ioctl to take per component pitch and offset args. Generally, the offset[0] field will be 0, but it's conceivable that some metadata could be stored at the start of a given buffer, and an offset[0] allows the client to skip past that.

[RFC] ttm merge ttm_backend & ttm_tt

On Wed, Nov 02, 2011 at 11:04:43AM -0400, Konrad Rzeszutek Wilk wrote: > On Tue, Nov 01, 2011 at 09:11:37PM -0400, Jerome Glisse wrote: > > Hi, > > > > So attached is patch serie (sorry for that i am away of my normal mail > > config) which ultimately merge ttm_backend & ttm_tt it allows to get >

[Bug 40024] Power management does not work on ATI Mobility Radeon 9700

https://bugs.freedesktop.org/show_bug.cgi?id=40024 --- Comment #7 from Andrew Randrianasulu 2011-11-02 05:15:55 PDT --- from #nouveau channel: http://people.freedesktop.org/~cbrill/dri-log/index.php?channel=nouveau_html=true_names==2011-08-19 15:53 #nouveau: < MaximLevitsky> mupuf:

[PATCH] drm/radeon: set hpd polarity at init time so hotplug detect works

On Wed, Nov 2, 2011 at 10:27 AM, Jerome Glisse wrote: > On Tue, Nov 01, 2011 at 05:27:26PM -0400, Alex Deucher wrote: >> On Fri, Oct 28, 2011 at 5:52 PM, ? wrote: >> > From: Jerome Glisse >> > >> > Polarity needs to be set accordingly to connector status (connected >> > or disconnected). Set it

[PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

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[PATCH] DRM: EXYNOS: Add EXYNOS DRM maintainer entry

From: Kyungmin Park As Exynos DRM is merged at mainline. Also update the maintainer entry. Signed-off-by: Kyungmin Park --- diff --git a/MAINTAINERS b/MAINTAINERS index 5d6941f..1deeac9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2327,6 +2327,13 @@ S:

[Bug 40024] Power management does not work on ATI Mobility Radeon 9700

https://bugs.freedesktop.org/show_bug.cgi?id=40024 --- Comment #6 from Andrew Randrianasulu 2011-11-02 04:31:12 PDT --- for memtimings on radeon 7500 (changed via rovclock, while running proprietary driver) see forum post here and down :

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

On 11/2/11 2:20 AM, Keith Packard wrote: > + if (intel_dp->link_configuration [1] & > DP_LANE_COUNT_ENHANCED_FRAME_EN) > + intel_dp->DP |= DP_ENHANCED_FRAMING; > + > + /* > + * Check for DPCD version> 1.1 and enhanced framing support > +

RFC: Radeon multi ring support branch

On 31.10.2011 16:05, Jerome Glisse wrote: > On Sat, Oct 29, 2011 at 03:00:28PM +0200, Christian K?nig wrote: >> Hello everybody, >> >> to support multiple compute rings, async DMA engines and UVD we need >> to teach the radeon kernel module how to sync buffers between >> different rings and make

[RFC] ttm merge ttm_backend & ttm_tt

On Tue, Nov 01, 2011 at 09:11:37PM -0400, Jerome Glisse wrote: > Hi, > > So attached is patch serie (sorry for that i am away of my normal mail > config) which ultimately merge ttm_backend & ttm_tt it allows to get > rid of data duplication btw the two, especialy btw ttm_tt and driver > specific

[Bug 28426] hardware cursor corruption with radeon+kms

https://bugs.freedesktop.org/show_bug.cgi?id=28426 --- Comment #8 from Michel D?nzer 2011-11-02 03:53:49 PDT --- Kernel 3.0.7 has one HW cursor fix, 3.1 has more and other HW cursor changes. Do any of those help? -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email

[PATCH 6/7] drm/i915: Try harder during dp pattern 1 link training

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[Intel-gfx] [PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

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[Bug 39272] Ridiculous performances with HD5870

https://bugs.freedesktop.org/show_bug.cgi?id=39272 --- Comment #1 from Andrew Randrianasulu 2011-11-02 03:28:48 PDT --- Try patch from https://bugs.freedesktop.org/show_bug.cgi?id=38917 ? -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this

[PATCH] drm/radeon: set hpd polarity at init time so hotplug detect works

On Tue, Nov 01, 2011 at 05:27:26PM -0400, Alex Deucher wrote: > On Fri, Oct 28, 2011 at 5:52 PM, wrote: > > From: Jerome Glisse > > > > Polarity needs to be set accordingly to connector status (connected > > or disconnected). Set it up at module init so first hotplug works > > reliably no

RFC: Radeon multi ring support branch

On Wed, Nov 02, 2011 at 11:12:42AM +0100, Christian K?nig wrote: > On 31.10.2011 16:05, Jerome Glisse wrote: > >On Sat, Oct 29, 2011 at 03:00:28PM +0200, Christian K?nig wrote: > >>Hello everybody, > >> > >>to support multiple compute rings, async DMA engines and UVD we need > >>to teach the

[PATCH 6/7] drm/i915: Try harder during dp pattern 1 link training

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[Intel-gfx] [PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

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[PATCH 5/5] vmwgfx: Fix hw cursor position

Signed-off-by: Thomas Hellstrom Reviewed-by: Jakob Bornecrantz --- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |7 +-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 1cebf64..5ccce1c 100644 ---

[PATCH 4/5] vmwgfx: Infrastructure for explicit placement

Make it possible to use explicit placement (although not hooked up with a user-space interface yet) and relax the single framebuffer limit to only apply to implicit placement. Signed-off-by: Thomas Hellstrom Reviewed-by: Jakob Bornecrantz --- drivers/gpu/drm/vmwgfx/vmwgfx_kms.h |1 +

[PATCH 3/5] vmwgfx: Make the preferred autofit mode have a 60Hz vrefresh

Signed-off-by: Thomas Hellstrom Reviewed-by: Jakob Bornecrantz --- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 24 +++- 1 files changed, 23 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index

[PATCH 2/5] vmwgfx: Remove screen object active list

It isn't used for anything. Replace with an active bool. Also make a couple of functions return void instead of int since their return value wasn't checked anyway. Signed-off-by: Thomas Hellstrom Reviewed-by: Jakbo Bornecrantz --- drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c | 52

[PATCH 1/5] vmwgfx: Screen object cleanups

Remove unused member. No need to pin / unpin fb. Signed-off-by: Thomas Hellstrom Reviewed-by: Jakob Bornecrantz --- drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c | 16 ++-- 1 files changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c

[PATCH -fixes 0/5] vmwgfx fixes

The patch series was intended to be preceded by this mail. A bunch of fixes for 3.2 for vmwgfx. /Thomas

[Intel-gfx] [PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

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[Intel-gfx] [PATCH 2/7] drm/i915: Remove link_status field from intel_dp structure

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[Intel-gfx] [PATCH 1/7] drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control

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[PATCH 6/7] drm/i915: Try harder during dp pattern 1 link training

On Tue, 1 Nov 2011 23:20:29 -0700, Keith Packard wrote: > Instead of going through the sequence just once, run through the whole > set up to 5 times to see if something can work. This isn't part of the > DP spec, but the BIOS seems to do it, and given that link training > failure is so bad, it

[Intel-gfx] [PATCH 1/7] drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control

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[PATCH] vmwgfx: Reinstate the update_layout ioctl

Dave, I saw the other two patches going into drm-fixes-staging, but this one was not included. It's pretty important because it fixes fighting when setting monitor topology between gnome-settings-daemon and the vmware-user daemon. Thanks Thomas On 10/25/2011 11:35 PM, Thomas Hellstrom

[Bug 28426] hardware cursor corruption with radeon+kms

https://bugs.freedesktop.org/show_bug.cgi?id=28426 J?rg Billeter changed: What|Removed |Added CC||j at bitron.ch --- Comment #7 from J?rg

[RFC] ttm merge ttm_backend & ttm_tt

On 11/02/2011 02:11 AM, Jerome Glisse wrote: > Hi, > > So attached is patch serie (sorry for that i am away of my normal mail > config) which ultimately merge ttm_backend& ttm_tt it allows to get > rid of data duplication btw the two, especialy btw ttm_tt and driver > specific backend. So net

[Bug 42435] Suspected loss of varyings between shaders

https://bugs.freedesktop.org/show_bug.cgi?id=42435 --- Comment #13 from Alexander Sabourenkov 2011-11-02 00:41:39 PDT --- Yes, thank you. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for

[Bug 42435] Suspected loss of varyings between shaders

https://bugs.freedesktop.org/show_bug.cgi?id=42435 --- Comment #12 from Vadim 2011-11-01 21:56:03 PDT --- Created attachment 53033 --> https://bugs.freedesktop.org/attachment.cgi?id=53033 [PATCH] r600g: take into account PSIZE output for spi mapping Does this patch help? -- Configure

[Bug 40024] Power management does not work on ATI Mobility Radeon 9700

https://bugs.freedesktop.org/show_bug.cgi?id=40024 --- Comment #5 from Andrew Randrianasulu 2011-11-02 04:00:35 UTC --- Probably bad advice, but what if user executes rovclock [1] on top of KMS ? [1] - http://www.thinkwiki.org/wiki/Rovclock - has some info about min. clocks Also, not

[Bug 42435] Suspected loss of varyings between shaders

https://bugs.freedesktop.org/show_bug.cgi?id=42435 --- Comment #11 from Alexander Sabourenkov 2011-11-01 18:41:06 PDT --- Problem manifests itself only when gl_PointSize is set in the shader. Corrected patch attached. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email

[Bug 42435] Suspected loss of varyings between shaders

https://bugs.freedesktop.org/show_bug.cgi?id=42435 Alexander Sabourenkov changed: What|Removed |Added Attachment #53030|0 |1 is obsolete|

[Bug 42435] Suspected loss of varyings between shaders

https://bugs.freedesktop.org/show_bug.cgi?id=42435 Alexander Sabourenkov changed: What|Removed |Added Attachment #53029|0 |1 is obsolete|

[Bug 42435] Suspected loss of varyings between shaders

https://bugs.freedesktop.org/show_bug.cgi?id=42435 --- Comment #8 from Alexander Sabourenkov 2011-11-01 17:54:54 PDT --- Created attachment 53029 --> https://bugs.freedesktop.org/attachment.cgi?id=53029 piglit test case for the problem -- Configure bugmail:

[Bug 42435] Suspected loss of varyings between shaders

https://bugs.freedesktop.org/show_bug.cgi?id=42435 --- Comment #7 from Alexander Sabourenkov 2011-11-01 17:53:45 PDT --- Further reducing shaders I got to this point: #version 120 #line 2 0 varying float idx; void main() { vec2 posn2 = posz*posn; idx = 0.625; gl_Position =

[Bug 42435] Suspected loss of varyings between shaders

https://bugs.freedesktop.org/show_bug.cgi?id=42435 --- Comment #6 from Alexander Sabourenkov 2011-11-01 17:31:52 PDT --- Created attachment 53028 --> https://bugs.freedesktop.org/attachment.cgi?id=53028 xterm corruption screenshot xterm corruption screenshot, got it right after I first run

[PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

E_STATE_ON_IDLE) -- keith.packard at intel.com -- next part -- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 827 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/2002/5aa8566a/attachment.pgp>

[RFC] ttm merge ttm_backend & ttm_tt

On Tue, Nov 01, 2011 at 11:05:49PM -0400, Jerome Glisse wrote: > On Tue, Nov 1, 2011 at 9:29 PM, Konrad Rzeszutek Wilk > wrote: > > On Tue, Nov 01, 2011 at 09:11:37PM -0400, Jerome Glisse wrote: > >> Hi, > >> > >> So attached is patch serie (sorry for that i am away of my normal mail > >> config)

[PATCH 7/7] drm/i915: Remove trailing white space

Found a couple of bare tabs in intel_dp.c Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_dp.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bf20a35..7ebeb01 100644 ---

[PATCH 6/7] drm/i915: Try harder during dp pattern 1 link training

Instead of going through the sequence just once, run through the whole set up to 5 times to see if something can work. This isn't part of the DP spec, but the BIOS seems to do it, and given that link training failure is so bad, it seems reasonable to follow suit. Signed-off-by: Keith Packard ---

[PATCH 5/7] drm/i915: Make DP prepare/commit consistent with DP dpms

Make sure the sequence of operations in all three functions makes sense: 1) The backlight must be off unless the screen is running 2) The link must be running to turn the eDP panel on/off 3) The CPU eDP PLL must be running until everything is off Signed-off-by: Keith Packard ---

[PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

The panel power sequencing hardware tracks the stages of panel power sequencing and signals when the panel is completely on or off. Instead of blindly assuming the panel timings will work, poll the panel power status register until it shows the correct values. Signed-off-by: Keith Packard ---

[PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

PCH eDP has many of the same needs as regular PCH DP connections, including the DP_CTl bit settings, the TRANS_DP_CTL register. Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_display.c |3 +- drivers/gpu/drm/i915/intel_dp.c | 112 -- 2

[PATCH 2/7] drm/i915: Remove link_status field from intel_dp structure

No persistent data was ever stored here, so link_status is instead allocated on the stack as needed. Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_dp.c | 65 +- 1 files changed, 36 insertions(+), 29 deletions(-) diff --git

[PATCH 1/7] drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control

Every usage of PCH_PP_CONTROL sets the PANEL_UNLOCK_REGS value to ensure that writes will be respected, move this to a common function to make the driver cleaner. No functional changes. Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_dp.c | 37

[PATCH 0/7] drm/i915: Fix PCH eDP support for SNB

Here's a patch sequence which makes my PCH-connected eDP panel work. The main bug was a pile of places where the driver was incorrectly treating a PCH connected eDP panel like a CPU connected eDP panel, setting incorrect bits in the DP_CTL register and failing to configure the TRANS_DP_CTL

[RFC] ttm merge ttm_backend & ttm_tt

On Tue, Nov 1, 2011 at 9:29 PM, Konrad Rzeszutek Wilk wrote: > On Tue, Nov 01, 2011 at 09:11:37PM -0400, Jerome Glisse wrote: >> Hi, >> >> So attached is patch serie (sorry for that i am away of my normal mail >> config) which ultimately merge ttm_backend & ttm_tt it allows to get >> rid of data

[PATCH 0/7] drm/i915: Fix PCH eDP support for SNB

Here's a patch sequence which makes my PCH-connected eDP panel work. The main bug was a pile of places where the driver was incorrectly treating a PCH connected eDP panel like a CPU connected eDP panel, setting incorrect bits in the DP_CTL register and failing to configure the TRANS_DP_CTL

[PATCH 1/7] drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control

Every usage of PCH_PP_CONTROL sets the PANEL_UNLOCK_REGS value to ensure that writes will be respected, move this to a common function to make the driver cleaner. No functional changes. Signed-off-by: Keith Packard kei...@keithp.com --- drivers/gpu/drm/i915/intel_dp.c | 37

[PATCH 5/7] drm/i915: Make DP prepare/commit consistent with DP dpms

Make sure the sequence of operations in all three functions makes sense: 1) The backlight must be off unless the screen is running 2) The link must be running to turn the eDP panel on/off 3) The CPU eDP PLL must be running until everything is off Signed-off-by: Keith Packard kei...@keithp.com

[PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

The panel power sequencing hardware tracks the stages of panel power sequencing and signals when the panel is completely on or off. Instead of blindly assuming the panel timings will work, poll the panel power status register until it shows the correct values. Signed-off-by: Keith Packard

[PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

PCH eDP has many of the same needs as regular PCH DP connections, including the DP_CTl bit settings, the TRANS_DP_CTL register. Signed-off-by: Keith Packard kei...@keithp.com --- drivers/gpu/drm/i915/intel_display.c |3 +- drivers/gpu/drm/i915/intel_dp.c | 112

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