[PATCH] drm: bridge: dw-hdmi: add ASoC dependency

The newly added sound driver depends on SND_SOC_HDMI_CODEC, which in turn only makes sense when ASoC is enabled, as shown by this warning: warning: (DRM_MSM && DRM_STI && DRM_MEDIATEK_HDMI && DRM_I2C_NXP_TDA998X && DRM_DW_HDMI_I2S_AUDIO) selects SND_SOC_HDMI_CODEC which has unmet direct

Enabling peer to peer device transactions for PCIe devices

Am 25.11.2016 um 20:32 schrieb Jason Gunthorpe: > On Fri, Nov 25, 2016 at 02:22:17PM +0100, Christian König wrote: > >>> Like you say below we have to handle short lived in the usual way, and >>> that covers basically every device except IB MRs, including the >>> command queue on a NVMe drive. >>

Question regarding clocks in the DW-HDMI DT bindings

Hi Philipp, On Friday 25 Nov 2016 17:08:13 Philipp Zabel wrote: > Am Freitag, den 25.11.2016, 17:45 +0200 schrieb Laurent Pinchart: > > On Friday 25 Nov 2016 10:56:55 Philipp Zabel wrote: > >> Am Donnerstag, den 24.11.2016, 23:16 +0200 schrieb Laurent Pinchart: > >>> Hi Andy, > >>> > >>> As the

[Bug 98005] VCE dual instance encoding inconsistent since st/va: enable dual instances encode by sync surface

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[Bug 90202] Firefox nightly hangs with accelerated layers and latest r600 driver

nts/20161125/c576c659/attachment.html>

[Bug 92996] [Fiji/amdgpu/Powerplay] Problems with interactivity, performance, EQ overflow with Powerplay

dri-devel/attachments/20161125/1212152b/attachment.html>

[Bug 98239] saints row 3: performance is limited by flushes

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[PATCH V3 2/3] dt-bindings: mxsfb: Add new bindings for the MXSFB driver

On 11/16/2016 01:21 PM, Marek Vasut wrote: > Add new DT bindings for new MXSFB driver that is using the > OF graph to parse the video output structure instead of > hard-coding the display properties into the MXSFB node. > The old MXSFB fbdev driver bindings are preserved in the > same file in the

Enabling peer to peer device transactions for PCIe devices

On Fri, Nov 25, 2016 at 2:34 PM, Jason Gunthorpe wrote: > On Fri, Nov 25, 2016 at 12:16:30PM -0500, Serguei Sagalovitch wrote: > >> b) Allocation may not have CPU address at all - only GPU one. > > But you don't expect RDMA to work in the case, right? > > GPU people need to stop doing this

[PATCH v10 13/13] drm/mediatek: add support for Mediatek SoC MT2701

This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 8 drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 6 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 17

[PATCH v10 12/13] drm/mediatek: update DSI sub driver flow for sending commands to panel

This patch update enable/disable flow of DSI module. Original flow works on there is a bridge chip: DSI -> bridge -> panel. In this case: DSI -> panel, the DSI sub driver flow should be updated. We need to initialize DSI first so that we can send commands to panel. Signed-off-by: shaoming chen

[PATCH v10 11/13] drm/mediatek: add dsi rxtx control

add non-continuous clock mode and EOT packet control for dsi Signed-off-by: shaoming chen Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index

[PATCH v10 10/13] drm/mediatek: add dsi ulp mode control

modify dsi enter ultra low power mode method Signed-off-by: shaoming chen Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index

[PATCH v10 09/13] drm/mediatek: add mipi_tx data rate check

modify data rate limitation (>lGbps/lane) for mipitx Signed-off-by: shaoming chen Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c

[PATCH v10 08/13] drm/mediatek: add dsi transfer function

From: shaoming chen add dsi read/write commands for transfer function Signed-off-by: shaoming chen --- drivers/gpu/drm/mediatek/mtk_dsi.c | 168 - 1 file changed, 166 insertions(+), 2 deletions(-) diff --git

[PATCH v10 07/13] drm/mediatek: add dsi interrupt control

From: shaoming chen add dsi interrupt control Signed-off-by: shaoming chen --- drivers/gpu/drm/mediatek/mtk_dsi.c | 92 ++ 1 file changed, 92 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c

[PATCH v10 06/13] drm/mediatek: cleaning up and refine

cleaning up unused define and refine function name and variable Signed-off-by: shaoming chen Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_dsi.c | 77 -- drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 8 ++-- 2 files changed, 41 insertions(+), 44

[PATCH v10 05/13] drm/mediatek: update display module connections

update connections for OVL, RDMA, BLS, DSI Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 + 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index b77d456..a9b209c

[PATCH v10 04/13] drm/mediatek: add BLS component

Add BLS component for PWM + GAMMA function Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 5 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

[PATCH v10 03/13] drm/mediatek: add shadow register support

We need to acquire mutex before using the resources, and need to release it after finished. So we don't need to write registers in the blanking period. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 76 -

[PATCH v10 02/13] drm/mediatek: add *driver_data for different hardware settings

There are some hardware settings changed, between MT8173 & MT2701: DISP_OVL address offset changed, color format definition changed. DISP_RDMA fifo size changed. DISP_COLOR offset changed. MIPI_TX pll setting changed. And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod. Signed-off-by: YT

[PATCH v10 01/13] drm/mediatek: add helpers for coverting from the generic components

define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_ovl' define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_rdma' Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 +-- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 15 +-- 2

[PATCH v10 00/13] MT2701 DRM support

This is MT2701 DRM support PATCH v10, based on 4.9-rc1. We add DSI interrupt control, transfer function for MIPI DSI panel support. Most codes are the same, except some register changed. For example: - DISP_OVL address offset changed, color format definition changed. - DISP_RDMA fifo size

[PATCH v6 3/5] ARM: dts: sun8i-h3: add HDMI video nodes

25.11.2016, 18:22, "Jean-Francois Moine" : > On Fri, 25 Nov 2016 17:41:51 +0800 > Icenowy Zheng wrote: > >>  After removing CLK_PLL_DE's assigned-clock, the kernel passes compilation. > > The 'pll-de' and 'de' must have a fixed rate. Otherwise, if you do not > use the legacy u-boot, I don't

Question regarding clocks in the DW-HDMI DT bindings

Hi Fabio, On Friday 25 Nov 2016 13:29:37 Fabio Estevam wrote: > On Fri, Nov 25, 2016 at 1:22 PM, Laurent Pinchart wrote: > >> I got the clock name from I.MX6Q TRM, I also checked the name again > >> with Rockchip IC design team now, hope to get some new information soon. > > > > Thank you. While

Question regarding clocks in the DW-HDMI DT bindings

Hi Philipp, On Friday 25 Nov 2016 10:56:55 Philipp Zabel wrote: > Am Donnerstag, den 24.11.2016, 23:16 +0200 schrieb Laurent Pinchart: > > Hi Andy, > > > > As the author of the DW-HDMI DT bindings this question is addressed to > > you, but information from anyone is more than welcome. > > > >

[PATCH v6 3/5] ARM: dts: sun8i-h3: add HDMI video nodes

20.11.2016, 20:12, "Jean-Francois Moine" : > Signed-off-by: Jean-Francois Moine > --- >  arch/arm/boot/dts/sun8i-h3.dtsi | 51 > + >  1 file changed, 51 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi >

Question regarding clocks in the DW-HDMI DT bindings

Hi Andy, On Friday 25 Nov 2016 10:56:53 Andy Yan wrote: > On 2016年11月25日 07:26, Laurent Pinchart wrote: > > On Friday 25 Nov 2016 00:16:00 Vladimir Zapolskiy wrote: > >> On 11/25/2016 12:07 AM, Fabio Estevam wrote: > >>> On Thu, Nov 24, 2016 at 7:16 PM, Laurent Pinchart wrote: > Hi

[Bug 98856] Dirt: Showdown broken graphics

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Question regarding clocks in the DW-HDMI DT bindings

Am Freitag, den 25.11.2016, 17:45 +0200 schrieb Laurent Pinchart: > Hi Philipp, > > On Friday 25 Nov 2016 10:56:55 Philipp Zabel wrote: > > Am Donnerstag, den 24.11.2016, 23:16 +0200 schrieb Laurent Pinchart: > > > Hi Andy, > > > > > > As the author of the DW-HDMI DT bindings this question is

[PATCH 3/3] ARM: dts: da850: enable the memctrl and mstpri nodes per board

Currently the memory controller and master priorities drivers are enabled in da850.dtsi. For boards for which there are no settings defined, this makes these drivers emit error messages. Disable the nodes in da850.dtsi and only enable them for da850-lcdk - the only board that currently needs

[PATCH 2/3] ARM: dts: da850: specify the maximum bandwidth for tilcdc

It has been determined that the maximum resolution supported correctly by tilcdc rev1 on da850 SoCs is 800x600 at 60. Due to memory throughput constraints we must filter out higher modes. Specify the max-bandwidth property for the display node for da850-based boards. Signed-off-by: Bartosz

[PATCH 1/3] ARM: da850-lcdk: add the dumb-vga-dac node

Add the dumb-vga-dac node to the board DT together with corresponding ports and vga connector. This allows to retrieve the edid info from the display automatically. Signed-off-by: Bartosz Golaszewski --- arch/arm/boot/dts/da850-lcdk.dts | 58

[PATCH 0/3] ARM: dts: da850: tilcdc related DT changes

I previously sent these patches separately, but since they're touching the same files while coming from different trees, I decided to post it again in a series to make applying them easier. Bartosz Golaszewski (3): ARM: da850-lcdk: add the dumb-vga-dac node ARM: dts: da850: specify the

[RFC PATCH 3/3] dt-bindings: display: add Amlogic Meson DRM Bindings

Signed-off-by: Neil Armstrong --- .../bindings/display/meson/meson-drm.txt | 134 + 1 file changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/meson/meson-drm.txt diff --git

[RFC PATCH 2/3] ARM64: dts: meson-gx: Add Graphic Controller nodes

Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 46 ++ .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts| 4 ++

[RFC PATCH 1/3] drm: Add support for Amlogic Meson Graphic Controller

The Amlogic Meson Display controller is composed of several components : DMC|---VPU (Video Processing Unit)|--HHI--| | vd1 ___ __ | | D |---| ||| |||

[RFC PATCH 0/3] drm: Add support for the Amlogic Video Processing Unit

The Amlogic Meson SoCs embeds a Video Processing Unit able to output at least a Composite/CVBS Video with embedded VDAC and an HDMI Link with Embedded HDMI Transceiver. Thus, the current driver does not support HDMI yet. The Video Processig Unit is composed of multiple modules like the Video

[PATCH 6/6] drm: mali-dp: Add writeback connector

Mali-DP has a memory writeback engine which can be used to write the composition result to a memory buffer. Expose this functionality as a DRM writeback connector on supported hardware. Changes since v1: Daniel Vetter: - Don't require a modeset when writeback routing changes - Make writeback

[PATCH 5/6] drm: mali-dp: Add RGB writeback formats for DP550/DP650

Add a layer bit for the SE memory-write, and add it to the pixel format matrix for DP550/DP650. Signed-off-by: Brian Starkey --- drivers/gpu/drm/arm/malidp_hw.c | 28 ++-- drivers/gpu/drm/arm/malidp_hw.h |1 + 2 files changed, 15 insertions(+), 14 deletions(-)

[PATCH 4/6] drm: mali-dp: Add support for writeback on DP550/DP650

From: Liviu Dudau Mali-DP display processors are able to write the composition result to a memory buffer via the SE. Add entry points in the HAL for enabling/disabling this feature, and implement support for it on DP650 and DP550. DP500 acts differently and so is omitted

[PATCH 3/6] drm: mali-dp: Rename malidp_input_format

We're going to use the same format list for output formats, so rename everything related to input formats to avoid confusion. Signed-off-by: Brian Starkey Reviewed-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_hw.c | 24 drivers/gpu/drm/arm/malidp_hw.h |

[PATCH 2/6] drm: writeback: Add out-fences for writeback connectors

Add the OUT_FENCE_PTR property to writeback connectors, to enable userspace to get a fence which will signal once the writeback is complete. It is not allowed to request an out-fence without a framebuffer attached to the connector. A timeline is added to drm_writeback_connector for use by the

[PATCH 1/6] drm: Add writeback connector type

Writeback connectors represent writeback engines which can write the CRTC output to a memory framebuffer. Add a writeback connector type and related support functions. Drivers should initialize a writeback connector with drm_writeback_connector_init() which takes care of setting up all the

[RFC PATCH v3 0/6] Introduce writeback connectors

Hi, This is v3 of my series introducing a new connector type: DRM_MODE_CONNECTOR_WRITEBACK See v1 and v2 here: [1] [2] Writeback connectors are used to expose the memory writeback engines found in some display controllers, which can write a CRTC's composition result to a memory buffer. This is

[PATCH] ARM: dts: da850: specify the maximum bandwidth for tilcdc

It has been determined that the maximum resolution supported correctly by tilcdc rev1 on da850 SoCs is 800x600 at 60. Due to memory throughput constraints we must filter out higher modes. Specify the max-bandwidth property for the display node for da850-based boards. Signed-off-by: Bartosz

[GIT PULL] Another HDLCD fix

Hi Dave, Thanks for pulling the previous patch for HDLCD. Unfortunately, yesterday Robin Murphy discovered another issue while playing with CMA allocation sizes, which he has submitted a fix for. If you think it is too late for this to go into v4.9, please let me know. Many thanks, Liviu The

Enabling peer to peer device transactions for PCIe devices

On 16-11-25 03:40 PM, Christian König wrote: > Am 25.11.2016 um 20:32 schrieb Jason Gunthorpe: >> This assumes the commands are fairly short lived of course, the >> expectation of the mmu notifiers is that a flush is reasonably prompt > > Correct, this is another problem. GFX command submissions

Enabling peer to peer device transactions for PCIe devices

On 2016-11-25 03:26 PM, Felix Kuehling wrote: > On 16-11-25 12:20 PM, Serguei Sagalovitch wrote: >>> A white list may end up being rather complicated if it has to cover >>> different CPU generations and system architectures. I feel this is a >>> decision user space could easily make. >>> >>>

Question regarding clocks in the DW-HDMI DT bindings

On 11/25/2016 03:06 PM, Fabio Estevam wrote: > Hi Vladimir, > > On Fri, Nov 25, 2016 at 11:00 AM, Vladimir Zapolskiy > wrote: > >> according to the DTSI files in the vanilla kernel DW HDMI IP is found >> only on iMX6Q/D and iMX6DL/iMX6S SoCs (but please double check it), >> so this approach

[PATCH 3/3] drm: Track framebuffer references at the point of assignment

We can simplify the code greatly if both legacy and atomic paths updated the references as they assigned the framebuffer to the planes. Long before framebuffer reference counting was added, the code had to keep the old_fb around until after the operation was completed - but now we can simply leave

[PATCH 2/3] drm: Introduce drm_framebuffer_assign()

In a couple of places currently, and with the intent to add more, we update a pointer to a framebuffer to hold a new fb reference (evicting the old). Signed-off-by: Chris Wilson --- drivers/gpu/drm/drm_atomic.c | 8 ++-- include/drm/drm_framebuffer.h | 18 ++ 2 files

[PATCH 1/3] drm/i915: Use helper for setting plane->state->fb

We are told not to set plane_state->fb directly, but use drm_atomic_set_fb_for_plane() instead. Using the helper, means one less piece of code that needs fixing should the interface change... Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 6 +- 1 file changed, 1

Enabling peer to peer device transactions for PCIe devices

On 16-11-25 12:20 PM, Serguei Sagalovitch wrote: > >> A white list may end up being rather complicated if it has to cover >> different CPU generations and system architectures. I feel this is a >> decision user space could easily make. >> >> Logan > I agreed that it is better to leave up to user

Question regarding clocks in the DW-HDMI DT bindings

Hi Fabio, On Friday 25 Nov 2016 10:43:04 Fabio Estevam wrote: > On Thu, Nov 24, 2016 at 9:26 PM, Laurent Pinchart wrote: > > Another question I have about the bus clock (CC'ing the devicetree mailing > > list as well as the clock maintainers) is whether it should be made > > optional. The clock

Question regarding clocks in the DW-HDMI DT bindings

Hi Fabio, On 11/25/2016 02:29 PM, Fabio Estevam wrote: > Hi Vladimir, > > On Thu, Nov 24, 2016 at 8:16 PM, Vladimir Zapolskiy > wrote: > >> By the way while we're discussing DW HDMI bindings specific to iMX, >> I would recommend to remove utterly hackish and iMX only "gpr" >> property from the

[PATCH] drm: Fixup kernel doc for driver->gem_create_object

On Fri, Nov 25, 2016 at 12:34:27PM +, Chris Wilson wrote: > Silences > > ./include/drm/drm_drv.h:295: warning: Incorrect use of kernel-doc format > > Signed-off-by: Chris Wilson Applied to drm-misc, thanks. -Daniel > --- > include/drm/drm_drv.h | 2 ++ > 1 file changed, 2 insertions(+) >

Enabling peer to peer device transactions for PCIe devices

On 2016-11-25 02:34 PM, Jason Gunthorpe wrote: > On Fri, Nov 25, 2016 at 12:16:30PM -0500, Serguei Sagalovitch wrote: > >> b) Allocation may not have CPU address at all - only GPU one. > But you don't expect RDMA to work in the case, right? > > GPU people need to stop doing this windowed memory

[git pull] drm fixes for v4.9-rc7

Hi Linus, Seems to be quietening down nicely, a few mediatek, one exynos and one hdlcd fix, along with 2 amd fixes. Dave. The following changes since commit 9c763584b7c8911106bb77af7e648bef09af9d80: Linux 4.9-rc6 (2016-11-20 13:52:19 -0800) are available in the git repository at:

Enabling peer to peer device transactions for PCIe devices

Am 24.11.2016 um 17:42 schrieb Jason Gunthorpe: > On Wed, Nov 23, 2016 at 06:25:21PM -0700, Logan Gunthorpe wrote: >> >> On 23/11/16 02:55 PM, Jason Gunthorpe wrote: > Only ODP hardware allows changing the DMA address on the fly, and it > works at the page table level. We do not need

Enabling peer to peer device transactions for PCIe devices

On Fri, Nov 25, 2016 at 09:40:10PM +0100, Christian König wrote: > We call this "userptr" and it's just a combination of get_user_pages() on > command submission and making sure the returned list of pages stays valid > using a MMU notifier. Doesn't that still pin the page? > The "big" problem

Enabling peer to peer device transactions for PCIe devices

Am 24.11.2016 um 18:55 schrieb Logan Gunthorpe: > Hey, > > On 24/11/16 02:45 AM, Christian König wrote: >> E.g. it can happen that PCI device A exports it's BAR using ZONE_DEVICE. >> Not PCI device B (a SATA device) can directly read/write to it because >> it is on the same bus segment, but PCI

[Bug 97403] AMDGPU/Iceland Strange warnings on drm-next-4.9-wip

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[Bug 97403] AMDGPU/Iceland Strange warnings on drm-next-4.9-wip

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[Bug 98238] witcher 2: objects are black when changing lod

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Question regarding clocks in the DW-HDMI DT bindings

On Fri, Nov 25, 2016 at 1:22 PM, Laurent Pinchart wrote: >> I got the clock name from I.MX6Q TRM, I also checked the name again >> with Rockchip IC design team now, hope to get some new information soon. > > Thank you. While at it, could you ask them which version of the DW HDMI IP > used in the

[linux-sunxi] [PATCH v6 3/5] ARM: dts: sun8i-h3: add HDMI video nodes

20.11.2016, 20:07, "Jean-Francois Moine" : > Signed-off-by: Jean-Francois Moine > --- >  arch/arm/boot/dts/sun8i-h3.dtsi | 51 > + >  1 file changed, 51 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi >

Enabling peer to peer device transactions for PCIe devices

On Fri, Nov 25, 2016 at 02:49:50PM -0500, Serguei Sagalovitch wrote: > GPU could perfectly access all VRAM. It is only issue for p2p without > special interconnect and CPU access. Strictly speaking as long as we > have "bus address" we could have RDMA but I agreed that for > RDMA we

[Intel-gfx] v4.9-rc3: graphical artefacts in X

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[Bug 98238] witcher 2: objects are black when changing lod

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Enabling peer to peer device transactions for PCIe devices

> Well, I guess there's some consensus building to do. The existing > options are: > > * Device DAX: which could work but the problem I see with it is that it > only allows one application to do these transfers. Or there would have > to be some user-space coordination to figure which application

[Bug 98238] witcher 2: objects are black when changing lod

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Enabling peer to peer device transactions for PCIe devices

On Thu, Nov 24, 2016 at 11:58:17PM -0800, Christoph Hellwig wrote: > On Thu, Nov 24, 2016 at 11:11:34AM -0700, Logan Gunthorpe wrote: > > * Regular DAX in the FS doesn't work at this time because the FS can > > move the file you think your transfer to out from under you. Though I > > understand

[PATCH] drm: Fixup kernel doc for driver->gem_create_object

Silences ./include/drm/drm_drv.h:295: warning: Incorrect use of kernel-doc format Signed-off-by: Chris Wilson --- include/drm/drm_drv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h index aad8bbacd1f0..52bf44e2b5cc 100644 ---

Enabling peer to peer device transactions for PCIe devices

On Fri, Nov 25, 2016 at 12:16:30PM -0500, Serguei Sagalovitch wrote: > b) Allocation may not have CPU address at all - only GPU one. But you don't expect RDMA to work in the case, right? GPU people need to stop doing this windowed memory stuff :) Jason

Enabling peer to peer device transactions for PCIe devices

On Fri, Nov 25, 2016 at 02:22:17PM +0100, Christian König wrote: > >Like you say below we have to handle short lived in the usual way, and > >that covers basically every device except IB MRs, including the > >command queue on a NVMe drive. > > Well a problem which wasn't mentioned so far is

Enabling peer to peer device transactions for PCIe devices

> A white list may end up being rather complicated if it has to cover > different CPU generations and system architectures. I feel this is a > decision user space could easily make. > > Logan I agreed that it is better to leave up to user space to check what is working and what is not. I found

Enabling peer to peer device transactions for PCIe devices

On 2016-11-25 08:22 AM, Christian König wrote: > >> Serguei, what is your plan in GPU land for migration? Ie if I have a >> CPU mapped page and the GPU moves it to VRAM, it becomes non-cachable >> - do you still allow the CPU to access it? Or do you swap it back to >> cachable memory if the CPU

[PATCH v4 00/10] drm/tilcdc: LCDC Revision 1 related fixes

2016-11-25 10:09 GMT+01:00 Jyri Sarha : > The git branch bellow is updated. > > Changes since v3: > - "drm/tilcdc: Enable sync lost error and recovery handling for rev 1 LCDC" > - disable sync-lost irq also for rev1 LCDC > - LCDC_V1_SYNC_LOST_ENA to LCDC_V1_SYNC_LOST_INT_ENA > - "drm/tilcdc:

[PATCH v5 0/4] drm/tilcdc: Add bridge support and sync-lost flood recovery

2016-11-25 10:02 GMT+01:00 Jyri Sarha : > Changes since v4: > - "drm/bridge: Add ti-tfp410 DVI transmitter driver" > - Put i2c behind #if IS_ENABLED(CONFIG_I2C) > - "drm/tilcdc: Add drm bridge support for attaching drm bridge drivers" > - Use exsisting infrastructure to hookup crtc mode

[Bug 188621] Function kfd_wait_on_events() does not set error code when the call to copy_from_user() fails

https://bugzilla.kernel.org/show_bug.cgi?id=188621 --- Comment #1 from Oded Gabbay --- I'll look into it. Thanks for the bug. Oded -- You are receiving this mail because: You are watching the assignee of the bug.

[PATCH v6 3/5] ARM: dts: sun8i-h3: add HDMI video nodes

On Fri, 25 Nov 2016 17:41:51 +0800 Icenowy Zheng wrote: > After removing CLK_PLL_DE's assigned-clock, the kernel passes compilation. The 'pll-de' and 'de' must have a fixed rate. Otherwise, if you do not use the legacy u-boot, I don't know which can be the rate of the DE. > However, it cannot

[Bug 98239] saints row 3: performance is limited by flushes

tps://lists.freedesktop.org/archives/dri-devel/attachments/20161125/258169b4/attachment.html>

[PATCH v4 10/10] drm/tilcdc: Enable frame done irq and functionality for LCDC rev 1

We should wait for the last frame to complete before shutting things down also on LCDC rev 1. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 18 +++--- drivers/gpu/drm/tilcdc/tilcdc_regs.h | 1 + 2 files changed, 12 insertions(+), 7 deletions(-) diff --git

[PATCH v4 09/10] drm/tilcdc: Configure video mode to HW in enable() not in mode_set_nofb()

Configure video mode to HW in enable() call back. There is no reason to do it before that. This makes PM functions way easier because there is no HW context to save when screen is for instance blanked. This patch removes mode_set_nofb() call back from tilcdc. Signed-off-by: Jyri Sarha ---

[PATCH v4 08/10] drm/tilcdc: Load palette at the end of mode_set_nofb()

Load palette at the end of mode_set_nofb(). Moving the palette loading to mode_set_nofb() saves us from storing and restoring of framebuffer addresses in dma registers that were just recently written there. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 25

[PATCH v4 07/10] drm/tilcdc: Add timeout wait for palette loading to complete

Add timeout wait for palette loadind to complete. We do not want to hang forever if palette loaded interrupt does not arrive for some reason. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git

[PATCH v4 06/10] drm/tilcdc: Enable palette loading for revision 2 LCDC too

The LCDC revision 2 documentation also mentions the mandatory palette for true color modes. Even if the rev 2 LCDC appears to work just fine without the palette being loaded loading it helps in testing the feature. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 90

[PATCH v4 05/10] drm/tilcdc: Fix load mode bit-field setting in tilcdc_crtc_enable()

Set LCDC_PALETTE_LOAD_MODE bit-field with new tilcdc_write_mask() instead of tilcdc_set(). Setting a bit-fields with tilcdc_set() is fundamentally broken. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH v4 04/10] drm/tilcdc: Add tilcdc_write_mask() to tilcdc_regs.h

Add tilcdc_write_mask() for handling register field wider than one bit and mask values for those fields. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_regs.h | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_regs.h

[PATCH v4 03/10] drm/tilcdc: Fix tilcdc_crtc_create() return value handling

Failed tilcdc_crtc_create() error handling was broken, this patch should fix it. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 12 +++- drivers/gpu/drm/tilcdc/tilcdc_drv.c | 11 --- drivers/gpu/drm/tilcdc/tilcdc_drv.h | 2 +- 3 files changed, 12

[PATCH v4 02/10] drm/tilcdc: implement palette loading for rev1

From: Bartosz Golaszewski Revision 1 of the IP doesn't work if we don't load the palette (even if it's not used, which is the case for the RGB565 format). Add a function called from tilcdc_crtc_enable() which performs all required actions if we're dealing with a rev1

[PATCH v4 01/10] drm/tilcdc: Enable sync lost error and recovery handling for rev 1 LCDC

Revision 1 LCDC support also sync lost errors and can benefit from sync lost recovery routine. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 35 --- drivers/gpu/drm/tilcdc/tilcdc_regs.h | 1 + 2 files changed, 21 insertions(+), 15

[PATCH v4 00/10] drm/tilcdc: LCDC Revision 1 related fixes

The git branch bellow is updated. Changes since v3: - "drm/tilcdc: Enable sync lost error and recovery handling for rev 1 LCDC" - disable sync-lost irq also for rev1 LCDC - LCDC_V1_SYNC_LOST_ENA to LCDC_V1_SYNC_LOST_INT_ENA - "drm/tilcdc: Enable palette loading for revision 2 LCDC too" -

[Bug 188911] New: Function qxl_release_alloc() returns an improper value when the call to kmalloc() fails, resulting in bad memory access

https://bugzilla.kernel.org/show_bug.cgi?id=188911 Bug ID: 188911 Summary: Function qxl_release_alloc() returns an improper value when the call to kmalloc() fails, resulting in bad memory access Product: Drivers

Question regarding clocks in the DW-HDMI DT bindings

Hi Vladimir, On Fri, Nov 25, 2016 at 11:00 AM, Vladimir Zapolskiy wrote: > according to the DTSI files in the vanilla kernel DW HDMI IP is found > only on iMX6Q/D and iMX6DL/iMX6S SoCs (but please double check it), > so this approach should work ideally. After thinking more about this I think

[PATCH v5 4/4] drm/tilcdc: Add drm bridge support for attaching drm bridge drivers

Adds drm bride support for attaching drm bridge drivers to tilcdc. The decision whether a video port leads to an external encoder or bridge is made simply based on remote device's compatible string. The code has been tested with BeagleBone-Black with and without BeagleBone DVI-D Cape Rev A3 using

[PATCH v5 3/4] drm/bridge: Add ti-tfp410 DVI transmitter driver

Add very basic ti-tfp410 DVI transmitter driver. The only feature separating this from a completely dummy bridge is the EDID read support trough DDC I2C. Even that functionality should be in a separate generic connector driver. However, because of missing DRM infrastructure support the connector

[PATCH v5 2/4] dt-bindings: Move "ti, tfp410.txt" from display/ti to display/bridge

Move "ti,tfp410.txt" from display/ti to display/bridge before adding generic (non omapdrm/dss specific) implementation and new features. Signed-off-by: Jyri Sarha --- Documentation/devicetree/bindings/display/{ti => bridge}/ti,tfp410.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-)

[PATCH v5 1/4] drm/tilcdc: Recover from sync lost error flood by resetting the LCDC

Recover from sync lost error flood by resetting the LCDC instead of turning off the SYNC_LOST error IRQ. When LCDC starves on limited memory bandwidth it may sometimes result an error situation when the picture may have shifted couple of pixels to right and SYNC_LOST interrupt is generated on

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