On 12/18/19 10:52 PM, Dan Williams wrote:
On Wed, Dec 18, 2019 at 9:51 PM John Hubbard wrote:
On 12/18/19 9:27 PM, Dan Williams wrote:
...
@@ -461,5 +449,5 @@ void __put_devmap_managed_page(struct page *page)
page->mapping = NULL;
page->pgmap->ops->page_free(page);
}
On Wed, Dec 18, 2019 at 9:51 PM John Hubbard wrote:
>
> On 12/18/19 9:27 PM, Dan Williams wrote:
> ...
> >> @@ -461,5 +449,5 @@ void __put_devmap_managed_page(struct page *page)
> >> page->mapping = NULL;
> >> page->pgmap->ops->page_free(page);
> >> }
> >>
On 12/18/19 9:27 PM, Dan Williams wrote:
...
@@ -461,5 +449,5 @@ void __put_devmap_managed_page(struct page *page)
page->mapping = NULL;
page->pgmap->ops->page_free(page);
}
-EXPORT_SYMBOL(__put_devmap_managed_page);
+EXPORT_SYMBOL(free_devmap_managed_page);
This patch does
On Mon, Dec 16, 2019 at 2:26 PM John Hubbard wrote:
>
> An upcoming patch changes and complicates the refcounting and
> especially the "put page" aspects of it. In order to keep
> everything clean, refactor the devmap page release routines:
>
> * Rename put_devmap_managed_page() to
On Wed, Dec 18, 2019 at 6:07 PM Dave Airlie wrote:
>
> Hey,
>
> I've pulled in these two patches to drm-next directly because my arm
> test build was broken.
Sounds good.
Alex
>
> Dave.
>
> On Wed, 18 Dec 2019 at 06:47, Alex Deucher wrote:
> >
> > ARM has a 2000us limit for udelay. Switch to
This is a little simpler.
Signed-off-by: Gurchetan Singh
---
drivers/gpu/drm/virtio/virtgpu_drv.h | 8 +---
drivers/gpu/drm/virtio/virtgpu_gem.c | 4 +---
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h
That's the only file that uses it.
Signed-off-by: Gurchetan Singh
---
drivers/gpu/drm/virtio/virtgpu_display.c | 3 +++
drivers/gpu/drm/virtio/virtgpu_drv.h | 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c
Not used anywhere else.
Signed-off-by: Gurchetan Singh
---
drivers/gpu/drm/virtio/virtgpu_display.c | 2 +-
drivers/gpu/drm/virtio/virtgpu_drv.h | 4
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c
Not used anywhere.
Signed-off-by: Gurchetan Singh
---
drivers/gpu/drm/virtio/virtgpu_drv.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h
b/drivers/gpu/drm/virtio/virtgpu_drv.h
index cf09e4af2fc5..3e0580a8d818 100644
---
That's the only file that uses it.
Signed-off-by: Gurchetan Singh
---
drivers/gpu/drm/virtio/virtgpu_drv.h | 2 --
drivers/gpu/drm/virtio/virtgpu_fence.c | 3 +++
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h
Not used anywhere else.
Signed-off-by: Gurchetan Singh
---
drivers/gpu/drm/virtio/virtgpu_drv.h | 1 -
drivers/gpu/drm/virtio/virtgpu_fence.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h
b/drivers/gpu/drm/virtio/virtgpu_drv.h
An upcoming patch changes and complicates the refcounting and
especially the "put page" aspects of it. In order to keep
everything clean, refactor the devmap page release routines:
* Rename put_devmap_managed_page() to page_is_devmap_managed(),
and limit the functionality to "read only": return
On 12/18/19 8:04 AM, Kirill A. Shutemov wrote:
On Mon, Dec 16, 2019 at 02:25:16PM -0800, John Hubbard wrote:
An upcoming patch changes and complicates the refcounting and
especially the "put page" aspects of it. In order to keep
everything clean, refactor the devmap page release routines:
*
Hi Dave,
Just one bug fixup which makes sure to unregister a component
for Exynos gscaler driver.
Please kindly let me know if there is any problem.
Thanks,
Inki Dae
The following changes since commit d1eef1c619749b2a57e514a3fa67d9a516ffa919:
Linux 5.5-rc2 (2019-12-15 15:16:08
On Wed, Dec 18, 2019 at 09:43:49PM +0530, Manna, Animesh wrote:
>
> On 18-12-2019 21:12, Harry Wentland wrote:
> >On 2019-12-18 10:13 a.m., Animesh Manna wrote:
> >>[Why]:
> >>Aligh with DP spec wanted to follow same naming convention.
> >>
> >>[How]:
> >>Changed the macro name of the dpcd
On Tue, Dec 17, 2019 at 08:18:21PM +, Jason Gunthorpe wrote:
On Fri, Dec 13, 2019 at 01:56:04PM -0800, Niranjana Vishwanathapura wrote:
+ ctx = i915_gem_context_lookup(file->driver_priv, args->rsvd1);
+ if (!ctx || !rcu_access_pointer(ctx->vm))
+ return -ENOENT;
+
On Tue, Dec 17, 2019 at 12:01:26PM -0600, Jason Ekstrand wrote:
On Sun, Dec 15, 2019 at 10:24 PM Niranjan Vishwanathapura
wrote:
On Sat, Dec 14, 2019 at 10:31:37AM +, Chris Wilson wrote:
>Quoting Jason Ekstrand (2019-12-14 00:36:19)
>> On Fri, Dec 13, 2019 at 5:24 PM
Hi all,
After merging the amdgpu tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c: In function 'vcn_v2_5_hw_init':
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:288:5: warning: 'r' may be used
uninitialized in this function
Hey,
I've pulled in these two patches to drm-next directly because my arm
test build was broken.
Dave.
On Wed, 18 Dec 2019 at 06:47, Alex Deucher wrote:
>
> ARM has a 2000us limit for udelay. Switch to msleep. This code
> executes in a worker thread so shouldn't be an atomic context.
>
>
On Sun, Dec 15, 2019 at 08:15:24PM -0800, Niranjan Vishwanathapura wrote:
On Sat, Dec 14, 2019 at 10:56:54AM +, Chris Wilson wrote:
Quoting Niranjana Vishwanathapura (2019-12-13 21:56:04)
Shared Virtual Memory (SVM) runtime allocator support allows
binding a shared virtual address to a
On Tue, Dec 17, 2019 at 08:31:07PM +, Jason Gunthorpe wrote:
On Fri, Dec 13, 2019 at 01:56:07PM -0800, Niranjana Vishwanathapura wrote:
+static struct i915_svm *vm_get_svm(struct i915_address_space *vm)
+{
+ struct i915_svm *svm = vm->svm;
+
+ mutex_lock(>svm_mutex);
+ if
On Wed, Dec 18, 2019 at 02:15:53PM -0800, John Hubbard wrote:
> On 12/18/19 7:52 AM, Kirill A. Shutemov wrote:
> > On Mon, Dec 16, 2019 at 02:25:13PM -0800, John Hubbard wrote:
> > > +static void put_compound_head(struct page *page, int refs)
> > > +{
> > > + /* Do a get_page() first, in case refs
Hi,
On Tue, Dec 17, 2019 at 8:03 PM Rob Clark wrote:
>
> > > + for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
> > > + rate_times_200khz = le16_to_cpu(sink_rates[i]);
> > > +
> > > + if (!rate_times_200khz)
> > > +
These two things were in one function. Split into two. This looks
like it's duplicating some code, but don't worry. This is is just in
preparation for future changes.
This is intended to have zero functional change and will just make
future patches easier to understand.
Signed-off-by: Douglas
This series contains a pile of patches that was created to support
hooking up the AUO B116XAK01 panel to the eDP side of the bridge. In
general it should be useful for hooking up a wider variety of DP
panels to the bridge, especially those with lower resolution and lower
bits per pixel.
The
When we iterate over ti_sn_bridge_dp_rate_lut, there's no reason to
start at index 0 which always contains the value 0. 0 is not a valid
link rate.
This change should have no real effect but is a small cleanup.
Signed-off-by: Douglas Anderson
Tested-by: Rob Clark
Reviewed-by: Rob Clark
---
We'll re-organize the ti_sn_bridge_enable() function a bit to group
together all the parts relating to link training and split them into a
sub-function. This is not intended to have any functional change and
is in preparation for trying link training several times at different
rates. One small
The ti-sn65dsi86 is a bridge from MIPI to DP and thus has two links:
the MIPI link and the DP link. The two links do not need to have the
same format or number of lanes. Stop using MIPI variables when
talking about the DP link.
This has zero functional change because:
* currently we are
Based on work by Bjorn Andersson ,
Jeffrey Hugo , and
Rob Clark .
Let's read the SUPPORTED_LINK_RATES and/or MAX_LINK_RATE (depending on
the eDP version of the sink) to figure out what eDP rates are
supported and pick the ideal one.
NOTE: I have only personally tested this code on eDP panels
If we fail training at a lower DP link rate let's now keep trying
until we run out of rates to try. Basically the algorithm here is to
start at the link rate that is the theoretical minimum and then slowly
bump up until we run out of rates or hit the max rate of the sink. We
query the sink using
At least one panel hooked up to the bridge (AUO B116XAK01) only
supports 1 lane of DP. Let's read this information and stop
hardcoding 4 DP lanes.
Signed-off-by: Douglas Anderson
Tested-by: Rob Clark
Reviewed-by: Rob Clark
---
Changes in v3: None
Changes in v2: None
The driver used to say that the value to program into bridge register
0x93 was dp_lanes - 1. Looking at the datasheet for the bridge, this
is wrong. The data sheet says:
* 1 = 1 lane
* 2 = 2 lanes
* 3 = 4 lanes
A more proper way to express this encoding is min(dp_lanes, 3).
At the moment this
The current bridge driver always forced us to use 24 bits per pixel
over the DP link. This is a waste if you are hooked up to a panel
that only supports 6 bits per color or fewer, since in that case you
ran run at 18 bits per pixel and thus end up at a lower DP clock rate.
Let's support this.
On Wed, Dec 18, 2019 at 4:56 AM Gerd Hoffmann wrote:
>
> With shmem helpers allowing to update pgprot caching flags via
> drm_gem_shmem_object.map_cached we can just use that and ditch
> our own implementations of mmap() and vmap().
>
> We also don't need a special case for imported objects, any
On Tue, Dec 17, 2019 at 08:35:47PM +, Jason Gunthorpe wrote:
On Fri, Dec 13, 2019 at 01:56:08PM -0800, Niranjana Vishwanathapura wrote:
@@ -169,6 +170,11 @@ static int i915_range_fault(struct svm_notifier *sn,
return ret;
}
+ /* For
On 12/18/19 7:52 AM, Kirill A. Shutemov wrote:
On Mon, Dec 16, 2019 at 02:25:13PM -0800, John Hubbard wrote:
+static void put_compound_head(struct page *page, int refs)
+{
+ /* Do a get_page() first, in case refs == page->_refcount */
+ get_page(page);
+ page_ref_sub(page,
On 12/18/19 8:19 AM, Kirill A. Shutemov wrote:
...
diff --git a/mm/gup.c b/mm/gup.c
index 3ecce297a47f..c0c56888e7cc 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -29,6 +29,13 @@ struct follow_page_context {
unsigned int page_mask;
};
+static __always_inline long
On Tue, Dec 17, 2019 at 02:46:32PM +0200, Stefan Mavrodiev wrote:
> When the HDMI unbinds drm_connector_cleanup() and drm_encoder_cleanup()
> are called. This also happens when the connector and the encoder are
> destroyed. This double call triggers a NULL pointer exception.
>
> The patch fixes
On Thu, Dec 19, 2019 at 12:40:14AM +0530, Jagan Teki wrote:
> regmap has special API to enable the controller bus clock while
> initializing register space, and current driver is using
> devm_regmap_init_mmio_clk which require to specify bus
> clk_id argument as "bus"
>
> But, the usage of clocks
On Tue, 17 Dec 2019 23:29:05 +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> The XPP055C272 is a 5.5" 720x1280 DSI display.
>
> changes in v4:
> - fix id (Maxime)
> - drop port (Maxime)
> changes in v2:
> - add size info into binding title (Sam)
> - add more required properties (Sam)
>
On Tue, 17 Dec 2019 23:29:04 +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> Shenzhen Xinpeng Technology Co., Ltd produces for example display panels.
>
> Signed-off-by: Heiko Stuebner
> Acked-by: Sam Ravnborg
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1
On Tue, Dec 17, 2019 at 07:01:59PM +0100, H. Nikolaus Schaller wrote:
> The Imagination PVR/SGX GPU is part of several SoC from
> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo
> and others.
>
> With this binding, we describe how the SGX processor is
> interfaced to the SoC
On Sat, Dec 14, 2019 at 09:21:45AM +0100, Sam Ravnborg wrote:
> Hi Allen.
>
> On Tue, Dec 10, 2019 at 01:53:41PM +0800, allen wrote:
> > Add a DT binding documentation for IT6505.
> >
> > Signed-off-by: Allen Chen
> > Signed-off-by: Pi-Hsun Shih
> > ---
> >
On Tue, Dec 17, 2019 at 01:46:00PM +, Fabrizio Castro wrote:
> Add binding for the idk-2121wr LVDS panel from Advantech.
>
> Some panel-specific documentation can be found here:
> https://buy.advantech.eu/Displays/Embedded-LCD-Kits-High-Brightness/model-IDK-2121WR-K2FHA2E.htm
>
>
On Tue, Dec 17, 2019 at 01:46:00PM +, Fabrizio Castro wrote:
> Add binding for the idk-2121wr LVDS panel from Advantech.
>
> Some panel-specific documentation can be found here:
> https://buy.advantech.eu/Displays/Embedded-LCD-Kits-High-Brightness/model-IDK-2121WR-K2FHA2E.htm
>
>
On Wed, Dec 18, 2019 at 3:14 AM Pan Zhang wrote:
>
> this set adds support for removal of gpu drm dead code.
>
> patch3 is similar with patch 1:
> `num` is a data of u8 type and ATOM_MAX_HW_I2C_READ == 255,
>
> so there is a impossible condition '(num > 255) => (0-255 > 255)'.
>
> Signed-off-by:
On Wed, Dec 18, 2019 at 3:13 AM Pan Zhang wrote:
>
> this set adds support for removal of gpu drm dead code.
>
> patch1:
> `num` is a data of u8 type and ATOM_MAX_HW_I2C_READ == 255,
>
> so there is a impossible condition '(num > 255) => (0-255 > 255)'.
>
> Signed-off-by: Pan Zhang
This change
On Wed, Dec 18, 2019 at 10:37 AM Jason Gunthorpe wrote:
>
> I think this is what you are looking for?
I think that with these names, I would have had an easier time reading
the original patch that made me go "Eww", yes.
Of course, now that it's just a rename patch, it's not like the patch
is
The MIPI DSI controller in Allwinner A64 is similar to A33.
But unlike A33, A64 doesn't have DSI_SCLK gating so add compatible
for Allwinner A64 with uninitialized has_mod_clk driver.
Signed-off-by: Jagan Teki
Tested-by: Merlijn Wajer
---
Changes for v13:
- update the changes since has_mod_clk
As per the user manual, look like mod clock is not mandatory
for all Allwinner MIPI DSI controllers, it is connected to
CLK_DSI_SCLK for A31 and not available in A64.
So, add compatible check for A31 and get mod clock accordingly.
Tested-by: Merlijn Wajer
Signed-off-by: Jagan Teki
---
Changes
The MIPI DSI PHY controller on Allwinner A64 is similar
on the one on A31.
Add A64 compatible and append A31 compatible as fallback.
Reviewed-by: Rob Herring
Signed-off-by: Jagan Teki
---
Changes for v13:
- collect Rob review tag
.../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml |
This patch add support for Bananapi S070WV20-CT16 DSI panel to
BPI-M64 board.
DSI panel connected via board DSI port with,
- DLDO1 as VCC-DSI supply
- DCDC1 as VDD supply
- PD7 gpio for lcd enable pin
- PD6 gpio for lcd reset pin
- PD5 gpio for backlight enable pin
Signed-off-by: Jagan Teki
---
The MIPI DSI controller in Allwinner A64 is similar to A33.
But unlike A33, A64 doesn't have DSI_SCLK gating so it is valid
to have separate compatible for A64 on the same driver.
DSI_SCLK uses mod clock-names on dt-bindings, so the same
is not required for A64.
On that note
- A64 require
Add MIPI DSI pipeline for Allwinner A64.
- dsi node, with A64 compatible since it doesn't support
DSI_SCLK gating unlike A33
- dphy node, with A64 compatible with A33 fallback since
DPHY on A64 and A33 is similar
- finally, attach the dsi_in to tcon0 for complete MIPI DSI
Signed-off-by:
This is v13 version for Allwinner A64 MIPI-DSI support
and here is the previous version set[1]
Changes for v13:
- update dt-bindings for A64
- drop has_mod_clk variant
- use regmap bus clock properly
Changes for v12:
- use enum insted of oneOf+const
- handle bus clock using regmap attach clk
-
regmap has special API to enable the controller bus clock while
initializing register space, and current driver is using
devm_regmap_init_mmio_clk which require to specify bus
clk_id argument as "bus"
But, the usage of clocks are varies between different Allwinner
DSI controllers. Clocking in A33
On Wed, 2019-12-18 at 16:21 +0100, Enric Balletbo i Serra wrote:
> Hi Ezequiel,
>
> Many thanks for the review, I am just preparing the next version to send.
>
[..]
> > > +
> > > +#define PAGE1_VSTART 0x6b
> > > +#define PAGE2_SPI_CFG3 0x82
> > > +#define I2C_TO_SPI_RESET
On Sat, 7 Dec 2019 23:47:30 +0100, matthias@kernel.org wrote:
> From: Matthias Brugger
>
> MediaTek mt7623 uses the mt2701 binings as fallback.
> Document this in the binding description.
>
> Signed-off-by: Matthias Brugger
> ---
>
On Wed, Dec 18, 2019 at 6:59 AM Jason Gunthorpe wrote:
>
> Do you think calling it 'mmn_subscriptions' is clear?
Why do you want that "mmn"?
Guys, the "mmn" part is clear from the _context_. The function name is
When the function name is something like "mmu_interval_read_begin()",
and the
On Sat, Dec 07, 2019 at 11:47:29PM +0100, matthias@kernel.org wrote:
> From: Matthias Brugger
>
> The MediaTek DRM has a block called mmsys, which sets
> the routing and enalbes the different blocks.
typo
> This patch adds one line for the mmsys bindings description.
>
> Signed-off-by:
On 2019-12-18 11:13 a.m., Manna, Animesh wrote:
>
> On 18-12-2019 21:12, Harry Wentland wrote:
>> On 2019-12-18 10:13 a.m., Animesh Manna wrote:
>>> [Why]:
>>> Aligh with DP spec wanted to follow same naming convention.
>>>
>>> [How]:
>>> Changed the macro name of the dpcd address used for
On Mon, Dec 16, 2019 at 02:25:18PM -0800, John Hubbard wrote:
> As it says in the updated comment in gup.c: current FOLL_LONGTERM
> behavior is incompatible with FAULT_FLAG_ALLOW_RETRY because of the
> FS DAX check requirement on vmas.
>
> However, the corresponding restriction in
On 18-12-2019 21:12, Harry Wentland wrote:
On 2019-12-18 10:13 a.m., Animesh Manna wrote:
[Why]:
Aligh with DP spec wanted to follow same naming convention.
[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.
Please roll this into your patch that
On Mon, Dec 16, 2019 at 02:25:16PM -0800, John Hubbard wrote:
> An upcoming patch changes and complicates the refcounting and
> especially the "put page" aspects of it. In order to keep
> everything clean, refactor the devmap page release routines:
>
> * Rename put_devmap_managed_page() to
On Mon, Dec 16, 2019 at 02:25:13PM -0800, John Hubbard wrote:
> +static void put_compound_head(struct page *page, int refs)
> +{
> + /* Do a get_page() first, in case refs == page->_refcount */
> + get_page(page);
> + page_ref_sub(page, refs);
> + put_page(page);
> +}
It's not
Hi Neil and Jonas,
Thank you for the patch.
On Wed, Dec 18, 2019 at 04:46:29PM +0100, Neil Armstrong wrote:
> From: Jonas Karlman
>
> Add the max_bpc property to the dw-hdmi connector to prepare support
> for 10, 12 & 16bit output support.
>
> Signed-off-by: Jonas Karlman
> Signed-off-by:
Switch the dw-hdmi driver to drm_bridge_funcs by implementing a new local
bridge, connecting it to the dw-hdmi bridge, then implement the
atomic_get_input_bus_fmts/atomic_get_output_bus_fmts.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 98
This patch adds support for the YUV420 output from the Amlogic Meson SoCs
Video Processing Unit to the HDMI Controller.
The YUV420 is obtained by generating a YUV444 pixel stream like
the classic HDMI display modes, but then the Video Encoder output
can be configured to down-sample the YUV444
From: Jonas Karlman
Add the max_bpc property to the dw-hdmi connector to prepare support
for 10, 12 & 16bit output support.
Signed-off-by: Jonas Karlman
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4
1 file changed, 4 insertions(+)
diff --git
Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negociate
the possible output and input formats for the current mode and monitor,
and use the negotiated formats in a basic atomic_check callback.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 272
This patch adds encoding support for the YUV420 output from the
Amlogic Meson SoCs Video Processing Unit to the HDMI Controller.
The YUV420 is obtained by generating a YUV444 pixel stream like
the classic HDMI display modes, but then the Video Encoder output
can be configured to down-sample the
To allow using formats from negotiation, stop enforcing input_bus_format
in the private dw-plat-data struct.
Signed-off-by: Neil Armstrong
Reviewed-by: Boris Brezillon
---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 1 -
1 file changed, 1 deletion(-)
diff --git
Before switching to bridge funcs, make sure drm_display_mode is passed
as const to the venc functions.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_venc.c | 2 +-
drivers/gpu/drm/meson/meson_venc.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
This patch adds clocking support for the YUV420 output from the
Amlogic Meson SoCs Video Processing Unit to the HDMI Controller.
The YUV420 is obtained by generating a YUV444 pixel stream like
the classic HDMI display modes, but then the Video Encoder output
can be configured to down-sample the
From: Jonas Karlman
Configure the correct mtmdsclock for deep colors to prepare support
for 10, 12 & 16bit output.
Signed-off-by: Jonas Karlman
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +
1 file changed, 17 insertions(+)
diff --git
Now the DW-HDMI Controller supports the HDMI2.0 modes, enable support
for these modes in the connector if the platform supports them.
We limit these modes to DW-HDMI IP version >= 0x200a which
are designed to support HDMI2.0 display modes.
Signed-off-by: Neil Armstrong
---
This patchset is based on Boris's v4 "drm: Add support for bus-format
negotiation" at [1]
patchset to implement full bus-format negotiation for DW-HDMI, including YUV420
support and
10/12/16bit YUV444, YUV422 and RGB. The Color Space Converter support is
already implemented.
And the
On 2019-12-18 10:13 a.m., Animesh Manna wrote:
> [Why]:
> Aligh with DP spec wanted to follow same naming convention.
>
> [How]:
> Changed the macro name of the dpcd address used for getting requested
> test-pattern.
>
Please roll this into your patch that renames the definition. All
patches
On 18/12/2019 16:46, Laurent Pinchart wrote:
Hi Tomi,
On Wed, Dec 18, 2019 at 09:07:52AM +0200, Tomi Valkeinen wrote:
On 18/12/2019 04:03, Laurent Pinchart wrote:
Hopefully we can soon have this series landed so we can start
working on top of the new bridge/connector handling.
I assume it
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.
No functional change.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 +++
These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.
Acked-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git
Send uevent to testapp and set test_active flag. To align with link
compliance design existing intel_dp_compliance tool will be used to
get the phy request in userspace through uevent.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 --
1 file changed, 8
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
As per request from DP phy compliance test few special
test pattern need to set by source. Added function
to set pattern in DP_COMP_CTL register. It will be
called along with other test parameters like vswing,
pre-emphasis programming in atomic_commit_tail path.
Signed-off-by: Animesh Manna
---
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
Note: FIXME tag added as design discusion is ongoing in previous patch
series. Some temporary fix added and the patch is under-development, not for
review.
Signed-off-by: Animesh Manna
---
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1 +
[Why]:
Aligh with DP spec wanted to follow same naming convention.
[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.
Cc: Harry Wentland
Cc: Alex Deucher
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
1 file
During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
v2: As per review feedback from Manasi on RFC version,
- added dp
Driver changes mainly to process the request coming from Test equipment
as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis
Complete auto test suite takes much lesser time than manual run.
Overall design:
--
Automate test request will come to source device as HDP
git://linuxtv.org/pinchartl/media.git tags/du-next-20191218
>
> for you to fetch changes up to c267782c5f0efbd20c560101738e68bb30d4fad5:
>
> drm: rcar-du: Add r8a77980 support (2019-12-18 02:40:29 +0200)
>
> --
Hi Dave and Daniel,
The following changes since commit d1eef1c619749b2a57e514a3fa67d9a516ffa919:
Linux 5.5-rc2 (2019-12-15 15:16:08 -0800)
are available in the Git repository at:
git://linuxtv.org/pinchartl/media.git tags/du-next-20191218
for you to fetch changes up
On Fri, Dec 13, 2019 at 03:38:53PM -0800, Lucas De Marchi wrote:
> On Thu, Nov 07, 2019 at 04:24:13PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä
> >
> >Annoyingly __drm_atomic_helper_crtc_reset() does two
> >totally separate things:
> >a) reset the state to defaults values
> >b) assign
Hi Tomi,
On Wed, Dec 18, 2019 at 09:07:52AM +0200, Tomi Valkeinen wrote:
> On 18/12/2019 04:03, Laurent Pinchart wrote:
> >> Hopefully we can soon have this series landed so we can start
> >> working on top of the new bridge/connector handling.
> >>
> >> I assume it will be applied direct to
Hi Rob,
On Tue, Dec 10, 2019 at 8:12 PM Fabio Estevam wrote:
>
> Booting the adreno driver on a imx53 board leads to the following
> error message:
>
> adreno 3000.gpu: [drm:adreno_gpu_init] *ERROR* Could not find the GPU
> powerlevels
>
> As the "qcom,gpu-pwrlevels" property is optional
On 11/12/2019 00:57, Laurent Pinchart wrote:
The TPD12S015, OPA362 and analog and HDMI connectors are now supported
by DRM bridge drivers, and the omapdrm HDMI and VENC outputs can be
handled through the drm_bridge API. Switch the outputs to drm_bridge by
making the next bridge mandatory and
Hi Enric,
Thank you for the patch.
On Wed, Dec 18, 2019 at 01:12:23PM +0100, Enric Balletbo i Serra wrote:
> Fix the 'manged' typo with 'managed' in the drm_panel_bridge_add
> kernel-doc documentation.
>
> Signed-off-by: Enric Balletbo i Serra
Reviewed-by: Laurent Pinchart
> ---
>
>
Hi Neil,
On Wed, Dec 18, 2019 at 12:55:24PM +0100, Neil Armstrong wrote:
> On 18/12/2019 12:22, Neil Armstrong wrote:
> > On 18/12/2019 01:44, Laurent Pinchart wrote:
> >> On Tue, Dec 17, 2019 at 02:23:57PM +0100, Neil Armstrong wrote:
> >>> On 17/12/2019 13:43, Daniel Vetter wrote:
> On
Add map_cached bool to drm_gem_shmem_object, to request cached mappings
on a per-object base. Check the flag before adding writecombine to
pgprot bits.
Signed-off-by: Gerd Hoffmann
---
include/drm/drm_gem_shmem_helper.h | 5 +
drivers/gpu/drm/drm_gem_shmem_helper.c | 12 +---
With shmem helpers allowing to update pgprot caching flags via
drm_gem_shmem_object.map_cached we can just use that and ditch
our own implementations of mmap() and vmap().
We also don't need a special case for imported objects, any map
requests are handled by the exporter not udl.
Signed-off-by:
virtio-gpu uses cached mappings, set
drm_gem_shmem_object.map_cached accordingly.
Reported-by: Gurchetan Singh
Signed-off-by: Gerd Hoffmann
virtio fixup
---
drivers/gpu/drm/virtio/virtgpu_object.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c
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