> -Original Message-
> From: Lyude Paul
> Sent: Saturday, December 21, 2019 8:12 AM
> To: Lin, Wayne ; dri-devel@lists.freedesktop.org;
> amd-...@lists.freedesktop.org
> Cc: Kazlauskas, Nicholas ; Wentland, Harry
> ; Zuo, Jerry ;
> sta...@vger.kernel.org
> Subject: Re: [PATCH]
On Tue, Dec 24, 2019 at 06:03:50PM -0800, John Hubbard wrote:
> On 12/22/19 5:23 AM, Leon Romanovsky wrote:
> > On Fri, Dec 20, 2019 at 03:54:55PM -0800, John Hubbard wrote:
> > > On 12/20/19 10:29 AM, Leon Romanovsky wrote:
> > > ...
> > > > > $ ./build.sh
> > > > > $ build/bin/run_tests.py
> > >
Hi, Mark:
On Wed, 2019-12-11 at 10:49 -0500, Mark Yacoub wrote:
> drm/mediatek: return if plane pending state is disabled.
>
> If the plane pending state is disabled, call mtk_ovl_layer_off then
> return.
> This guarantees that that the state is valid for all operations when the
> pending state
On 12/22/19 5:23 AM, Leon Romanovsky wrote:
On Fri, Dec 20, 2019 at 03:54:55PM -0800, John Hubbard wrote:
On 12/20/19 10:29 AM, Leon Romanovsky wrote:
...
$ ./build.sh
$ build/bin/run_tests.py
If you get things that far I think Leon can get a reproduction for you
I'm not so optimistic about
Hi Sam,
On Tue, Dec 24, 2019 at 12:31:11PM +0100, Sam Ravnborg wrote:
> > Just a reminder of my 2 proposals:
> >
> > 1/ implement the bridge_ops->pre_enable/post_disable() hooks so you can
> >split your enable/disable logic in 2 parts and make sure things are
> >ready when the panel/next
On Tue, Dec 24, 2019 at 9:30 AM zhengbin wrote:
>
> zhengbin (8):
> drm/amd/display: use true,false for bool variable in dc_link_ddc.c
> drm/amd/display: use true,false for bool variable in
> dcn10_hw_sequencer.c
> drm/amd/display: use true,false for bool variable in dcn20_hwseq.c
>
On Tue, Dec 24, 2019 at 9:30 AM zhengbin wrote:
>
> Fixes coccicheck warning:
>
> drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c:875:1-31: WARNING:
> Assignment of 0/1 to bool variable
>
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
Applied. thanks!
Alex
> ---
>
+ Maxime (Fixed Maxime's email address)
On 23/12/19 5:57 PM, Kishon Vijay Abraham I wrote:
> + Maxime
>
> Hi,
>
> On 23/12/19 12:24 PM, Yuti Amonkar wrote:
>> Allow DisplayPort PHYs to be configured through the generic
>> functions through a custom structure added to the generic union.
>> The
+ Maxime
Hi,
On 23/12/19 12:24 PM, Yuti Amonkar wrote:
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.
The
Hi,
Please note that I don't have access to the displayPort spec, so I'll
only comment on the content of that patch, not whether it's complete
or not.
On Mon, Dec 23, 2019 at 02:41:13PM +0100, Yuti Amonkar wrote:
> Allow DisplayPort PHYs to be configured through the generic
> functions through a
From: Jitao Shi
This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi
Reviewed-by: Daniel Kurtz
[uli: followed API changes, removed FW update feature]
Signed-off-by: Ulrich Hecht
Signed-off-by: Enric Balletbo i Serra
Tested-by: Hsin-Yi Wang
---
One
Satoz is a Chinese TFT manufacturer.
Website: http://www.sat-sz.com/English/index.html
Signed-off-by: Miquel Raynal
Acked-by: Rob Herring
---
Changes since v2:
* None.
Changes since v1:
* Added Rob's Ack.
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:255:2-20: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:267:2-20: WARNING: Assignment of 0/1 to
bool variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
Satoz is a Chinese TFT manufacturer.
Website: http://www.sat-sz.com/English/index.html
Signed-off-by: Miquel Raynal
Acked-by: Rob Herring
---
Changes since v1:
* Added Rob's Ack.
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hi Laurent,
On 23/12/19 15:35, Enric Balletbo i Serra wrote:
> From: Jitao Shi
>
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
> Reviewed-by: Daniel Kurtz
> [uli: followed API changes, removed FW update feature]
> Signed-off-by: Ulrich
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:482:6-14: WARNING:
Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:485:2-10: WARNING:
Assignment of 0/1 to bool variable
Reported-by: Hulk Robot
Signed-off-by:
于 2019年12月24日 GMT+08:00 下午7:28:41, Martin Blumenstingl
写到:
>Hi Alyssa,
>
>On Mon, Dec 16, 2019 at 4:48 PM Alyssa Rosenzweig
> wrote:
>>
>> If so much code is being duplicated over, I'm wondering if it makes
>> sense for us to move some of the common devfreq code to core DRM
>> helpers?
>if you
Fixes coccicheck warning:
drivers/gpu/drm/i915/display/intel_crt.c:1066:1-28: WARNING: Assignment of 0/1
to bool variable
drivers/gpu/drm/i915/display/intel_crt.c:928:2-29: WARNING: Assignment of 0/1
to bool variable
drivers/gpu/drm/i915/display/intel_crt.c:443:2-29: WARNING: Assignment of 0/1
Add support for the Satoz SAT050AT40H12R2 RGB panel.
Signed-off-by: Miquel Raynal
---
Changes since v2:
* Dropped two uneeded lines which would fail the build.
Changes since v1:
* Switched to display_timing's instead of display_mode.
drivers/gpu/drm/panel/panel-simple.c | 26
The panel common bindings provide a gpios-reset property. Let's
support it in the simple driver.
Two fields are added to the panel description structure: the time to
assert the reset and the time to wait right after before starting to
interact with it in any manner. In case these default values
On Mon, Dec 23, 2019 at 04:16:40PM +0100, Yuti Amonkar wrote:
> Document the bindings used for the Cadence MHDP DPI/DP bridge in
> yaml format.
>
> Signed-off-by: Yuti Amonkar
> ---
> .../bindings/display/bridge/cdns,mhdp.yaml | 109
> +
> 1 file changed, 109
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:157:46-64: WARNING: Assignment
of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:159:2-20: WARNING: Assignment
of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:161:46-64:
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:593:6-9: WARNING: Assignment
of 0/1 to bool variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Hello,
Miquel Raynal wrote on Tue, 24 Dec 2019
15:05:51 +0100:
> Add support for the Satoz SAT050AT40H12R2 RGB panel.
>
> Signed-off-by: Miquel Raynal
> ---
>
> Changes since v1:
> * Switched to display_timing's instead of display_mode.
>
> drivers/gpu/drm/panel/panel-simple.c | 28
Hi Nicolas,
On 23/12/19 10:14, Nicolas Boichat wrote:
> On Mon, Dec 23, 2019 at 3:10 PM Enric Balletbo i Serra
> wrote:
>>
>> Hi Nicolas,
>>
>> Many thanks for you review. Just preparing a new version with your comments
>> addressed.
>>
>> On 20/12/19 9:44, Nicolas Boichat wrote:
>>> On Fri, Dec
Updating REG_DSI_LANE_CTRL register value by reading default
register value and writing it back using bitwise OR with
DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST. This works for all panels.
Signed-off-by: Harigovindan P
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 8 +---
1 file changed, 5
zhengbin (7):
drm/radeon: use true,false for bool variable in r100.c
drm/radeon: use true,false for bool variable in si.c
drm/radeon: use true,false for bool variable in r600.c
drm/radeon: use true,false for bool variable in evergreen.c
drm/radeon: use true,false for bool variable in
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:110:6-13:
WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:113:2-9:
WARNING: Assignment of 0/1 to bool variable
Fixes coccicheck warning:
drivers/gpu/drm/radeon/evergreen.c:4948:2-15: WARNING: Assignment of 0/1 to
bool variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/radeon/evergreen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi,
> -Original Message-
> From: Maxime Ripard
> Sent: Monday, December 23, 2019 22:49
> To: Yuti Suresh Amonkar
> Cc: linux-ker...@vger.kernel.org; dri-devel@lists.freedesktop.org;
> prane...@ti.com; tomi.valkei...@ti.com; jsa...@ti.com; Milind Parab
> ; Swapnil Kashinath Jakhade
>
>
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:110:6-13:
WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:113:2-9:
WARNING: Assignment of 0/1 to bool variable
On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port
becomes useless and never responds to cable hotplugging:
[3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon
[3.031945] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port D
Seems like the
On Mon, Dec 16, 2019 at 4:03 AM Chen-Yu Tsai wrote:
>
> On Mon, Dec 16, 2019 at 5:12 AM Martin Blumenstingl
> wrote:
> >
> > This is my attempt at adding devfreq (and cooling device) support to
> > the lima driver.
> > I didn't have much time to do in-depth testing. However, I'm sending
> > this
> On Dec 24, 2019, at 01:36, Jani Nikula wrote:
>
> On Tue, 24 Dec 2019, Kai-Heng Feng wrote:
>> On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port
>> becomes useless and never responds to cable hotplugging:
>> [3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to
Fixes coccicheck warning:
drivers/gpu/drm/radeon/r600.c:3056:2-15: WARNING: Assignment of 0/1 to bool
variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/radeon/r600.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/r600.c
Hi Alyssa,
On Mon, Dec 16, 2019 at 4:48 PM Alyssa Rosenzweig
wrote:
>
> If so much code is being duplicated over, I'm wondering if it makes
> sense for us to move some of the common devfreq code to core DRM
> helpers?
if you have any recommendation where to put it then please let me know
(I am
On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port
becomes useless and never responds to cable hotplugging:
[3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon
[3.031945] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port D
Seems like the
Satoz is a Chinese TFT manufacturer.
Website: http://www.sat-sz.com/English/index.html
Add (simple) bindings for its SAT050AT40H12R2 5.0 inch LCD panel.
Signed-off-by: Miquel Raynal
---
Changes since v1:
* New patch
.../display/panel/satoz,sat050at40h12r2.yaml | 27 +++
1
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3961:1-19: WARNING: Assignment of
0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3981:1-19: WARNING: Assignment of
0/1 to bool variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
---
.../bindings/display/bridge/cdns,mhdp.yaml | 109 +
1 file changed, 109 insertions(+)
create mode 100644
Satoz is a Chinese TFT manufacturer.
Website: http://www.sat-sz.com/English/index.html
Add (simple) bindings for its SAT050AT40H12R2 5.0 inch LCD panel.
Signed-off-by: Miquel Raynal
---
Changes since v2:
* None.
Changes since v1:
* New patch
.../display/panel/satoz,sat050at40h12r2.yaml |
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:253:2-20: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:265:2-20: WARNING: Assignment of 0/1 to
bool variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
On Mon, Dec 16, 2019 at 3:51 AM Qiang Yu wrote:
[...]
> For the code, I think you may need some lock to protect the time records as
> there are two kernel threads gp/pp will try to mark GPU busy and several
> interrupts try to mark GPU idle.
good catch, thank you for this!
I assume the reason is
Add support for the Satoz SAT050AT40H12R2 RGB panel.
Signed-off-by: Miquel Raynal
---
Changes since v1:
* Switched to display_timing's instead of display_mode.
drivers/gpu/drm/panel/panel-simple.c | 28
1 file changed, 28 insertions(+)
diff --git
Fixes coccicheck warning:
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c:875:1-31: WARNING:
Assignment of 0/1 to bool variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Jitao Shi
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
Signed-off-by: Ulrich Hecht
Signed-off-by: Enric Balletbo i Serra
---
I maintained the ack from Rob Herring and the review
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.
The parameters added here are the ones defined in the
Fixes coccicheck warning:
drivers/gpu/drm/radeon/cik.c:8140:2-15: WARNING: Assignment of 0/1 to bool
variable
drivers/gpu/drm/radeon/cik.c:8212:2-15: WARNING: Assignment of 0/1 to bool
variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/radeon/cik.c | 4 ++--
1 file
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:132:2-10: WARNING: Assignment of
0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:140:2-10: WARNING: Assignment of
0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:142:13-21: WARNING:
Fixes coccicheck warning:
drivers/gpu/drm/i915/display/intel_dp.c:4950:1-33: WARNING: Assignment of 0/1
to bool variable
drivers/gpu/drm/i915/display/intel_dp.c:4906:1-33: WARNING: Assignment of 0/1
to bool variable
Reported-by: Hulk Robot
Signed-off-by: Ma Feng
---
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c:4124:3-28:
WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c:4128:5-30:
WARNING: Assignment of 0/1 to bool variable
+Kishon
Thanks & Regards,
Yuti Amonkar
> -Original Message-
> From: Yuti Amonkar
> Sent: Monday, December 23, 2019 19:11
> To: linux-ker...@vger.kernel.org; dri-devel@lists.freedesktop.org;
> max...@cerno.tech
> Cc: prane...@ti.com; tomi.valkei...@ti.com; jsa...@ti.com; Milind Parab
> ;
Fixes coccicheck warning:
drivers/gpu/drm/radeon/r100.c:1826:3-31: WARNING: Assignment of 0/1 to bool
variable
drivers/gpu/drm/radeon/r100.c:1828:3-31: WARNING: Assignment of 0/1 to bool
variable
drivers/gpu/drm/radeon/r100.c:2390:2-22: WARNING: Assignment of 0/1 to bool
variable
zhengbin (5):
drm/amdgpu: use true,false for bool variable in mxgpu_ai.c
drm/amdgpu: use true,false for bool variable in mxgpu_nv.c
drm/amdgpu: use true,false for bool variable in amdgpu_device.c
drm/amdgpu: use true,false for bool variable in amdgpu_debugfs.c
drm/amdgpu: use true,false
This patch series adds new DRM driver for Cadence Display Port.
The Cadence Display Port is also referred as MHDP (Mobile High
Definition Link, High-Definition Multimedia Interface Display
Port) Cadence Display Port complies with VESA DisplayPort (DP)
and embedded Display Port (eDP) standards This
Hello,
syzbot found the following crash on:
HEAD commit:62104694 Merge branch 'parisc-5.5-2' of git://git.kernel.o..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=1711b6c1e0
kernel config: https://syzkaller.appspot.com/x/.config?x=1b59a3066828ac4c
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:85:6-13:
WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:88:2-9:
WARNING: Assignment of 0/1 to bool variable
zhengbin (8):
drm/amd/display: use true,false for bool variable in dc_link_ddc.c
drm/amd/display: use true,false for bool variable in
dcn10_hw_sequencer.c
drm/amd/display: use true,false for bool variable in dcn20_hwseq.c
drm/amd/display: use true,false for bool variable in
On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port
becomes useless and never responds to cable hotplugging:
[3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon
[3.031945] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port D
Seems like the
Fixes coccicheck warning:
drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/i915/i915_debugfs.c:3080:4-36: WARNING: Assignment of 0/1 to
bool
Fixes coccicheck warning:
drivers/gpu/drm/radeon/rv770.c:1706:2-15: WARNING: Assignment of 0/1 to bool
variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/radeon/rv770.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/Kconfig | 10
drivers/gpu/drm/bridge/Makefile | 3 ++
drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79
On Mon, Dec 23, 2019 at 3:19 AM Harigovindan P wrote:
>
> Updating REG_DSI_LANE_CTRL register value by reading default
> register value and writing it back using bitwise OR with
> DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST. This works for all panels.
Why?
You explain what the code does, which I can
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:674:2-26: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:794:1-25: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:897:2-36: WARNING: Assignment of 0/1 to
Fixes coccicheck warning:
drivers/gpu/drm/radeon/si.c:6475:2-15: WARNING: Assignment of 0/1 to bool
variable
drivers/gpu/drm/radeon/si.c:6542:2-15: WARNING: Assignment of 0/1 to bool
variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/radeon/si.c | 4 ++--
1 file
syzbot has bisected this bug to:
commit e3933f26b657c341055443103bad331f4537b113
Author: Rex Zhu
Date: Tue Jan 16 10:35:15 2018 +
drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=12b5a799e0
start
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c:186:6-14: WARNING:
Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c:189:2-10: WARNING:
Assignment of 0/1 to bool variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
This patch adds new DRM driver for Cadence MHDP DPTX IP used on J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards.It integrates uCPU running the
embedded Firmware(FW) interfaced over APB interface.
Basically, it takes a DPI
Fixes coccicheck warning:
drivers/gpu/drm/radeon/ni.c:2020:2-15: WARNING: Assignment of 0/1 to bool
variable
drivers/gpu/drm/radeon/ni.c:2088:2-15: WARNING: Assignment of 0/1 to bool
variable
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/radeon/ni.c | 4 ++--
1 file
Hi all,
This is another version of the driver. Note that the driver changed
significally and is a more simply because now is using the panel_bridge
helpers. Apart from this, I addressed the comments from Maxime, Laurent
and Ezequiel.
This bridge is required to have the embedded display working
>-Original Message-
>From: dri-devel On Behalf Of Lucas De
>Marchi
>Sent: Wednesday, December 18, 2019 1:09 AM
>To: Roper, Matthew D
>Cc: Lisovskiy, Stanislav ; David Airlie
>; Laxminarayan Bharadiya, Pankaj
>; Summers, Stuart
>; dri-devel@lists.freedesktop.org; Vivi, Rodrigo
>;
Hi Boris.
> Just a reminder of my 2 proposals:
>
> 1/ implement the bridge_ops->pre_enable/post_disable() hooks so you can
>split your enable/disable logic in 2 parts and make sure things are
>ready when the panel/next bridge tries to send DSI commands
> 2/ move everything that's needed
From: Heiko Stuebner
The XPP055C272 is a 5.5" 720x1280 DSI display.
changes in v4:
- fix id (Maxime)
- drop port (Maxime)
changes in v2:
- add size info into binding title (Sam)
- add more required properties (Sam)
Signed-off-by: Heiko Stuebner
Reviewed-by: Sam Ravnborg
Acked-by: Maxime
From: Heiko Stuebner
Shenzhen Xinpeng Technology Co., Ltd produces for example display panels.
Signed-off-by: Heiko Stuebner
Acked-by: Sam Ravnborg
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Heiko Stuebner
Base on the somewhat similar Rocktech driver but adapted for
panel-specific init of the XPP055C272.
changes in v5:
- drop error message when backlight not found, no other panel
does that and if needed it should live in drm_panel_of_backlight
changes in v4:
none
changes
From: Heiko Stuebner
The LTK500HD1829 is 5.5" DSI display.
changes in v4:
- drop error message if backlight not found, no other panel
does that and if needed it should live in drm_panel_of_backlight
changes in v3:
- drop one more overlooked panel->drm access
Signed-off-by: Heiko Stuebner
From: Heiko Stuebner
The LTK500HD1829 is a 5.0" 720x1280 DSI display.
changes in v2:
- fix id (Maxime)
- drop port (Maxime)
Signed-off-by: Heiko Stuebner
Acked-by: Maxime Ripard
---
.../display/panel/leadtek,ltk500hd1829.yaml | 47 +++
1 file changed, 47 insertions(+)
From: Heiko Stuebner
Shenzhen Leadtek Technology Co., Ltd. produces for example display
and touch panels.
Signed-off-by: Heiko Stuebner
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Tom-Murphy/Convert-the-intel-iommu-driver-to-the-dma-iommu-api/20191224-171249
base:
https
On Tue, 24 Dec 2019 10:49:36 +0100
Boris Brezillon wrote:
> On Tue, 24 Dec 2019 10:44:22 +0100
> Boris Brezillon wrote:
>
> > On Tue, 24 Dec 2019 10:16:49 +0100
> > Andrzej Hajda wrote:
> >
> > > On 23.12.2019 10:55, Marek Szyprowski wrote:
> > > > Hi Boris,
> > > >
> > > > On
On Tue, 24 Dec 2019 10:44:22 +0100
Boris Brezillon wrote:
> On Tue, 24 Dec 2019 10:16:49 +0100
> Andrzej Hajda wrote:
>
> > On 23.12.2019 10:55, Marek Szyprowski wrote:
> > > Hi Boris,
> > >
> > > On 16.12.2019 16:25, Boris Brezillon wrote:
> > >> On Mon, 16 Dec 2019 16:02:36 +0100
> >
On Tue, 24 Dec 2019 10:16:49 +0100
Andrzej Hajda wrote:
> On 23.12.2019 10:55, Marek Szyprowski wrote:
> > Hi Boris,
> >
> > On 16.12.2019 16:25, Boris Brezillon wrote:
> >> On Mon, 16 Dec 2019 16:02:36 +0100
> >> Marek Szyprowski wrote:
> >>> Hi Boris,
> >>>
> >>> On 16.12.2019 15:55,
On 23.12.2019 10:55, Marek Szyprowski wrote:
> Hi Boris,
>
> On 16.12.2019 16:25, Boris Brezillon wrote:
>> On Mon, 16 Dec 2019 16:02:36 +0100
>> Marek Szyprowski wrote:
>>> Hi Boris,
>>>
>>> On 16.12.2019 15:55, Boris Brezillon wrote:
On Mon, 16 Dec 2019 14:54:25 +0100
Marek Szyprowski
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