Hi, Enric:
Enric Balletbo i Serra 於 2020年2月26日 週三 下午7:27寫道：
>
> Equivalent information can be nowadays obtained using function tracer.
Applied to mediatek-drm-next [1], thanks.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Hi Maxime,
Am 24.04.20 um 17:35 schrieb Maxime Ripard:
> The HDMI driver was registering a single debugfs file so far with the name
> hdmi_regs.
>
> Obviously, this is not going to work anymore when will have multiple HDMI
> controllers since we will end up trying to register two files with the
Hi Maxime,
Am 24.04.20 um 17:34 schrieb Maxime Ripard:
> The HDMI controllers found in the BCM2711 has a pretty different clock and
> registers areas than found in the older BCM283x SoCs.
>
> Let's create a variant structure to store the various adjustments we'll
> need later on, and a function
Hi Maxime,
Am 24.04.20 um 17:35 schrieb Maxime Ripard:
> Now that all the drivers have been adjusted for it, let's bring in the
> necessary device tree changes.
>
> Signed-off-by: Maxime Ripard
> ---
> arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 46 +++-
> arch/arm/boot/dts/bcm2711.dtsi
Hi Venkateshwar
On Tue, Apr 21, 2020 at 02:50:55AM +0530, Venkateshwar Rao Gannavarapu wrote:
> This add a dt binding for Xilinx DSI TX subsystem.
>
> The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem
> implements the Mobile Industry Processor Interface (MIPI) based display
>
Quoting Douglas Anderson (2020-04-23 09:25:46)
> This moves the bindings over, based a lot on toshiba,tc358768.yaml.
> Unless there's someone known to be better, I've set the maintainer in
> the yaml as the first person to submit bindings.
>
> Signed-off-by: Douglas Anderson
> ---
Reviewed-by:
Hi Björn.
On Mon, Apr 20, 2020 at 02:57:27PM -0700, Bjorn Andersson wrote:
> Define the vendor prefix for InfoVision Optoelectronics and add their
> M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel to the compatible list
> of panel-simple.
>
> Signed-off-by: Bjorn Andersson
I got OK for the
On Fri, Apr 17, 2020 at 05:06:07PM +0200, Enric Balletbo i Serra wrote:
> The PS8640 dsi-to-eDP bridge driver is using the panel bridge API,
> however, not all the components in the chain have been ported to the
> drm_bridge API. Actually, when a panel is attached the default panel's mode
> is
Hi Dmitry
On Sat, Apr 18, 2020 at 08:07:03PM +0300, Dmitry Osipenko wrote:
> Currently Tegra DRM driver manually manages display panel, but this
> management could be moved out into DRM core if we'll wrap panel into
> DRM bridge. This patch wraps RGB panel into a DRM bridge and removes
> manual
On Mon, Apr 20, 2020 at 02:57:42PM -0700, Bjorn Andersson wrote:
> The BOE NV133FHM-N61 panel is a 13.3" 1920x1080 eDP panel, add support
> for it in panel-simple.
>
> Signed-off-by: Bjorn Andersson
While applying I fixed so boe_nv133fhm_n61 is defined before boe_nv140fhmn49.
Sam
>
On Mon, Apr 20, 2020 at 02:57:41PM -0700, Bjorn Andersson wrote:
> Add the BOE NV133FHM-N61 13.3" FHD (1920x1080) TFT LCD Panel to the
> compatible list of panel-simple.
>
> Signed-off-by: Bjorn Andersson
Applied to drm-misc-next.
Sam
> ---
>
Hi Souptick
On Mon, Apr 20, 2020 at 11:57:24PM +0530, Souptick Joarder wrote:
> These are dead code since 3.15. These can be removed forever if no
> plan to use it further.
>
> Signed-off-by: Souptick Joarder
Thanks. Patch applied to drm-misc-next.
It will appear in mianline kernel in next
Hi YueHaibing
On Fri, Apr 17, 2020 at 06:14:01PM +0800, YueHaibing wrote:
> drivers/gpu/drm/panel/panel-truly-nt35597.c:493:31: warning: variable
> ‘config’ set but not used [-Wunused-but-set-variable]
> const struct nt35597_config *config;
>^~
>
>
On Fri, Apr 17, 2020 at 08:53:28AM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Add missing compatible strings for the Panasonic and Chunghwa panels
> found on NVIDIA Dalmore and Cardhu boards.
>
> Signed-off-by: Thierry Reding
Applied to drm-misc-next.
The resulting patch in git
On Thu, Apr 16, 2020 at 11:06:54PM +0200, Enric Balletbo i Serra wrote:
> Since commit 89958b7cd955 ("drm/bridge: panel: Infer connector type from
> panel by default"), drm_panel_bridge_add() and their variants can return
> NULL and an error pointer. This is fine but none of the actual users of
>
On Thu, Apr 16, 2020 at 06:44:04PM +0200, Enric Balletbo i Serra wrote:
> The panel connector type should be set by the panel not the bridge, so
> remove the connector_type assignment.
>
> Signed-off-by: Enric Balletbo i Serra
Thanks, applied to drm-misc-next.
Sam
> ---
>
>
On Thu, Apr 16, 2020 at 06:44:03PM +0200, Enric Balletbo i Serra wrote:
> The LP120UP1 is a eDP panel, set the connector type accordingly.
>
> Signed-off-by: Enric Balletbo i Serra
Thanks.
Applied to drm-misc-next.
Sam
> ---
>
> drivers/gpu/drm/panel/panel-simple.c | 1 +
> 1 file
Hi Sebastian.
On Wed, Apr 15, 2020 at 07:27:22PM +0200, Sebastian Reichel wrote:
> Hi,
>
> Patches are more or less independent of each other. There
> was a previous version for the 12" and 15" panels, which
> was missing the DT binding update. The 19" patch is new,
> for the previous 10" panel
Hi Zheng
On Fri, Apr 24, 2020 at 04:02:24PM +0800, Zheng Bin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/panel/panel-ilitek-ili9322.c:382:2-3: Unneeded semicolon
> drivers/gpu/drm/panel/panel-ilitek-ili9322.c:391:2-3: Unneeded semicolon
>
> Reported-by: Hulk Robot
> Signed-off-by:
Hi Daniel.
On Wed, Apr 15, 2020 at 09:40:21AM +0200, Daniel Vetter wrote:
> Simple pipe helpers only have an enable and disable hook, no more
> mode_set_nofb. Call it from our enable hook to align with that
> conversions.
>
> Atomic helpers always call mode_set_nofb and enable together, so
>
Hi Thomas.
On Thu, Apr 23, 2020 at 09:40:03AM +0200, Thomas Zimmermann wrote:
> MAINTAINERS got sorted in
>
> commit 4400b7d68f6e ("MAINTAINERS: sort entries by entry name")
>
> Merging from drm-next into drm-misc-next duplicated some of the
> entries by restoring old, unsorted sections.
https://bugzilla.kernel.org/show_bug.cgi?id=206987
Cyrax (ev...@hotmail.com) changed:
What|Removed |Added
Kernel Version|5.6.5 |5.6.7
--
You are receiving
https://bugzilla.kernel.org/show_bug.cgi?id=206987
--- Comment #10 from Cyrax (ev...@hotmail.com) ---
Created attachment 288719
--> https://bugzilla.kernel.org/attachment.cgi?id=288719=edit
gdb disassembler dump around mode_support_and_system_configuration
And it happened again. Looks like
Chrontel makes encoders for video displays and perhaps other stuff.
Their web site is http://www.chrontel.com/.
Signed-off-by: Lubomir Rintel
Acked-by: Rob Herring
---
Changes since v1:
- Collect Rob's ack
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2
On Fri, Apr 24, 2020 at 09:17:58AM +0300, Jani Nikula wrote:
> On Tue, 21 Apr 2020, Guru Das Srinagesh wrote:
> > Since the PWM framework is switching struct pwm_state.duty_cycle's
> > datatype to u64, prepare for this transition by using DIV_ROUND_UP_ULL
> > to handle a 64-bit dividend.
> >
> >
Add SGX GPU node with interrupt.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/am3517.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index e0b5a00e2078..3fce56a646d1 100644
---
Add SGX GPU node with interrupt. Tested on Pyra-Handheld.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap5.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index
This is a driver for video encoder with VGA and DVI/HDMI outputs.
There is no documentation for the chip -- the operation was guessed from
what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
come from the ch7035 driver in Mediatek's GPL code dump.
Only bare minimum is
On Fri, Apr 24, 2020 at 07:43:03AM +0100, Lee Jones wrote:
> A great deal of mailing lists contain numerous protections against
> things like flooding and spamming. One of those protections is a
> check for "Too many recipients to the message". Most of the time this
> simply requires moderator
and add interrupt and clocks.
Tested to build for CI20 board and load a driver.
Setup can not yet be fully tested since there is no working
HDMI driver for jz4780.
Suggested-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++
1 file
* changed commit message for the dt-bindings to better describe latest situation
* added properties for up to 4 clocks, reset, power-domains, sgx-supply -
proposed by Maxime Ripard
* fixed jz4780 and s5pv210 to use "core" clock name
* simplified example
* update for arm: dts: s5pv210 - by
Add SGX GPU node with interrupt. Tested on GTA04, BeagleBoard XM.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap36xx.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index
From: Philipp Rossak
We are adding the devicetree binding for the PVR-SGX-544-115 gpu.
This driver is currently under development in the openpvrsgx-devgroup.
Right now the full binding is not figured out, so we provide here a
placeholder. It will be completed as soon as there is a demo
From: Philipp Rossak
We are adding the devicetree binding for the PVR-SGX-544-115 gpu.
This driver is currently under development in the openpvrsgx-devgroup.
Right now the full binding is not figured out, so we provide here a
placeholder. It will be completed as soon as there is a demo
> Am 24.04.2020 um 22:34 schrieb H. Nikolaus Schaller :
>
> The Imagination PVR/SGX GPU is part of several SoC from
> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo,
> Allwinner A83 and others.
>
> With this binding, we describe how the SGX processor is
> interfaced to the SoC
From: Philipp Rossak
We are adding the devicetree binding for the PVR-SGX-544-115 gpu.
This driver is currently under development in the openpvrsgx-devgroup.
Right now the full binding is not figured out, so we provide here a
placeholder. It will be completed as soon as there is a demo
The Imagination PVR/SGX GPU is part of several SoC from
multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo,
Allwinner A83 and others.
With this binding, we describe how the SGX processor is
interfaced to the SoC (registers and interrupt).
The interface also consists of clocks, reset,
From: Jonathan Bakker
All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached.
There is no external regulator for it so it can be enabled by default.
Signed-off-by: Jonathan Bakker
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/s5pv210.dtsi | 13 +
1 file
Add SGX GPU node with interrupt. Tested on PandaBoard ES.
Since omap4420/30/60 and omap4470 come with different SGX variants
we need to introduce a new omap4470.dtsi. If an omap4470 board
does not want to use SGX it is no problem to still include
omap4460.dtsi.
Signed-off-by: H. Nikolaus
Add SGX GPU node with interrupt. Tested on BeagleBone Black.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/am33xx.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index
Add binding document for the Chrontel CH7033 VGA/DVI/HDMI Encoder.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v3:
- Fixed the example so that it validates
Changes since v1:
- Dual licensed with BSD-2-Clause
- Collected Rob's reviewed-by tag
Add SGX GPU node with interrupt. Tested on OpenPandora 600 MHz.
According to omap3530 TRM the SGX register block is 64kB.
See: 13.4 SGX Register Mapping, Table 13-2
Reported-by: Andrew F. Davis # register size
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap34xx.dtsi | 11
Hi,
chained to this message is another spin of a driver for CH7033.
Compared to the previous submission, the integration with device
component framework and creation of an encoder on component bind has
been removed. This means that until the Armada driver won't work with
this driver until it's
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