Am 07.01.21 um 22:32 schrieb Bjorn Helgaas:
On Thu, Jan 07, 2021 at 06:50:17PM +0100, Nirmoy Das wrote:
RX 5600 XT Pulse advertises support for BAR0 being 256MB, 512MB,
or 1GB, but it also supports 2GB, 4GB, and 8GB. Add a rebar
size quirk so that CPU can fully access the BAR0.
This isn't
I demand that Bjorn Helgaas may or may not have written...
>> +static inline int pci_rebar_bytes_to_size(u64 bytes)
>> +{
>> +bytes = roundup_pow_of_two(bytes);
>> +return max(ilog2(bytes), 20) - 20;
> This isn't returning a "size", is it? It looks like it's returning the
> log2 of the
[AMD Public Use]
Thanks Siqueira.
Comments below.
> -Original Message-
> From: Siqueira, Rodrigo
> Sent: Friday, January 8, 2021 4:53 AM
> To: amd-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Lin, Wayne ; Deucher, Alexander
> ; Wentland, Harry
> ; Li, Roman ; R,
On Fri, 25 Dec 2020 15:52:57 +0800, Chunfeng Yun wrote:
> Convert mediatek,mtu3.txt to YAML schema mediatek,mtu3.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v5: changes suggested by Rob
> 1. remove unnecessary maxItems
> 2. define all phys supported
>
> v4:
> 1. refer to usb-drd.yaml
On Fri, 25 Dec 2020 15:52:56 +0800, Chunfeng Yun wrote:
> Convert mediatek,mtk-xhci.txt to YAML schema mediatek,mtk-xhci.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v5: changes suggested by Rob
> 1. refer to usb-xhci.yaml instead of usb-hcd.yaml
> 2. remove unnecessary maxItems
> 3. add
On Fri, 25 Dec 2020 15:52:48 +0800, Chunfeng Yun wrote:
> Convert usb-device.txt to YAML schema usb-device.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v5: changes suggested by Rob:
> 1. limit the pattern length
> 2. remove properties description for hard wired USB devices in usb-hcd.yaml
>
On Thu, 24 Dec 2020 08:48:07 +0800, Yongqiang Niu wrote:
> Add documentation for the mt8192 gce.
>
> Add gce header file defined the gce hardware event,
> subsys number and constant for mt8192.
>
> Signed-off-by: Yongqiang Niu
> ---
> .../devicetree/bindings/mailbox/mtk-gce.txt| 7 +-
On Wed, 23 Dec 2020 20:24:33 +0100, Stefan Wahren wrote:
> Adding the missing property power-domains to the bcm2835-vec schema to fix
> the following dtbs_check issue:
>
> vec@7e806000: 'power-domains' does not match any of the regexes: ...
>
> Signed-off-by: Stefan Wahren
> ---
>
On Thu, Jan 7, 2021 at 1:07 PM Chia-I Wu wrote:
> commit 16845c5d5409 ("drm/virtio: implement blob resources: implement
> vram object") and commit c6069a02fa55 ("drm/virtgpu: Set PRIME export
> function in struct drm_gem_object_funcs") landed from different trees,
> resulting in prime export
On Thu, Jan 7, 2021 at 1:07 PM Chia-I Wu wrote:
> The context might still be missing when DRM_IOCTL_PRIME_FD_TO_HANDLE is
> the first ioctl on the drm_file.
>
> Fixes: 72b48ae800da ("drm/virtio: enqueue virtio_gpu_create_context after
> the first 3D ioctl")
> Cc: Gurchetan Singh
> Cc: Gerd
' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Thomas-Zimmermann/drm-Move-struct-drm_device-pdev-to-legacy/20210107-161007
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-s021-20210107 (attached as .config
mapfb/displays/panel-dsi-cm.ko
> drivers/gpu/drm/panel/panel-dsi-cm.ko
>
> Maybe caused by commit
>
> cf64148abcfd ("drm/panel: Move OMAP's DSI command mode panel driver")
>
> I have used the drm tree from next-20210107 for today.
This has affected the drm-misc
Add support for MT8183's G72 Bifrost.
Signed-off-by: Nicolas Boichat
Reviewed-by: Tomeu Vizoso
---
(no changes since v7)
Changes in v7:
- Fix GPU ID in commit message
Changes in v6:
- Context conflicts, reflow the code.
- Use ARRAY_SIZE for power domains too.
Changes in v5:
- Change
GPUs with more than a single regulator (e.g. G72 on MT8183) will
require platform-specific handling for devfreq, for 2 reasons:
1. The opp core (drivers/opp/core.c:_generic_set_opp_regulator)
does not support multiple regulators, so we'll need custom
handlers.
2. Generally, platforms
Define a compatible string for the Mali Bifrost GPU found in
Mediatek's MT8183 SoCs.
Signed-off-by: Nicolas Boichat
Reviewed-by: Alyssa Rosenzweig
---
(no changes since v6)
Changes in v6:
- Rebased, actually tested with recent mesa driver.
- No change
Changes in v5:
- Rename "2d" power
Hi!
Follow-up on the v5 [1], things have gotten significantly
better in the last 9 months, thanks to the efforts on Bifrost
support by the Collabora team (and probably others I'm not
aware of).
I've been testing this series on a MT8183/kukui device, with a
chromeos-5.10 kernel [2], and got basic
On Thu, Jan 07, 2021 at 11:31:36PM +, Darren Salt wrote:
> I demand that Bjorn Helgaas may or may not have written...
?
> >> +static inline int pci_rebar_bytes_to_size(u64 bytes)
> >> +{
> >> + bytes = roundup_pow_of_two(bytes);
> >> + return max(ilog2(bytes), 20) - 20;
>
> > This isn't
("drm/panel: Move OMAP's DSI command mode panel driver")
I have used the drm tree from next-20210107 for today.
--
Cheers,
Stephen Rothwell
pgp8llxUX_bBW.pgp
Description: OpenPGP digital signature
___
dri-devel mailing list
On Thu, Jan 7, 2021 at 11:59 PM Steven Price wrote:
>
> On 05/01/2021 00:11, Nicolas Boichat wrote:
> > GPUs with more than a single regulator (e.g. G-57 on MT8183) will
> > require platform-specific handling, disable devfreq for now.
>
> Can you explain what actually goes wrong here? AFAICT the
Hi, Jitao:
Jitao Shi 於 2021年1月7日 週四 下午10:34寫道：
>
> SoC will transmit the EoTp (End of Transmission packet) when
> MIPI_DSI_MODE_EOT_PACKET flag is set.
>
> Enabling EoTp will make the line time larger, so the hfp and
> hbp should be reduced to keep line time.
>
> Signed-off-by: Jitao Shi
> ---
This reverts commit 0883ce8146ed6074c76399f4e70dbed788582e12. Originally
these quirks were added because of the issues with using the eDP
backlight interfaces on certain laptop panels, which made it impossible
to properly probe for DPCD backlight support without having a whitelist
for panels that
Since we now support controlling panel backlights through DPCD using
both the standard VESA interface, and Intel's proprietary HDR backlight
interface, we should allow the user to be able to explicitly choose
between one or the other in the event that we're wrong about panels
reliably reporting
So-recently a bunch of laptops on the market have started using DPCD
backlight controls instead of the traditional DDI backlight controls.
Originally we thought we had this handled by adding VESA backlight
control support to i915, but the story ended up being a lot more
complicated then that.
Currently, every different type of backlight hook that i915 supports is
pretty straight forward - you have a backlight, probably through PWM
(but maybe DPCD), with a single set of platform-specific hooks that are
used for controlling it.
HDR backlights, in particular VESA and Intel's HDR
On Thu, Jan 7, 2021 at 7:16 PM Mario Kleiner wrote:
>
> On Thu, Jan 7, 2021 at 7:04 PM Daniel Vetter wrote:
>>
>> On Thu, Jan 7, 2021 at 7:00 PM Mario Kleiner
>> wrote:
>> >
>> > On Thu, Jan 7, 2021 at 6:57 PM Daniel Vetter wrote:
>> >>
>> >> On Sat, Jan 02, 2021 at 04:31:36PM +0100, Mario
On Thu, Jan 7, 2021 at 9:20 AM Rob Clark wrote:
>
> On Sat, Jan 2, 2021 at 12:26 PM Iskren Chernev
> wrote:
> >
> > The msm_gem_get_iova should be guarded with gpu != NULL and not aspace
> > != NULL, because aspace is NULL when using vram carveout.
> >
> > Fixes: 933415e24bd0d ("drm/msm: Add
On Thu, Jan 7, 2021 at 3:53 PM Rodrigo Siqueira
wrote:
>
> Hi,
>
> A couple of weeks ago, Daniel highlighted [1] some issue related to a
> patch entitle "drm/amd/display: Expose new CRC window property". After
> discussion, we realize that we can revert that patch because we will
> need to
Hi Dave,
A few misc fixes
The following changes since commit e319a1b956f785f618611857cd946dca2bb68542:
drm/msm: add IOMMU_SUPPORT dependency (2020-12-05 08:25:52 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/drm/msm.git drm-msm-fixes-2021-01-07
for you to
On Thu, Jan 07, 2021 at 06:50:17PM +0100, Nirmoy Das wrote:
> RX 5600 XT Pulse advertises support for BAR0 being 256MB, 512MB,
> or 1GB, but it also supports 2GB, 4GB, and 8GB. Add a rebar
> size quirk so that CPU can fully access the BAR0.
This isn't quite accurate. The CPU can fully access BAR
On Thu, Jan 07, 2021 at 06:50:14PM +0100, Nirmoy Das wrote:
> From: Darren Salt
>
> Export pci_rebar_get_possible_sizes() for use by modular drivers.
>
> Signed-off-by: Darren Salt
> Signed-off-by: Nirmoy Das
Acked-by: Bjorn Helgaas
> ---
> drivers/pci/pci.c | 1 +
> drivers/pci/pci.h
On Thu, Jan 07, 2021 at 06:50:15PM +0100, Nirmoy Das wrote:
> Users of pci_resize_resource() need a way to calculate bar size
> from desired bytes. Add a helper function and export it so that
> modular drivers can use it.
s/bar/BAR/
> Signed-off-by: Darren Salt
> Signed-off-by: Christian König
Every heap needs to create a dmabuf and then export it to a fd
via dma_buf_fd(), so to consolidate things a bit, have the heaps
just return a struct dmabuf * and let the top level
dma_heap_buffer_alloc() call handle creating the fd via
dma_buf_fd().
Cc: Sumit Semwal
Cc: Liam Mark
Cc: Laura
We shouldn't vunmap more then we vmap, but if we do, make
sure we complain loudly.
Cc: Sumit Semwal
Cc: Liam Mark
Cc: Laura Abbott
Cc: Brian Starkey
Cc: Hridya Valsaraju
Cc: Suren Baghdasaryan
Cc: Sandeep Patil
Cc: Daniel Mentz
Cc: Chris Goldsworthy
Cc: Ørjan Eide
Cc: Robin Murphy
Cc:
If we abort from the allocation due to a fatal_signal_pending(),
be sure we report an error so any return code paths don't trip
over the fact that the allocation didn't succeed.
Cc: Sumit Semwal
Cc: Liam Mark
Cc: Laura Abbott
Cc: Brian Starkey
Cc: Hridya Valsaraju
Cc: Suren Baghdasaryan
Cc:
commit 16845c5d5409 ("drm/virtio: implement blob resources: implement
vram object") and commit c6069a02fa55 ("drm/virtgpu: Set PRIME export
function in struct drm_gem_object_funcs") landed from different trees,
resulting in prime export never working for vram objects.
Cc: Gurchetan Singh
Cc:
The context might still be missing when DRM_IOCTL_PRIME_FD_TO_HANDLE is
the first ioctl on the drm_file.
Fixes: 72b48ae800da ("drm/virtio: enqueue virtio_gpu_create_context after the
first 3D ioctl")
Cc: Gurchetan Singh
Cc: Gerd Hoffmann
Signed-off-by: Chia-I Wu
---
This reverts commit 110d586ba77ed573eb7464ca69b6490ec0b70c5f.
Cc: Wayne Lin
Cc: Alexander Deucher
Cc: Harry Wentland
Cc: Roman Li
Cc: Bindu R
Cc: Daniel Vetter
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +-
This reverts commit b5d8f1d02ba7021cad1bd5ad8460ce5611c479d8.
Cc: Wayne Lin
Cc: Alexander Deucher
Cc: Harry Wentland
Cc: Roman Li
Cc: Bindu R
Cc: Daniel Vetter
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++-
This reverts commit 1206904465c8a9eebff9ca5a65effc8cf8f3cb84.
Cc: Wayne Lin
Cc: Alexander Deucher
Cc: Harry Wentland
Cc: Roman Li
Cc: Bindu R
Cc: Daniel Vetter
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 21 +--
1 file changed, 1
Hi,
A couple of weeks ago, Daniel highlighted [1] some issue related to a
patch entitle "drm/amd/display: Expose new CRC window property". After
discussion, we realize that we can revert that patch because we will
need to create a debugfs or full UAPI for CRC soon, which will make this
code
Bing Song noticed the CMA heap was leaking memory due to a flub
I made in commit a5d2d29e24be ("dma-buf: heaps: Move heap-helper
logic into the cma_heap implementation"), and provided this fix
which ensures the pagelist is also freed on release.
Cc: Bing Song
Cc: Sumit Semwal
Cc: Liam Mark
Cc:
Am 07.01.21 um 19:07 schrieb Daniel Vetter:
On Tue, Jan 05, 2021 at 07:23:08PM +0100, Christian König wrote:
Drivers are not supposed to init the page pool directly any more.
Signed-off-by: Christian König
Please include reported-by credits and link to the bug reports on
lore.kernel.org when
On Thu, Jan 7, 2021 at 7:04 PM Daniel Vetter wrote:
> On Thu, Jan 7, 2021 at 7:00 PM Mario Kleiner
> wrote:
> >
> > On Thu, Jan 7, 2021 at 6:57 PM Daniel Vetter wrote:
> >>
> >> On Sat, Jan 02, 2021 at 04:31:36PM +0100, Mario Kleiner wrote:
> >> > On Sat, Jan 2, 2021 at 3:02 PM Bas
On Tue, Jan 05, 2021 at 07:23:08PM +0100, Christian König wrote:
> Drivers are not supposed to init the page pool directly any more.
>
> Signed-off-by: Christian König
Please include reported-by credits and link to the bug reports on
lore.kernel.org when merging this. Also I guess this should
On Thu, Jan 7, 2021 at 7:00 PM Mario Kleiner wrote:
>
> On Thu, Jan 7, 2021 at 6:57 PM Daniel Vetter wrote:
>>
>> On Sat, Jan 02, 2021 at 04:31:36PM +0100, Mario Kleiner wrote:
>> > On Sat, Jan 2, 2021 at 3:02 PM Bas Nieuwenhuizen
>> > wrote:
>> > >
>> > > With modifiers one can actually have
On Thu, Jan 7, 2021 at 6:57 PM Daniel Vetter wrote:
> On Sat, Jan 02, 2021 at 04:31:36PM +0100, Mario Kleiner wrote:
> > On Sat, Jan 2, 2021 at 3:02 PM Bas Nieuwenhuizen
> > wrote:
> > >
> > > With modifiers one can actually have different format_info structs
> > > for the same format, which
On Thu, Jan 7, 2021 at 6:21 PM Liu, Zhan wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> > -Original Message-
> > From: Liu, Zhan
> > Sent: 2021/January/06, Wednesday 10:04 AM
> > To: Bas Nieuwenhuizen ; Mario Kleiner
> >
> > Cc: dri-devel ; amd-gfx list >
On Sat, Jan 02, 2021 at 04:31:36PM +0100, Mario Kleiner wrote:
> On Sat, Jan 2, 2021 at 3:02 PM Bas Nieuwenhuizen
> wrote:
> >
> > With modifiers one can actually have different format_info structs
> > for the same format, which now matters for AMDGPU since we convert
> > implicit modifiers to
RX 5600 XT Pulse advertises support for BAR0 being 256MB, 512MB,
or 1GB, but it also supports 2GB, 4GB, and 8GB. Add a rebar
size quirk so that CPU can fully access the BAR0.
Signed-off-by: Christian König
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Nirmoy Das
---
This allows BAR0 resizing to be done for cards which don't advertise
support for a size large enough to cover the VRAM but which do
advertise at least one size larger than the default. For example,
my RX 5600 XT, which advertises 256MB, 512MB and 1GB.
Signed-off-by: Darren Salt
Signed-off-by:
Users of pci_resize_resource() need a way to calculate bar size
from desired bytes. Add a helper function and export it so that
modular drivers can use it.
Signed-off-by: Darren Salt
Signed-off-by: Christian König
Signed-off-by: Nirmoy Das
---
drivers/pci/pci.c | 2 +-
include/linux/pci.h |
From: Darren Salt
Export pci_rebar_get_possible_sizes() for use by modular drivers.
Signed-off-by: Darren Salt
Signed-off-by: Nirmoy Das
---
drivers/pci/pci.c | 1 +
drivers/pci/pci.h | 1 -
include/linux/pci.h | 1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git
Hi Bjorn,
I cleaned up the patch series[1] that Christian sent
earlier to fix wrongly exported resizable bar
capability dword by VBIOS of RX 5600 XT Pulse card.
I didn't split #2 patch instead merged amdgpu changes
of #2 patch to #3 patch and removed changes related to
pci_rebar_size_to_bytes()
On Fri, Jan 01, 2021 at 10:18:17PM +0100, Jonathan Neuschäfer wrote:
> The syntax without dots is available since commit 43756e347f21
> ("scripts/kernel-doc: Add support for named variable macro arguments").
>
> The same HTML output is produced with and without this patch.
>
> Signed-off-by:
> -Original Message-
> From: Daniel Vetter
> Sent: 2021/January/07, Thursday 12:33 PM
> To: Koenig, Christian
> Cc: Liu, Zhan ; amd-...@lists.freedesktop.org; Cornij,
> Nikola ; Wang, Chao-kai (Stylon)
> ; Wang, Chao-kai (Stylon)
> ; dri-devel@lists.freedesktop.org; Kazlauskas,
>
On Sun, Jan 03, 2021 at 04:43:37PM +0100, Christian König wrote:
> Am 29.12.20 um 22:10 schrieb Zhan Liu:
> > [Why]
> > Driver cannot change amdgpu framebuffer (afb) format while doing
> > page flip. Force system doing so will cause ioctl error, and result in
> > breaking several functionalities
On Wed, Jan 6, 2021 at 8:50 PM Sai Prakash Ranjan
wrote:
>
> On 2021-01-05 01:00, Konrad Dybcio wrote:
> > Using this code on A5xx (and probably older too) causes a
> > smmu bug.
> >
> > Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system
> > cache(LLC)")
> > Signed-off-by: Konrad
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Liu, Zhan
> Sent: 2021/January/06, Wednesday 10:04 AM
> To: Bas Nieuwenhuizen ; Mario Kleiner
>
> Cc: dri-devel ; amd-gfx list g...@lists.freedesktop.org>; Deucher, Alexander
> ; Daniel Vetter ;
>
On Sat, Jan 2, 2021 at 12:26 PM Iskren Chernev wrote:
>
> The msm_gem_get_iova should be guarded with gpu != NULL and not aspace
> != NULL, because aspace is NULL when using vram carveout.
>
> Fixes: 933415e24bd0d ("drm/msm: Add support for private address space
> instances")
>
> Signed-off-by:
Hi Hans,
On Tue, Dec 29, 2020 at 02:02:30PM +0100, Hans de Goede wrote:
> Hi,
>
> On 12/28/20 7:39 PM, Peter Robinson wrote:
> > The info message was showing the mapped address for the framebuffer. To
> > avoid
> > security problems, all virtual addresses are converted to __ptrval__, so
> > the
On Mon, Dec 28, 2020 at 07:04:41PM +0800, Tian Tao wrote:
> Using drmm_mode_config_init() sets up managed release of modesetting
> resources.
>
> Signed-off-by: Tian Tao
This changes the order of the cleanup actions, so most likely will break
really badly. You can only move a cleanup action
On Mon, Dec 28, 2020 at 06:39:56PM +0800, Tian Tao wrote:
> Using the managed function simplifies the error handling. After
> unloading the driver, the PCI device should now get disabled as
> well.
>
> Signed-off-by: Tian Tao
We cant do this in core code because it changes the order of how the
Am 2021-01-07 um 11:28 a.m. schrieb Christian König:
> Am 07.01.21 um 17:16 schrieb Felix Kuehling:
>> Am 2021-01-07 um 5:56 a.m. schrieb Christian König:
>>
>>> Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Alex Sierra
[why]
To support svm bo eviction mechanism.
On Tue, Jan 05, 2021 at 07:41:52AM +0200, Laurent Pinchart wrote:
> Hi Dave and Daniel,
>
> The following changes since commit 5b2fc08c455bbf749489254a81baeffdf4c0a693:
>
> Merge tag 'amd-drm-fixes-5.11-2020-12-23' of
> git://people.freedesktop.org/~agd5f/linux into drm-next (2020-12-24
On Thu, Jan 07, 2021 at 01:49:45PM +0100, Christian König wrote:
> Am 22.12.20 um 14:51 schrieb Daniel Vetter:
> > On Fri, Dec 18, 2020 at 06:55:38PM +0100, Christian König wrote:
> > > Only initialize the DMA coherent pools if they are used.
> > >
> > > Signed-off-by: Christian König
> > Ah,
On 1/7/21 11:30 AM, Daniel Vetter wrote:
On Thu, Jan 07, 2021 at 11:26:52AM -0500, Andrey Grodzovsky wrote:
On 1/7/21 11:21 AM, Daniel Vetter wrote:
On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote:
On 11/23/20 3:01 AM, Christian König wrote:
Am 23.11.20 um 05:54 schrieb
On Thu, Jan 07, 2021 at 11:26:52AM -0500, Andrey Grodzovsky wrote:
>
> On 1/7/21 11:21 AM, Daniel Vetter wrote:
> > On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote:
> > > On 11/23/20 3:01 AM, Christian König wrote:
> > > > Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky:
> > > >
Am 07.01.21 um 17:16 schrieb Felix Kuehling:
Am 2021-01-07 um 5:56 a.m. schrieb Christian König:
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Alex Sierra
[why]
To support svm bo eviction mechanism.
[how]
If the BO crated has AMDGPU_AMDKFD_CREATE_SVM_BO flag set,
enable_signal
Typo Correction bellow
On 1/7/21 11:26 AM, Andrey Grodzovsky wrote:
Or is the idea to save the struct page * pointer? That feels a bit like
over-optimizing stuff. Better to have a simple implementation first and
then tune it if (and only if) any part of it becomes a problem for normal
usage.
On 1/7/21 11:21 AM, Daniel Vetter wrote:
On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote:
On 11/23/20 3:01 AM, Christian König wrote:
Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky:
On 11/21/20 9:15 AM, Christian König wrote:
Am 21.11.20 um 06:21 schrieb Andrey Grodzovsky:
Am 2021-01-07 um 4:23 a.m. schrieb Daniel Vetter:
> On Wed, Jan 06, 2021 at 10:00:52PM -0500, Felix Kuehling wrote:
>> This is the first version of our HMM based shared virtual memory manager
>> for KFD. There are still a number of known issues that we're working through
>> (see below). This will
On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote:
>
> On 11/23/20 3:01 AM, Christian König wrote:
> > Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky:
> > >
> > > On 11/21/20 9:15 AM, Christian König wrote:
> > > > Am 21.11.20 um 06:21 schrieb Andrey Grodzovsky:
> > > > > Will be
Am 2021-01-07 um 5:56 a.m. schrieb Christian König:
> Am 07.01.21 um 04:01 schrieb Felix Kuehling:
>> From: Alex Sierra
>>
>> [why]
>> To support svm bo eviction mechanism.
>>
>> [how]
>> If the BO crated has AMDGPU_AMDKFD_CREATE_SVM_BO flag set,
>> enable_signal callback will be called inside
On Thu, Jan 7, 2021 at 4:48 PM xuhuijie wrote:
> This commit 50145474f6ef(fbcon: remove soft scrollback code) remove soft
> scrollback in
> fbcon. So the shift+PageDown and shift+PageUp is missing. But PageUp is a
> vary important
> feature when system panic or reset. I can get log by PageUp
On 05/01/2021 00:11, Nicolas Boichat wrote:
GPUs with more than a single regulator (e.g. G-57 on MT8183) will
require platform-specific handling, disable devfreq for now.
Can you explain what actually goes wrong here? AFAICT the existing code
does support controlling multiple regulators - but
On Thu, Jan 07, 2021 at 10:01:00AM -0500, Alex Deucher wrote:
> On Wed, Dec 16, 2020 at 10:30 AM Greg Kroah-Hartman
> wrote:
> >
> > On Wed, Dec 16, 2020 at 02:52:25PM +, Deucher, Alexander wrote:
> > > [AMD Public Use]
> > >
> > > > -Original Message-
> > > > From: Laurent Pinchart
On Thu, Jan 7, 2021 at 11:28 AM Thomas Zimmermann wrote:
>
> Hi Daniel
>
> Am 11.12.20 um 10:50 schrieb Daniel Vetter:
> [...]
> >> +/**
> >> + * drm_gem_shmem_vmap_local - Create a virtual mapping for a shmem GEM
> >> object
> >> + * @shmem: shmem GEM object
> >> + * @map: Returns the kernel
On Wed, Dec 16, 2020 at 10:30 AM Greg Kroah-Hartman
wrote:
>
> On Wed, Dec 16, 2020 at 02:52:25PM +, Deucher, Alexander wrote:
> > [AMD Public Use]
> >
> > > -Original Message-
> > > From: Laurent Pinchart
> > > Sent: Tuesday, December 15, 2020 9:15 PM
> > > To: Koenig, Christian
>
SoC will transmit the EoTp (End of Transmission packet) when
MIPI_DSI_MODE_EOT_PACKET flag is set.
Enabling EoTp will make the line time larger, so the hfp and
hbp should be reduced to keep line time.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++--
1 file changed,
Hi Marek,
thanks for the patch. It works fine on stm32mp1 eval board with bridge
DSI & DPI panel.
Tested-by: Yannick Fertré
Best regards
On 12/24/20 7:20 AM, Marek Vasut wrote:
> There is not much value in the extra conversion step, the calculations
> required for the LTDC IP are different
Am 22.12.20 um 14:51 schrieb Daniel Vetter:
On Fri, Dec 18, 2020 at 06:55:38PM +0100, Christian König wrote:
Only initialize the DMA coherent pools if they are used.
Signed-off-by: Christian König
Ah, just realized the answer to my question on patch 2: The pools are
per-device, due to
On Wed, Jan 06, 2021 at 12:13:12PM +0100, Maarten Lankhorst wrote:
> drm-misc-next-2021-01-06:
> drm-misc-next for v5.12:
>
> Core Changes:
> - Lots of drm documentation updates by Simor Ser.
Extra kudos for documentation work!
> - Require that each crtc has a unique primary plane.
> - Add
Hi Marek,
thanks for the patch. It works fine on stm32mp1 eval board with bridge
DSI & DPI panel.
Tested-by: Yannick Fertré
Best regards
On 12/24/20 7:19 AM, Marek Vasut wrote:
> The drm_display_mode_to_videomode() does not populate DISPLAY_FLAGS_DE_LOW
> or DISPLAY_FLAGS_PIXDATA_NEGEDGE
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道：
>
> Add DDP support for MT8167 SoC.
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 48
> ++
> 1 file changed, 48 insertions(+)
>
> diff --git
On Mon, Jan 04, 2021 at 01:10:18PM -0800, Rodrigo Vivi wrote:
> Hi Dave and Daniel,
>
> Happy New Year.
>
> Here goes the first pull request targeting 5.12.
>
> drm-intel-next-2021-01-04:
> - Display hotplug fix for gen2/gen3 (Chris)
> - Remove trailing semicolon (Tom)
> - Suppress display
Add COLOR_ENCODING and COLOR_RANGE plane properties and use them to
control the DP CSC matrix.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 44 +--
1 file changed, 30 insertions(+), 14 deletions(-)
diff --git
Add YCbCr encoding and quantization range parameters to
ipu_dp_setup_channel() and configure the CSC DP matrix
accordingly.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 9 ++---
drivers/gpu/ipu-v3/ipu-dp.c | 25 ++---
Hi,
On 11/24/20 4:49 PM, Ville Syrjälä wrote:
> On Wed, Nov 18, 2020 at 01:40:58PM +0100, Hans de Goede wrote:
>> Commit 25b4620ee822 ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode")
>> added an intel_dsi_msleep() helper which skips sleeping if the
>> MIPI-sequences have a version of 3 or
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Philip Yang
If xnack is on, VM retry fault interrupt send to IH ring1, and ring1
will be full quickly. IH cannot receive other interrupts, this causes
deadlock if migrating buffer using sdma and waiting for sdma done while
handling retry
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Philip Yang
Forgot to reserve a fence slot to use sdma to update page table, cause
below kernel BUG backtrace to handle vm retry fault while application is
exiting.
[ 133.048143] kernel BUG at
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Alex Sierra
[why]
To support svm bo eviction mechanism.
[how]
If the BO crated has AMDGPU_AMDKFD_CREATE_SVM_BO flag set,
enable_signal callback will be called inside amdgpu_evict_flags.
This also causes gutting of the BO by removing all
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Philip Yang
It will be used by kfd to map svm range to GPU, because svm range does
not have amdgpu_bo and bo_va, cannot use amdgpu_bo_update interface, use
amdgpu vm update interface directly.
Signed-off-by: Philip Yang
Signed-off-by: Felix
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Philip Yang
Move the HMM get pages function from amdgpu_ttm and to amdgpu_mn. This
common function will be used by new svm APIs.
Signed-off-by: Philip Yang
Signed-off-by: Felix Kuehling
Acked-by: Christian König
---
-to-legacy/20210107-161007
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-s021-20210107 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-208-g46a52ca4-dirty
#
https
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道：
>
> not all SoC has dither function in gamma module
> dd private data to control this function setting
'add' ?
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 12 +---
> 1 file changed, 9
Hi Daniel
Am 11.12.20 um 10:50 schrieb Daniel Vetter:
[...]
+/**
+ * drm_gem_shmem_vmap_local - Create a virtual mapping for a shmem GEM object
+ * @shmem: shmem GEM object
+ * @map: Returns the kernel virtual address of the SHMEM GEM object's backing
+ * store.
+ *
+ * This function
On Mon, Jan 04, 2021 at 06:10:31PM +0100, Philipp Zabel wrote:
> Hi Dave, Daniel,
>
> this PR includes the drmm encoder/plane/crtc allocation functions and
> converts the imx-drm driver to use them.
>
> The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e:
>
> Linux
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道：
>
> mt8183 gamma module will different with mt8173
> separate gamma for add private data
I've applied series "Decouple Mediatek DRM sub driver" [1] into
mediatek-drm-next [2] and this patch would conflict with
mediatek-drm-next, so please
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:11寫道：
>
> add description for mt8183 display
Applied to mediatek-drm-next [1], thanks.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道：
>
> Get the fifo size from device tree
> because each rdma in the same SoC may have different fifo size
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19
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