My first email can be ignored except for the sync files. Oh well.
I think I see what you mean, Christian. If we assume that an imported fence
is always read only (the buffer with the sequence number is read only),
only the process that created and exported the fence can signal it. If the
fence is
The pull request you sent on Sat, 29 May 2021 06:00:49 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2021-05-29
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/567d1fd853b8786f93ba399c8ff7c8106bed5fe5
Thank you!
--
Deet-doot-dot, I am a bot.
The Lontium bridge is including legacy header files for GPIO
but not using them. Delete the includes.
Cc: Adrien Grassein
Cc: Robert Foss
Signed-off-by: Linus Walleij
---
drivers/gpu/drm/bridge/lontium-lt8912b.c | 2 --
1 file changed, 2 deletions(-)
diff --git
Add small API covering lists of register dumps. Currently this is a part
of MSM DRM driver, but is extracted as it might be usefull to other
drivers too.
Signed-off-by: Dmitry Baryshkov
---
include/linux/dump_state.h | 78 ++
lib/Kconfig| 3
Move DSI PHY state saving from dsi manager to dsi_phy driver. This way
the manager does not need to know that the DSI state is not preserved
acrosss resets. Everything is handled by the DSI PHY driver.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 1 -
From: Benjamin Li
Take advantage of previously-added support for persisting PLL
registers across DSI PHY disable/enable cycles (see 328e1a6
'drm/msm/dsi: Save/Restore PLL status across PHY reset') to
support persisting across the very first DSI PHY enable at
boot.
The bootloader may have left
Stop calling msm_dsi_phy_pll_save_state() from dsi_pll_7nm_init() and
dsi_pll_10nm_init(), as this is handled now by the generic code.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 ---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 ---
2 files changed, 6
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c | 3 +++
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h | 19 ---
.../gpu/drm/msm/disp/msm_disp_snapshot_util.c | 8
3 files changed, 11 insertions(+), 19 deletions(-)
diff --git
Change msm_disp_snapshot to use dump_state API.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c | 2 +-
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h |
msm_dsi_phy_pll_restore_state() is only called from msm_dsi_phy_enable(),
so there is no need to export it. Mark it static.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 1 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 30 +--
2 files changed,
This patchseries is an RFC for splitting Qualcomm DSI PHY from drm/msm
driver to generic PHY subsystem.
Dependencies:
- msm_disp_snapshot fix at
https://lore.kernel.org/linux-arm-msm/20210527220330.3364716-1-dmitry.barysh...@linaro.org/
- Patches 1-7 from
The hang_limit is the threshold after which the kernel no longer
attempts to schedule a job. Its documentation stated the opposite due to
a typo. Correct the wording to indicate the actual purpose of the field.
Signed-off-by: Alyssa Rosenzweig
Cc: David Airlie
Cc: Daniel Vetter
---
On 2021-05-10 21:20, Bjorn Andersson wrote:
The eDP controller found in SC8180x is at large compatible with the
current implementation, but has its register blocks at slightly
different offsets.
Add the compatible and the new register layout.
I am not able to completely recall the history of
On 2021-05-10 21:20, Bjorn Andersson wrote:
Some bootloaders set the widebus enable bit in the INTF_CONFIG
register,
but configuration of widebus isn't yet supported ensure that the
register has a known value, with widebus disabled.
Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver
On 2021-05-10 21:20, Bjorn Andersson wrote:
Not all platforms has DP_P0 at offset 0x1000 from the beginning of the
DP block. So move the offsets into dss_io_data, to make it possible in
the next patch to specify alternative offsets and sizes of these
segments.
Signed-off-by: Bjorn Andersson
Hi Bjorn
On 2021-05-10 21:20, Bjorn Andersson wrote:
In the search for causes to timing issues seen during implementation of
eDP support for SC8180x a fair amount of time was spent concluding why
the calculated mvid/nvid values where wrong.
The overall conclusion is that the ratio of MVID/NVID
Hi Bjorn
On 2021-05-19 07:51, Bjorn Andersson wrote:
On Tue 18 May 22:41 CDT 2021, abhin...@codeaurora.org wrote:
Hi Bjorn
I had a quick glance on the series and before getting to other things
wanted
to know how you are initializing two different connectors for
DP & EDP resp.
The
On 29/05/2021 01:23, abhin...@codeaurora.org wrote:
On 2021-05-28 03:39, Dmitry Baryshkov wrote:
On 21/05/2021 15:49, Vinod Koul wrote:
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions upto 4k. For more resolutions like 8k this won't
work.
If both implicit and explicit synchronization are handled the same, then
the kernel won't be able to identify the process that caused an implicit
sync deadlock. The process that is stuck waiting for a fence can be
innocent, and the kernel can't punish it. Likewise, the GPU reset guery
that reports
On 2021-05-28 03:39, Dmitry Baryshkov wrote:
On 21/05/2021 15:49, Vinod Koul wrote:
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions upto 4k. For more resolutions like 8k this
won't
work.
Furthermore, we can use 1 DSC encoder in lesser resulutions,
Hi Linus,
Pretty quiet this week, couple of amdgpu, one i915, and a few misc otherwise.
Dave.
drm-fixes-2021-05-29:
drm fixes for 5.13-rc4
ttm:
- prevent irrelevant swapout
amdgpu:
- MultiGPU fan fix
- VCN powergating fixes
amdkfd:
- Fix SDMA register offset error
meson:
- fix shutdown
On 5/22/21 3:13 AM, Christian König wrote:
Hi Zack,
IIRC that was for the VMW_PL_GMR type, wasn't it?
As far as I have seen that backend was just giving out unique numbers and it
looked questionable that we allocated pages for that.
E.g. when you set that flag then for each allocation we
On Sun, 31 Jan 2021 13:50:16 +0100, Johan Jonker wrote:
> To reduce memory various Rockchip VOP versions share
> common reg structures. However more recent added SoCs not
> always have to same futures as the old ones.
> Add PX30 missing version info, so all VOP version checks
> work correct if
On Sat, 1 May 2021 17:13:16 +0200, Christophe JAILLET wrote:
> 'ret' is know to be 0 a this point. Checking the return value of
> 'phy_init()' and 'phy_set_mode()' was intended instead.
>
> So add the missing assignments.
Applied, thanks!
[1/1] drm/rockchip: Fix an error handling path
On Tue, 15 Sep 2020 17:20:49 +0100, Colin King wrote:
> The variable bit_per_pix is a u8 and is promoted in the multiplication
> to an int type and then sign extended to a u64. If the result of the
> int multiplication is greater than 0x7fff then the upper 32 bits will
> be set to 1 as a
On Thu, 15 Apr 2021 16:47:01 +0800, Jiapeng Chong wrote:
> Fix the following clang warning:
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c:320:20: warning: unused
> function 'dsi_set' [-Wunused-function].
Applied, thanks!
[1/1] drm/rockchip: remove unused function
commit:
On Sun, 18 Apr 2021 19:03:04 -0700, Thomas Hebb wrote:
> commit cf6d100dd238 ("drm/rockchip: dsi: add dual mipi support") added
> this devcnt field and call to component_del(). However, these both
> appear to be erroneous changes left over from an earlier version of the
> patch. In the version
On Sun, 18 Apr 2021 19:04:10 -0700, Thomas Hebb wrote:
> When we first enable the DSI encoder, we currently program some per-chip
> configuration that we look up in rk3399_chip_data based on the device
> tree compatible we match. This data configures various parameters of the
> MIPI lanes,
On Wed, 19 May 2021 21:49:28 +0800, Yang Yingliang wrote:
> After calling clk_prepare_enable(), clk_disable_unprepare() need
> be called when calling regmap_write() failed.
Applied, thanks!
[1/1] drm/rockchip: cdn-dp-core: add missing clk_disable_unprepare() on error
in cdn_dp_grf_write()
On Thu, 6 May 2021 10:29:51 +0100, Peter Robinson wrote:
> The CDP DP component of the rockchip GPU driver requires firmware
> so define MODULE_FIRMWARE for rockchip/dptx.bin so the details
> are available in the module info.
Applied, thanks!
[1/1] drm/rockchip: cdn-dp-core: add MODULE_FIRMWARE
On Fri, 28 May 2021 15:05:49 +0200, Alex Bee wrote:
> this is v3 of a series I posted almost 1 year ago. I considered now all
> feedback I got at that time.
> It mainly ports existining functionality to older SoCs - most importantly
> enables alpha blending for RK3036, RK3066, RK3126 and RK3188
>
Instead of reading the desired 5 bytes of the actual target field,
the code was reading 8. This could result in a corrupted value if the
trailing 3 bytes were non-zero, so instead use an appropriately sized
and zero-initialized bounce buffer, and read only 5 bytes before casting
to u64.
Am 2021-05-28 um 9:08 a.m. schrieb Jason Gunthorpe:
> On Thu, May 27, 2021 at 07:08:04PM -0400, Felix Kuehling wrote:
>> Now we're trying to migrate data to and from that memory using the
>> migrate_vma_* helpers so we can support page-based migration in our
>> unified memory allocations, while
On 07/04/2021 18:01, Dmitry Baryshkov wrote:
Move the bus clock to mdp device node,in order to facilitate bus band
width scaling on sdm845 target.
The parent device MDSS will not vote for bus bw, instead the vote will
be triggered by mdp device node. Since a minimum vote is required to
turn on
Am 28.05.21 um 17:10 schrieb Thomas Hellström:
On 5/28/21 4:19 PM, Christian König wrote:
Am 27.05.21 um 16:47 schrieb Thomas Hellström:
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
On 5/28/21 4:19 PM, Christian König wrote:
Am 27.05.21 um 16:47 schrieb Thomas Hellström:
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking
On 5/28/2021 4:36 PM, Christian König wrote:
Am 20.04.21 um 12:50 schrieb Nirmoy Das:
Releasing pinned BOs is illegal now.
UVD 6 was missing from:
commit 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO")
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
Maybe add a
Hi Marek,
well I don't think that implicit and explicit synchronization needs to
be mutual exclusive.
What we should do is to have the ability to transport an synchronization
object with each BO.
Implicit and explicit synchronization then basically become the same,
they just transport the
Am 20.04.21 um 12:50 schrieb Nirmoy Das:
Releasing pinned BOs is illegal now.
UVD 6 was missing from:
commit 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO")
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
Maybe add a CC:stable tag as well.
Sorry I somehow overlooked this
Am 28.05.21 um 16:17 schrieb Thomas Hellström:
On 5/28/21 4:10 PM, Christian König wrote:
Am 28.05.21 um 09:33 schrieb Thomas Hellström:
On Fri, 2021-05-28 at 09:16 +0200, Christian König wrote:
Am 27.05.21 um 17:51 schrieb Thomas Hellström:
On Thu, 2021-05-27 at 17:32 +0200, Christian
Am 27.05.21 um 16:47 schrieb Thomas Hellström:
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts to
On 5/28/21 4:10 PM, Christian König wrote:
Am 28.05.21 um 09:33 schrieb Thomas Hellström:
On Fri, 2021-05-28 at 09:16 +0200, Christian König wrote:
Am 27.05.21 um 17:51 schrieb Thomas Hellström:
On Thu, 2021-05-27 at 17:32 +0200, Christian König wrote:
Am 27.05.21 um 17:05 schrieb Thomas
Am 28.05.21 um 09:33 schrieb Thomas Hellström:
On Fri, 2021-05-28 at 09:16 +0200, Christian König wrote:
Am 27.05.21 um 17:51 schrieb Thomas Hellström:
On Thu, 2021-05-27 at 17:32 +0200, Christian König wrote:
Am 27.05.21 um 17:05 schrieb Thomas Hellström:
On Thu, 2021-05-27 at 17:01 +0200,
Hi Philippe,
I have already reviewed this patch on January 7, 2020.
(https://lore.kernel.org/dri-devel/0ab4ee45-4437-3b02-cf63-0e3b1b539...@st.com/)
Could you please review it and merge it?
Best regards
Yannick
On 5/28/21 10:05 AM, Yannick Fertre wrote:
There is not much value in the extra
Am 27.05.21 um 09:38 schrieb Javier Martinez Canillas:
Hello Thomas,
On 5/16/21 12:30 PM, Thomas Zimmermann wrote:
Am 16.05.21 um 09:48 schrieb Javier Martinez Canillas:
There are drivers that register framebuffer devices very early in the boot
process and make use of the existing
[Why]
When we receive CSN message to notify one port is disconnected, we will
implicitly set its corresponding num_slots to 0. Later on, we will
eventually call drm_dp_update_payload_part1() to arrange down streams.
In drm_dp_update_payload_part1(), we iterate over all proposed_vcpis[]
to do the
[Why]
After unplug/hotplug hub from the system, userspace might start to
clear stale payloads gradually. If we call drm_dp_mst_deallocate_vcpi()
to release stale VCPI of those ports which are not relating to current
topology, we have chane to wrongly clear active payload table entry for
current
Use Startech 1to3 DP hub to do some mst hotplug tests and find some
light up issues.
1. ACT polling timeout:
Which is due to we didn't update DPCD payload table but still try
to send ACT and polling for "ACT Handled" bit
2. Not all monitors light up:
Due to we wrongly set unavailable VCP
Hi Tomeu,
> Will this be enough to implement GL_TIMESTAMP and GL_TIME_ELAPSED queries?
>
> Guess the DDK implements these as WRITE_VALUE jobs, and there's also a soft
> job BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME that I guess is used for
> glGet*(GL_TIMESTAMP). Other DRM drivers use an ioctl for that
On Fri, May 28, 2021 at 11:48:40AM +1000, Alistair Popple wrote:
[...]
> > > > > + while (page_vma_mapped_walk()) {
> > > > > + /* Unexpected PMD-mapped THP? */
> > > > > + VM_BUG_ON_PAGE(!pvmw.pte, page);
> > > > > +
> > > > > + if
On Thu, May 27, 2021 at 07:08:04PM -0400, Felix Kuehling wrote:
> Now we're trying to migrate data to and from that memory using the
> migrate_vma_* helpers so we can support page-based migration in our
> unified memory allocations, while also supporting CPU access to those
> pages.
So you have
On 5/28/21 3:00 PM, Christian König wrote:
We need to grab the resv lock first before doing that check.
v2 (chk): simplify the change for -fixes
Signed-off-by: Christian König
Signed-off-by: Thomas Hellström
Hmm, OK, but this doesn't fix the swapped-bo-not-on-lru and unpopulating
from
We need to grab the resv lock first before doing that check.
v2 (chk): simplify the change for -fixes
Signed-off-by: Christian König
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/ttm/ttm_bo.c | 5 -
drivers/gpu/drm/ttm/ttm_device.c | 8 +---
2 files changed, 5 insertions(+),
On 5/3/21 1:11 PM, Rob Herring wrote:
On Fri, Apr 23, 2021 at 01:24:40PM -0400, Jonathan Marek wrote:
Document qcom,dsi-phy-cphy-mode option, which can be used to control
whether DSI will operate in D-PHY (default) or C-PHY mode.
Given this is a standard MIPI thing, I think this needs to be a
Am 28.05.21 um 11:47 schrieb Yu, Lang:
[AMD Official Use Only]
Inline.
-Original Message-
From: Koenig, Christian
Sent: Thursday, May 27, 2021 7:51 PM
To: Yu, Lang ; amd-...@lists.freedesktop.org; dri-
de...@lists.freedesktop.org
Cc: Huang, Ray ; Deucher, Alexander
; Olsak, Marek
Am 28.05.21 um 11:29 schrieb Jiapeng Chong:
In the function amdgpu_uvd_cs_msg(), every branch in the switch
statement will have a return, so the code below the switch statement
will not be executed.
Eliminate the follow smatch warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:845
Convert the Solomon SSD1307 Framebuffer Device Tree binding
documentation to json-schema.
Fix the spelling of the "pwms" property.
Document default values.
Make properties with default values not required.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Rob Herring
---
v2:
- Add Reviewed-by,
Use DEVICE_ATTR_*() helper instead of plain DEVICE_ATTR(),
which makes the code a bit shorter and easier to read.
Signed-off-by: YueHaibing
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 8 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 28 +++
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we slightly
need to massage the mmap handlers to
From: Maarten Lankhorst
This allows drivers to distinguish between different types of vma_node's.
The readonly flag was unused and is thus removed.
This is a temporary solution, until i915 is converted completely to
use ttm for bo's.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas
Since objects can be migrated or evicted when not pinned or locked,
update the checks for lmem residency or future residency so that
the value returned is not immediately stale.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2: Simplify i915_gem_object_migratable() (Reported by
From: Maarten Lankhorst
The platform should exclusively use mmap_offset, one less path to worry
about for discrete.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other drivers as well.
Add an eviction_valuable call
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality like delayed delete and LRU list manipulation.
Initially we support only LMEM and SYSTEM memory, but SYSTEM
(which in this case means evicted LMEM
Temporarily remove the buddy allocator and related selftests
and hook up the TTM range manager for i915 regions.
Also modify the mock region selftests somewhat to account for a
fragmenting manager.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld #v2
---
v2:
- Fix an error unwind in
Any sleeping dma_resv lock taken while the vma pages_mutex is held
will cause a lockdep splat.
Move the i915_gem_object_pin_pages() call out of the pages_mutex
critical section.
Signed-off-by: Thomas Hellström
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_vma.c | 29
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulnerable to user-space
triggered kernel BUGs if the
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts to use a fast prefetching memcpy and
otherwise falls
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König #v4
--
v4:
- Clarify when we try drm_memcpy_from_wc_dbm (Reported by Matthew Auld)
- Be paranoid about when
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fault().
Instead, implement a method mapping
Embed a struct ttm_buffer_object into the i915 gem object, making sure
we alias the gem object part. It's a bit unfortunate that the
struct ttm_buffer_ojbect embeds a gem object since we otherwise could
make the TTM part private to the TTM backend, and use the usual
i915 gem object for the other
We are currently sharing the VM reservation locks across a number of
gem objects with page-table memory. Since TTM will individiualize the
reservation locks when freeing objects, including accessing the shared
locks, make sure that the shared locks are not freed until that is done.
For PPGTT we
All users of this function actually want the dma segment sizes, but that's
not what's calculated. Fix that and rename the function to
i915_sg_dma_sizes to reflect what's calculated.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2
This is an initial patch series to move discrete memory management over to
TTM. It will be followed up shortly with adding more functionality.
The buddy allocator is temporarily removed along with its selftests and
It is replaced with the TTM range manager and some selftests are adjusted
to
On 21/05/2021 15:49, Vinod Koul wrote:
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions upto 4k. For more resolutions like 8k this won't
work.
Furthermore, we can use 1 DSC encoder in lesser resulutions, but that is
not power efficient according to
On 21/05/2021 15:49, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc
enabled and pass this to .setup_intf_cfg()
On 21/05/2021 15:49, Vinod Koul wrote:
This add the bits in RM to enable the DSC blocks
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3
On 21/05/2021 15:49, Vinod Koul wrote:
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 26 +++
On 21/05/2021 15:49, Vinod Koul wrote:
DSC needs some configuration from device tree, add support to read and
store these params and add DSC structures in msm_drv
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 170 +
Hi Tomi,
Le ven., mai 28 2021 at 08:59:15 +0300, Tomi Valkeinen
a écrit :
On 28/05/2021 02:03, Paul Cercueil wrote:
The previous commit wrongly assumed that dma_mmap_wc() could be
replaced
by pgprot_writecombine() + dma_mmap_pages(). It did work on my setup,
but did not work everywhere.
Use DEVICE_ATTR_RO() helper instead of plain DEVICE_ATTR(),
which makes the code a bit shorter and easier to read.
Signed-off-by: YueHaibing
---
drivers/gpu/drm/i915/i915_pmu.c | 8 +++-
drivers/gpu/drm/i915/i915_sysfs.c | 30 +++---
2 files changed, 18
On 5/21/21 11:09 AM, Daniel Vetter wrote:
No need to set it explicitly.
Signed-off-by: Daniel Vetter
Cc: Laurentiu Palcu
Cc: Lucas Stach
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: Philipp Zabel
Cc: Paul Cercueil
Cc:
[AMD Official Use Only]
Inline.
>-Original Message-
>From: Koenig, Christian
>Sent: Thursday, May 27, 2021 7:51 PM
>To: Yu, Lang ; amd-...@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Huang, Ray ; Deucher, Alexander
>; Olsak, Marek
>Subject: Re: [PATCH 2/2]
On 2021/5/27 18:04, Jani Nikula wrote:
> On Thu, 27 May 2021, Zhen Lei wrote:
>> If intel_hdcp_validate_v_prime() has been successful within the allowed
>> number of tries, we can directly call drm_dbg_kms() and "goto out" without
>> jumping out of the loop and repeatedly judging whether the
In the function amdgpu_uvd_cs_msg(), every branch in the switch
statement will have a return, so the code below the switch statement
will not be executed.
Eliminate the follow smatch warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:845 amdgpu_uvd_cs_msg() warn:
ignoring unreachable code.
There is not much value in the extra conversion step, the calculations
required for the LTDC IP are different than what is used in the
drm_display_mode_to_videomode(), so just do the right ones in the LTDC
driver right away.
Signed-off-by: Marek Vasut
Signed-off-by: Yannick Fertre
---
Hello Thomas,
On 5/22/21 7:14 AM, Thomas Zimmermann wrote:
[snip]
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -127,6 +127,7 @@ config ARM
>> select PERF_USE_VMALLOC
>> select RTC_LIB
>> select SET_FS
>> +select SYSFB
>
> Don't select this as part of the
On Fri, 2021-05-28 at 09:16 +0200, Christian König wrote:
> Am 27.05.21 um 17:51 schrieb Thomas Hellström:
> > On Thu, 2021-05-27 at 17:32 +0200, Christian König wrote:
> > > Am 27.05.21 um 17:05 schrieb Thomas Hellström:
> > > > On Thu, 2021-05-27 at 17:01 +0200, Thomas Hellström wrote:
> > > > >
Quoting Joonas Lahtinen (2021-05-28 10:25:57)
> Hi Dave & Daniel,
>
> Here's drm-intel-gt-next pull request.
>
> Most notably it has the reworked DG1 uAPI (behind CONFIG_BROKEN)
> as requested. Important fix for Gitlab issues #3293 and #3450 and
> one another kernel crash. Adds missing
Hi Dave & Daniel,
Here's drm-intel-gt-next pull request.
Most notably it has the reworked DG1 uAPI (behind CONFIG_BROKEN)
as requested. Important fix for Gitlab issues #3293 and #3450 and
one another kernel crash. Adds missing workarounds for Gen11 and
Gen12. Hiding of modparams for compiled-out
Use DEVICE_ATTR_RW() helper instead of plain DEVICE_ATTR(),
which makes the code a bit shorter and easier to read.
Signed-off-by: YueHaibing
---
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git
Use DEVICE_ATTR_RW() helper instead of plain DEVICE_ATTR(),
which makes the code a bit shorter and easier to read.
Signed-off-by: YueHaibing
---
drivers/gpu/drm/radeon/radeon_pm.c | 56 --
1 file changed, 23 insertions(+), 33 deletions(-)
diff --git
Am 27.05.21 um 17:51 schrieb Thomas Hellström:
On Thu, 2021-05-27 at 17:32 +0200, Christian König wrote:
Am 27.05.21 um 17:05 schrieb Thomas Hellström:
On Thu, 2021-05-27 at 17:01 +0200, Thomas Hellström wrote:
On Thu, 2021-05-27 at 16:54 +0200, Christian König wrote:
Am 27.05.21 um 16:19
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/video/fbdev/intelfb/intelfb_i2c.c: In function 'intelfb_gpio_setscl':
drivers/video/fbdev/intelfb/intelfb_i2c.c:58:6: warning:
variable ‘val’ set but not used [-Wunused-but-set-variable]
drivers/video/fbdev/intelfb/intelfb_i2c.c: In function
On 28.05.2021 03:13, John Harrison wrote:
> On 5/26/2021 10:58, Matthew Brost wrote:
>> On Wed, May 26, 2021 at 02:36:18PM +0200, Michal Wajdeczko wrote:
>>> On 26.05.2021 08:42, Matthew Brost wrote:
Ensure H2G buffer updates are visible before descriptor tail updates by
inserting a
Hi Alyssa,
Will this be enough to implement GL_TIMESTAMP and GL_TIME_ELAPSED queries?
Guess the DDK implements these as WRITE_VALUE jobs, and there's also a
soft job BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME that I guess is used for
glGet*(GL_TIMESTAMP). Other DRM drivers use an ioctl for that
Hi Patrice, Alain,
Could you help to take a look at this patchset, thanks.
This series is the rebase to the newest kernel commit:
88b06399c9c766c283e070b022b5ceafa4f63f19
according to the request from:
https://lore.kernel.org/lkml/ff2bc09d-1a17-50d4-d3ee-16fd3a86d...@foss.st.com/
The clk bug
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