Am 10.11.21 um 05:31 schrieb xinhui pan:
BO might sit in a wrong lru list as there is a small period of memory
moving and lru list updating.
Lets skip eviction if we hit such mismatch.
Suggested-by: Christian König
Signed-off-by: xinhui pan
Reviewed-by: Christian König for the series.
Am 10.11.21 um 08:09 schrieb Jackie Liu:
From: Jackie Liu
HDMI 8996 PHY/PLL support need common clk. avoid like:
[...]
x86_64-linux-gnu-ld: drivers/gpu/drm/msm/hdmi/hdmi_phy.o:(.rodata+0x3e0):
undefined reference to `msm_hdmi_phy_8996_cfg'
Fixes: e17afdceb4f2 ("drm/msm/hdmi: HDMI 8996 PHY/PL
From: Jackie Liu
Let's select RATIONAL with dp driver. avoid like:
[...]
x86_64-linux-gnu-ld: drivers/gpu/drm/msm/dp/dp_catalog.o: in function
`dp_catalog_ctrl_config_msa':
dp_catalog.c:(.text+0x57e): undefined reference to `rational_best_approximation'
Fixes: c943b4948b58 ("drm/msm/dp: add di
From: Jackie Liu
HDMI 8996 PHY/PLL support need common clk. avoid like:
[...]
x86_64-linux-gnu-ld: drivers/gpu/drm/msm/hdmi/hdmi_phy.o:(.rodata+0x3e0):
undefined reference to `msm_hdmi_phy_8996_cfg'
Fixes: e17afdceb4f2 ("drm/msm/hdmi: HDMI 8996 PHY/PLL support")
Reported-by: kernelbot
Signed-
From: Jackie Liu
In fact, this will not cause any problems, but when COMPILE_TEST is
enabled, COMMON_CLK may not be selected, The CI system will report
some compilation errors. even if that is not issue, but we better fix
him.
[...]
x86_64-linux-gnu-ld: drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.o
On 09/11/2021 16:55, Nishanth Menon wrote:
On 12:40-20210921, Nishanth Menon wrote:
Add MODULE_DEVICE_TABLE to the device tree table to create required
aliases needed for module to be loaded with device tree based platform.
Fixes: e19233955d9e ("drm/bridge: Add Cadence DSI driver")
Signed-off-b
From: ran jianping
Fix the following coccicheck review:
./drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c:1174:14-18
:Unneeded variable
Remove unneeded variable used to store return value.
Reported-by: Zeal Robot
Signed-off-by: ran jianping
---
drivers/gpu/drm/amd/pm/swsmu/smu11/sien
Enable runtime pm autosuspend by default for gen12 and
later versions.
Signed-off-by: Tilak Tangudu
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index eaf7688
Enable runtime pm autosuspend by default for all Gen12
and Gen12+ platforms
Tilak Tangudu (1):
drm/i915/rpm: Enable runtime pm autosuspend by default
drivers/gpu/drm/i915/intel_runtime_pm.c | 4
1 file changed, 4 insertions(+)
--
2.25.1
On Tue, Nov 9, 2021 at 6:24 PM Adam Ford wrote:
>
> On Tue, Nov 9, 2021 at 11:34 AM Tim Harvey wrote:
> >
> > Add nodes for MIPI DSI and LCDIF on IMX8MM
> >
> > I'm currently working with a set of patches to convert drm/exynos
> > to a bridge [1] and add IMX8MM support [2] in order to get IMX8MM
BO might sit in a wrong lru list as there is a small period of memory
moving and lru list updating.
Lets skip eviction if we hit such mismatch.
Suggested-by: Christian König
Signed-off-by: xinhui pan
---
drivers/gpu/drm/ttm/ttm_bo.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
After we move BO to a new memory region, we should put it to
the new memory manager's lru list regardless we unlock the resv or not.
Cc: sta...@vger.kernel.org
Reviewed-by: Christian König
Signed-off-by: xinhui pan
---
drivers/gpu/drm/ttm/ttm_bo.c | 2 ++
1 file changed, 2 insertions(+)
diff -
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
If SmartDMA is supported by the hardware, SSPPs allow using two RGB
layers per the hardware pipe (with some additional restrictions, like
no
support for scaling, etc). Register additional planes (two per the
SSPP)
and check if we can use multirect d
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Client driven prefetch (CDP) is properly setup only for SSPP REC0
currently. Enable client driven prefetch also for SSPP REC1.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 12 +++
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Downstream driver uses dpu->caps->smart_dma_rev to update
sspp->cap->features with the bit corresponding to the supported
SmartDMA
version. Upstream driver does not do this, resulting in SSPP subdriver
not enbaling setup_multirect callback. Make SSPP
On Wed, 10 Nov 2021 at 04:35, wrote:
>
> On 2021-11-09 12:21, Dmitry Baryshkov wrote:
> > On Tue, 9 Nov 2021 at 23:15, wrote:
> >>
> >> On 2021-07-04 18:21, Dmitry Baryshkov wrote:
> >> > Stop limiting zpos property values, we use normalized_zpos anyway. And
> >> > nothing stops userspace from as
Hi Doug
On 11/9/2021 10:04 AM, Douglas Anderson wrote:
If you happened to try to access `/dev/drm_dp_aux` devices provided by
the MSM DP AUX driver too early at bootup you could go boom. Let's
avoid that by only allowing AUX transfers when the controller is
powered up.
Specifically the crash th
On 2021-11-09 12:21, Dmitry Baryshkov wrote:
On Tue, 9 Nov 2021 at 23:15, wrote:
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
> Stop limiting zpos property values, we use normalized_zpos anyway. And
> nothing stops userspace from assigning several planes to a single zpos
> (it is a userspace b
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Add support for handling and allocting SSPP blocks through the resource
manager. Handling code is not converted to use it though.
Signed-off-by: Dmitry Baryshkov
Conceptually this is identical to the previous attempt from QC on this:
https://patch
On Tue, Nov 9, 2021 at 11:34 AM Tim Harvey wrote:
>
> Add nodes for MIPI DSI and LCDIF on IMX8MM
>
> I'm currently working with a set of patches to convert drm/exynos
> to a bridge [1] and add IMX8MM support [2] in order to get IMX8MM DSI
> working for display with a Raspberry Pi DSI touchscreen c
Hi Dave and Daniel,
Here goes drm-intel-next-fixes-2021-11-09:
Couple Reverts, build fix, couple virtualization fixes,
blank screen and other display rates fixes, and more.
Four patches targeting stable in here.
Display Fixes:
- DP rates related fixes (Imre, Jani)
- A Revert on disaling dual eD
On Tue, Nov 09, 2021 at 02:48:50PM +0300, Dan Carpenter wrote:
> The "ret" variable is checked on the previous line so we know it's
> zero. No need to check again.
>
> Signed-off-by: Dan Carpenter
Reviewed-by: Rodrigo Vivi
and pushed.
thanks for the patch
> ---
> drivers/gpu/drm/i915/displa
On 2021-11-09 10:04, Douglas Anderson wrote:
If you happened to try to access `/dev/drm_dp_aux` devices provided by
the MSM DP AUX driver too early at bootup you could go boom. Let's
avoid that by only allowing AUX transfers when the controller is
powered up.
Specifically the crash that was seen
Quoting Krishna Manikandan (2021-11-09 01:47:28)
> In the current implementation, substring comparison
> using device node name is used to find mdp node
> during driver probe. Use compatible string list instead
> of node name to get mdp node from the parent mdss node.
>
> Signed-off-by: Krishna Man
Quoting Bjorn Andersson (2021-11-06 10:22:46)
> Since '8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon
> Chipsets")' the hpd_high member of struct dp_usbpd has been write-only.
>
> Let's clean up the code a little bit by removing the writes as well.
>
> Signed-off-by: Bjorn Anderss
On Tue, Nov 09, 2021 at 03:47:58PM -0500, Harry Wentland wrote:
> On 2021-11-08 04:54, Pekka Paalanen wrote:
> > On Thu, 4 Nov 2021 12:27:56 -0400
> > Harry Wentland wrote:
> >
> >> On 2021-11-04 04:38, Pekka Paalanen wrote:
> >>> On Wed, 3 Nov 2021 11:08:13 -0400
> >>> Harry Wentland wrote:
> >
On Tue, 2021-11-09 at 00:58 +, Nadav Amit wrote:
> > On Nov 8, 2021, at 4:37 PM, Joe Perches wrote:
> > On Mon, 2021-11-08 at 16:22 -0800, Srivatsa S. Bhat wrote:
> >
> > So it's an exploder not an actual maintainer and it likely isn't
> > publically archived with any normal list mechanism.
>
On 2021-11-09 16:45, Ville Syrjälä wrote:
> On Tue, Nov 09, 2021 at 03:19:47PM -0500, Harry Wentland wrote:
>> On 2021-11-05 08:59, Ville Syrjälä wrote:
>>> On Wed, Nov 03, 2021 at 11:10:37AM -0400, Harry Wentland wrote:
On 2021-09-06 17:38, Uma Shankar wrote:
> Define the str
On Tue, Nov 09, 2021 at 03:19:47PM -0500, Harry Wentland wrote:
> On 2021-11-05 08:59, Ville Syrjälä wrote:
> > On Wed, Nov 03, 2021 at 11:10:37AM -0400, Harry Wentland wrote:
> >>
> >>
> >> On 2021-09-06 17:38, Uma Shankar wrote:
> >>> Define the structure with XE_LPD degamma lut ranges. HDR and S
On Tue, Nov 09, 2021 at 12:06:48PM -0800, Sultan Alsawaf wrote:
> Hi,
>
> I encountered a printk deadlock on 5.13 which appears to still affect the
> latest
> kernel. The deadlock occurs due to printk being used while having the current
> CPU's runqueue locked, and the underlying framebuffer cons
From: Kuogee Hsieh
Current DP drivers have regulators, clocks, irq and phy are grouped
together within a function and executed not in a symmetric manner.
This increase difficulty of code maintenance and limited code scalability.
This patch divided the driver life cycle of operation into four stat
> Am 09.11.2021 um 21:42 schrieb H. Nikolaus Schaller :
>
>> So you want to update these properties to add the HDMI clock setting, like
>> this:
>>
>> assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
>> <&cgu JZ4780_CLK_HDMI>;
>> assigned-clock-parents = <0>, <&cg
On Tue, Nov 9, 2021 at 12:39 PM Marek Vasut wrote:
>
> On 11/9/21 8:35 PM, Adam Ford wrote:
>
> [...]
>
> >> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> >> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> >> index 208a0ed840f4..195dcbff7058 100644
> >> --- a/arch/arm64/boot/dts/freescal
On 2021-11-08 04:54, Pekka Paalanen wrote:
> On Thu, 4 Nov 2021 12:27:56 -0400
> Harry Wentland wrote:
>
>> On 2021-11-04 04:38, Pekka Paalanen wrote:
>>> On Wed, 3 Nov 2021 11:08:13 -0400
>>> Harry Wentland wrote:
>>>
On 2021-09-06 17:38, Uma Shankar wrote:
> Existing LUT precisio
> Am 09.11.2021 um 21:36 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
> Le mar., nov. 9 2021 at 21:19:17 +0100, H. Nikolaus Schaller
> a écrit :
>> Hi Paul,
>>> Am 07.11.2021 um 20:05 schrieb Paul Cercueil :
6. Therefore I think it *may* work overclocked with 48MHz
but is not guarant
On Tue, Nov 9, 2021 at 11:36 AM Adam Ford wrote:
>
> On Tue, Nov 9, 2021 at 11:34 AM Tim Harvey wrote:
> >
> > Add nodes for MIPI DSI and LCDIF on IMX8MM
> >
> > I'm currently working with a set of patches to convert drm/exynos
> > to a bridge [1] and add IMX8MM support [2] in order to get IMX8MM
On 11/9/21 8:35 PM, Adam Ford wrote:
[...]
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 208a0ed840f4..195dcbff7058 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -188,6 +188,1
Hi Nikolaus,
Le mar., nov. 9 2021 at 21:19:17 +0100, H. Nikolaus Schaller
a écrit :
Hi Paul,
Am 07.11.2021 um 20:05 schrieb Paul Cercueil :
6. Therefore I think it *may* work overclocked with 48MHz
but is not guaranteed or reliable above 27 MHz.
So everything is ok here.
One thing t
On 2021-11-05 07:49, Ville Syrjälä wrote:
> On Thu, Nov 04, 2021 at 12:27:56PM -0400, Harry Wentland wrote:
>>
>>
>> On 2021-11-04 04:38, Pekka Paalanen wrote:
>>> On Wed, 3 Nov 2021 11:08:13 -0400
>>> Harry Wentland wrote:
>>>
On 2021-09-06 17:38, Uma Shankar wrote:
> Existing LUT pre
On Tue, 9 Nov 2021 at 23:15, wrote:
>
> On 2021-07-04 18:21, Dmitry Baryshkov wrote:
> > Stop limiting zpos property values, we use normalized_zpos anyway. And
> > nothing stops userspace from assigning several planes to a single zpos
> > (it is a userspace bug, but the kernel is forgiving about i
On 2021-11-05 08:59, Ville Syrjälä wrote:
> On Wed, Nov 03, 2021 at 11:10:37AM -0400, Harry Wentland wrote:
>>
>>
>> On 2021-09-06 17:38, Uma Shankar wrote:
>>> Define the structure with XE_LPD degamma lut ranges. HDR and SDR
>>> planes have different capabilities, implemented respective
>>> struct
Hi Paul,
> Am 07.11.2021 um 20:05 schrieb Paul Cercueil :
>
>> 6. Therefore I think it *may* work overclocked with 48MHz
>> but is not guaranteed or reliable above 27 MHz.
>> So everything is ok here.
>
> One thing though - the "assigned-clocks" and "assigned-clock-rates", while it
> works here
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Stop limiting zpos property values, we use normalized_zpos anyway. And
nothing stops userspace from assigning several planes to a single zpos
(it is a userspace bug, but the kernel is forgiving about it).
Userspace assigning several planes to a singl
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Add DPU_SSPP_CSC_ANY denoting any CSC block. As we are at it, rewrite
DPU_SSPP_SCALER (any scaler) to use BIT(x) instead of hand-coded
bitshifts.
This can go independent of the multi-rect series, so can you please take
this with the
first half of th
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
As we are going to add virtual planes, add the list of supported
formats
to the hw catalog entry. It will be used to setup universal planes,
with
later selecting a pipe depending on whether the YUV format is used for
the framebuffer.
Signed-off-by:
On Tue, Nov 9, 2021 at 11:34 AM Tim Harvey wrote:
>
> Add nodes for MIPI DSI and LCDIF on IMX8MM
>
> I'm currently working with a set of patches to convert drm/exynos
> to a bridge [1] and add IMX8MM support [2] in order to get IMX8MM DSI
> working for display with a Raspberry Pi DSI touchscreen c
Add nodes for MIPI DSI and LCDIF on IMX8MM
I'm currently working with a set of patches to convert drm/exynos
to a bridge [1] and add IMX8MM support [2] in order to get IMX8MM DSI
working for display with a Raspberry Pi DSI touchscreen compatible with
a Toshiba TC358762 DSI bridge and Powertip PH8
From: Rob Clark
Add a debugfs interface to ignore hw error irqs, in order to force
fallback to sw hangcheck mechanism. Because the hw error detection is
pretty good on newer gens, we need this for igt tests to test the sw
hang detection.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno
From: Rob Clark
Add some helpers for fence comparision, which handle rollover properly,
and stop open coding fence seqno comparisions.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.h | 12
drivers/gpu/drm/msm/msm_gpu.c | 6 +++---
drivers/gpu/drm/msm/msm_gpu.h |
From: Rob Clark
The remaining struct_mutex usage is just to serialize various gpu
related things (submit/retire/recover/fault/etc), so replace
struct_mutex with gpu->lock.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 ++--
drivers/gpu/drm/msm/adreno/adreno_devic
From: Rob Clark
cur_ctx_seqno already does the same thing, but handles the edge cases
where a refcnt'd context can live after lastclose. So let's not have
two ways to do the same thing.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 3 +--
drivers/gpu/drm/msm/adreno/a3x
From: Rob Clark
The struct_mutex locking is a remnant from the days before per-obj locks,
and no longer needed.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_debugfs.c | 37 ++-
drivers/gpu/drm/msm/msm_fbdev.c | 13 ---
2 files changed, 16 insertion
From: Rob Clark
This started out as conversion to using drm/sched to handle job timeout,
recovery, and retire (and delete a bunch of code), but the latter part
is on hold until drm/sched is fixed to properly handle job retire/
cleanup before deciding which job triggered the fault/timeout[1]. But
If you happened to try to access `/dev/drm_dp_aux` devices provided by
the MSM DP AUX driver too early at bootup you could go boom. Let's
avoid that by only allowing AUX transfers when the controller is
powered up.
Specifically the crash that was seen (on Chrome OS 5.4 tree with
relevant backports
On Tue, Nov 9, 2021 at 11:38 AM Jagan Teki wrote:
>
> On Tue, Nov 9, 2021 at 11:04 PM Tim Harvey wrote:
> >
> > Add nodes for MIPI DSI and LCDIF on IMX8MM
> >
> > I'm currently working with a set of patches to convert drm/exynos
> > to a bridge [1] and add IMX8MM support [2] in order to get IMX8M
On Tue, Nov 9, 2021 at 11:04 PM Tim Harvey wrote:
>
> Add nodes for MIPI DSI and LCDIF on IMX8MM
>
> I'm currently working with a set of patches to convert drm/exynos
> to a bridge [1] and add IMX8MM support [2] in order to get IMX8MM DSI
> working for display with a Raspberry Pi DSI touchscreen c
On 09/11/2021 17:19, Lucas De Marchi wrote:
On Tue, Nov 09, 2021 at 12:17:59PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
On igfx + dgfx setups, it appears that intel_iommu=igfx_off option only
disables the igfx iommu. Stop relying on global intel_iommu_gfx_mapped
and probe presence o
On Tue, Nov 09, 2021 at 12:17:59PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
On igfx + dgfx setups, it appears that intel_iommu=igfx_off option only
disables the igfx iommu. Stop relying on global intel_iommu_gfx_mapped
and probe presence of iommu domain per device to accurately reflect
On 11/8/21 11:54 PM, Pavel Machek wrote:
Hi!
This series is truncated .. I only got first patches. Similary, 5.10
series is truncated, [PATCH AUTOSEL 5.10 035/101] media: s5p-mfc: Add
checking to s5p_mfc_probe... is last one I got.
I got all the patches before that, so I believe it is not probl
On 9/27/21 7:26 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
The meaning of the 'imply' keyword has changed recently, and neither the
old meaning (select the symbol if its dependencies are met) nor the new
meaning (enable it by default, but let the user set any other setting)
is what we want he
On 11/8/2021 4:29 PM, Bjorn Andersson wrote:
On Mon 08 Nov 15:42 PST 2021, Kuogee Hsieh wrote:
From: Kuogee Hsieh
Combo phy supports both USB and DP simultaneously. There may has a
possible conflict during phy initialization phase between USB and
DP driver which may cause USB phy timeout wh
On Tue, Nov 9, 2021 at 1:07 AM Daniel Vetter wrote:
>
> On Mon, Nov 08, 2021 at 03:39:17PM -0800, Rob Clark wrote:
> > I stumbled across this thread when I ran into the same issue, while
> > working out how to move drm/msm to use scheduler's retire +
> > timeout/recovery (and get rid of our own mi
Den 09.11.2021 15.56, skrev Thomas Zimmermann:
> Hi,
>
> thanks for looking through all this code.
>
> Am 09.11.21 um 14:04 schrieb Noralf Trønnes:
>>
>>
>> Den 09.11.2021 13.38, skrev Thomas Zimmermann:
>>>
>>>
>>> Am 08.11.21 um 21:55 schrieb Noralf Trønnes:
Den 01.11.2021 15.
Hi,
thanks for looking through all this code.
Am 09.11.21 um 14:04 schrieb Noralf Trønnes:
Den 09.11.2021 13.38, skrev Thomas Zimmermann:
Am 08.11.21 um 21:55 schrieb Noralf Trønnes:
Den 01.11.2021 15.15, skrev Thomas Zimmermann:
Enable the FB_DAMAGE_CLIPS property to reduce display-up
09.11.2021 17:17, Dmitry Osipenko пишет:
> 09.11.2021 17:08, Dmitry Osipenko пишет:
>>> +static void host1x_drm_dev_deinit(struct host1x_device *dev)
>>> +{
>>> + struct drm_device *drm = dev_get_drvdata(&dev->dev);
>> And platform_unregister_drivers() should be moved here.
>>
>
> Nah, that shou
09.11.2021 17:08, Dmitry Osipenko пишет:
>> +static void host1x_drm_dev_deinit(struct host1x_device *dev)
>> +{
>> +struct drm_device *drm = dev_get_drvdata(&dev->dev);
> And platform_unregister_drivers() should be moved here.
>
Nah, that should cause deadlock. This ad-hoc is too lame.
Anoth
09.11.2021 16:52, Dmitry Osipenko пишет:
> 09.11.2021 12:19, Daniel Vetter пишет:
>> On Mon, Nov 08, 2021 at 09:16:07PM +0300, Dmitry Osipenko wrote:
>>> 08.11.2021 18:17, Daniel Vetter пишет:
On Mon, Nov 08, 2021 at 02:08:21AM +0300, Dmitry Osipenko wrote:
> Use drm_dp_aux_register_ddc/ch
In general the correct idea, but the wrong place to check that.
Calling amdgpu_ttm_bo_eviction_valuable() is only optional, but that
check must be mandatory for correct operation.
This needs to be inside ttm_bo_evict_swapout_allowable().
Christian.
Am 09.11.21 um 14:41 schrieb Pan, Xinhui:
On 04/11/21 12:46 am, Matthew Auld wrote:
> On 25/10/2021 14:00, Arunpravin wrote:
>> On contiguous allocation, we round up the size
>> to the *next* power of 2, implement a function
>> to free the unused pages after the newly allocate block.
>>
>> Signed-off-by: Arunpravin
>
> Ideally this ge
09.11.2021 12:19, Daniel Vetter пишет:
> On Mon, Nov 08, 2021 at 09:16:07PM +0300, Dmitry Osipenko wrote:
>> 08.11.2021 18:17, Daniel Vetter пишет:
>>> On Mon, Nov 08, 2021 at 02:08:21AM +0300, Dmitry Osipenko wrote:
Use drm_dp_aux_register_ddc/chardev() helpers that allow to register I2C
[AMD Official Use Only]
yes, a double check is needed.
how about change below.
As long as we detect such mismatch, it indicates another eviction is on going.
return false here is reasonable.
@@ -1335,6 +1336,8 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct
ttm_buffer_object *bo,
Hi drm/bridge maintainers,
On 29/10/2021 15:59, Neil Armstrong wrote:
> The current ELD handling takes the internal connector ELD buffer and
> shares it to the I2S and AHB sub-driver.
>
> But with DRM_BRIDGE_ATTACH_NO_CONNECTOR, the connector is created
> elsewhere (not not), and an eventual conn
Hi Tomi,
On 12/10/2021 15:39, Neil Armstrong wrote:
> From: Tomi Valkeinen
>
> DSS5's maximum tv pclk rate (i.e. HDMI) is set to 186MHz, which comes
> from the TRM (DPLL_HDMI_CLK1 frequency must be lower than 186 MHz). To
> support DRA76's wide screen HDMI feature, we need to increase this
> max
Hi,
On 27/10/2021 14:50, Tomi Valkeinen wrote:
> On 18/10/2021 17:28, Neil Armstrong wrote:
>> From: Benoit Parrot
>>
>> If the drm_plane has a source width that's greater than the max width
>> supported by a single hw overlay, then we assign a 'r_overlay' to it in
>> omap_plane_atomic_check().
>
On Tue, 9 Nov 2021 at 12:47, Krishna Manikandan
wrote:
>
> In the current implementation, substring comparison
> using device node name is used to find mdp node
> during driver probe. Use compatible string list instead
> of node name to get mdp node from the parent mdss node.
>
> Signed-off-by: Kr
Exactly that's the reason why we should have the double check in TTM
I've mentioned in the other mail.
Christian.
Am 09.11.21 um 14:16 schrieb Pan, Xinhui:
[AMD Official Use Only]
Actually this patch does not totally fix the mismatch of lru list with mem_type as
mem_type is changed in ->move
Yeah, but that should never happen in the first place.
Even when the BO is on the wrong LRU TTM should check that beforehand.
In other words when we pick a BO from the LRU we should still double
check bo->resource->mem_type to make sure it is what we are searching for.
Christian.
Am 09.11.21
[AMD Official Use Only]
Actually this patch does not totally fix the mismatch of lru list with mem_type
as mem_type is changed in ->move() and lru list is changed after that.
During this small period, another eviction could still happed and evict this
mismatched BO from sMam(say, its lru list i
On 27/10/2021 10:30, Tomi Valkeinen wrote:
> On 27/10/2021 11:29, Tomi Valkeinen wrote:
>> On 18/10/2021 17:28, Neil Armstrong wrote:
>>> Call drm_atomic_helper_check_plane_state() from the plane
>>> atomic_check() callback in order to add plane state sanity
>>> checking.
>>>
>>> It will permit fil
Den 09.11.2021 10.06, skrev Thomas Zimmermann:
> Hi
>
> Am 08.11.21 um 22:01 schrieb Noralf Trønnes:
>>
>>
>> Den 01.11.2021 15.15, skrev Thomas Zimmermann:
>>> Add constants for the maximum size of the shadow-plane surface
>>> size. Useful for shadow planes with virtual screen sizes. The
>>> c
[AMD Official Use Only]
Yes, a stable tag is needed. vulkan guys say 5.14 hit this issue too.
I think that amdgpu_bo_move() does support copy from sysMem to sysMem correctly.
maybe something below is needed.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu
Den 09.11.2021 13.38, skrev Thomas Zimmermann:
>
>
> Am 08.11.21 um 21:55 schrieb Noralf Trønnes:
>>
>>
>> Den 01.11.2021 15.15, skrev Thomas Zimmermann:
>>> Enable the FB_DAMAGE_CLIPS property to reduce display-update
>>> overhead. Also fixes a warning in the kernel log.
>>>
>>> simple-fra
There is just one core thread, in order to separate different
hardware, using codec type to separeate it in scp driver.
Signed-off-by: Yunfei Dong
Reviewed-By: AngeloGioacchino Del Regno
---
fix spelling mistakes.
---
.../media/platform/mtk-vcodec/vdec_ipi_msg.h | 12 ---
.../media/platfo
Vdec and venc can use the same function to wake up interrupt event.
Reviewed-by: Tzung-Bi Shih
Reviewed-By: AngeloGioacchino Del Regno
Signed-off-by: Yunfei Dong
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 9 +
drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h |
There are only two lines in mtk_vcodec_release_dec_pm, using
pm_runtime_disable and put_device instead directly.
Move pm_runtime_enable outside mtk_vcodec_init_dec_pm to symmetry with
pm_runtime_disable, after that, rename mtk_vcodec_init_dec_pm to *_clk since
it only has clock operations now.
Si
There are only two lines in mtk_vcodec_release_enc_pm, using
pm_runtime_disable and put_device instead directly.
Move pm_runtime_enable outside mtk_vcodec_release_enc_pm to symmetry with
pm_runtime_disable, after that, rename mtk_vcodec_init_enc_pm to *_clk since
it only has clock operations now.
Generalizes power and clock on/off interfaces to support different hardware.
Signed-off-by: Yunfei Dong
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 6 +-
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.c | 2 +-
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.h | 4 +
.../platform/mtk-vcodec/
Add core dec and dec end ipi msg: AP_IPIMSG_DEC_CORE/AP_IPIMSG_DEC_CORE_END.
Signed-off-by: Yunfei Dong
Reviewed-By: AngeloGioacchino Del Regno
---
.../media/platform/mtk-vcodec/vdec_ipi_msg.h | 4
.../media/platform/mtk-vcodec/vdec_vpu_if.c| 12
.../media/platform/mtk
Adds decoder dt-bindings for mt8192.
Signed-off-by: Yunfei Dong
---
fix comments and rename yaml file.
---
.../media/mediatek,vcodec-subdev-decoder.yaml | 261 ++
1 file changed, 261 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/mediatek,vcodec-subdev
Add work queue to process core hardware information.
First, get lat_buf from message queue, then call core
hardware of each codec(H264/VP9/AV1) to decode, finally
puts lat_buf back to the message.
Signed-off-by: Yunfei Dong
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 16 +++-
.../pla
Use the dma_set_mask_and_coherent helper to set vdec
DMA bit mask to support 34bits iova space(16GB) that
the mt8192 iommu HW support.
Whole the iova range separate to 0~4G/4G~8G/8G~12G/12G~16G,
regarding which iova range VDEC actually locate, it
depends on the dma-ranges property of vdec dtsi nod
For lat and core architecture, lat thread will send message to core
thread when lat decode done. Core hardware will use the message
from lat to decode, then free message to lat thread when decode done.
Signed-off-by: Yunfei Dong
---
drivers/media/platform/mtk-vcodec/Makefile| 1 +
.../plat
From: Yunfei Dong
Adds MT8192's compatible "mediatek,mt8192-vcodec-dec".
Adds MT8192's device private data mtk_lat_sig_core_pdata.
Signed-off-by: Yunfei Dong
---
.../media/platform/mtk-vcodec/mtk_vcodec_dec.h | 1 +
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 4
.../mtk-vcodec/
For add new hardware, not only need to lock lat hardware, also
need to lock core hardware in case of different instance start
to decoder at the same time.
Signed-off-by: Yunfei Dong
Reviewed-By: AngeloGioacchino Del Regno
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 4 ++--
dri
Adds irq interface for multi hardware.
Signed-off-by: Yunfei Dong
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 33 +--
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.c | 2 +-
.../platform/mtk-vcodec/mtk_vcodec_drv.h | 25 ++
.../platform/mtk-vcodec/mtk_vcod
Separates different architecture for hardware: pure_sin_core
and lat_sin_core. MT8183 is pure single core. Uses .hw_arch to
distinguish.
Signed-off-by: Yunfei Dong
Reviewed-By: AngeloGioacchino Del Regno
---
.../platform/mtk-vcodec/mtk_vcodec_dec_stateful.c | 1 +
.../platform/mtk-vcodec
Separate decoder and encoder document for the dts are big difference.
Reviewed-by: Rob Herring
Signed-off-by: Yunfei Dong
---
.../media/mediatek,vcodec-decoder.yaml| 176 +
.../media/mediatek,vcodec-encoder.yaml| 187 ++
.../bindings/media/mediatek
This series adds support for multi hardware decode into mtk-vcodec, by first
adding use
of_platform_populate to manage each hardware information: interrupt, clock,
register
bases and power. Secondly add core work queue to deal with core hardware
message,
at the same time, add msg queue for diffe
Need to build decoder pm file as module for main device
and subdev use the same pm interface.
Signed-off-by: Yunfei Dong
---
drivers/media/platform/mtk-vcodec/Makefile| 6 --
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 9 +
2 files changed, 13 insertions(+), 2
Manage each hardware information which includes irq/power/clk.
The hardware includes LAT0, LAT1 and CORE.
Signed-off-by: Yunfei Dong
Reported-by: kernel test robot
---
drivers/media/platform/mtk-vcodec/Makefile| 5 +-
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 119 +
.../
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