: d36d68fd1925d33066d52468b7c7c6aca6521248
patch link:
https://lore.kernel.org/r/20230404012741.116502-14-dakr%40redhat.com
patch subject: [PATCH drm-next v3 13/15] drm/nouveau: nvkm/vmm: implement raw
ops to manage uvmm
config: arc-randconfig-r043-20230403
(https://download.01.org/0day-ci/archive/20230404
: d36d68fd1925d33066d52468b7c7c6aca6521248
patch link:
https://lore.kernel.org/r/20230404012741.116502-5-dakr%40redhat.com
patch subject: [PATCH drm-next v3 04/15] drm: manager to keep track of GPUs VA
mappings
config: mips-randconfig-r024-20230403
(https://download.01.org/0day-ci/archive/20230404/202304041336
On 2023-03-28 04:54, Lucas Stach wrote:
> Hi Danilo,
>
> Am Dienstag, dem 28.03.2023 um 02:57 +0200 schrieb Danilo Krummrich:
>> Hi all,
>>
>> Commit df622729ddbf ("drm/scheduler: track GPU active time per entity")
>> tries to track the accumulated time that a job was active on the GPU
>> writin
Hi Danilo,
kernel test robot noticed the following build warnings:
[auto build test WARNING on d36d68fd1925d33066d52468b7c7c6aca6521248]
url:
https://github.com/intel-lab-lkp/linux/commits/Danilo-Krummrich/drm-execution-context-for-GEM-buffers-v3/20230404-093042
base: d36d68fd1925d33066d52
EFI FB, VESA FB or VGA FB etc are belong to firmware based framebuffer
driver.
Signed-off-by: Sui Jingfeng
---
drivers/video/aperture.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/video/aperture.c b/drivers/video/aperture.c
index 41e77de1ea82..b009468ffd
Hi Andrew,
kernel test robot noticed the following build warnings:
[auto build test WARNING on char-misc/char-misc-testing]
[also build test WARNING on char-misc/char-misc-next char-misc/char-misc-linus
soc/for-next pza/reset/next linus/master v6.3-rc5 next-20230403]
[If your patch is applied
Hi Marek,
Thank you for the patch.
On Mon, Apr 03, 2023 at 09:02:42PM +0200, Marek Vasut wrote:
> Do not generate the HS front and back porch gaps, the HSA gap and
> EOT packet, as per "SN65DSI83 datasheet SLLSEC1I - SEPTEMBER 2012
> - REVISED OCTOBER 2020", page 22, these packets are not require
On 2023/3/29 17:04, Thomas Zimmermann wrote:
(cc'ing Lucas)
Hi
Am 25.03.23 um 08:46 schrieb Sui Jingfeng:
The assignment already done in drm_client_buffer_vmap(),
just trival clean, no functional change.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
drivers/gpu/drm/drm_fbdev_ge
From: Jagan Teki
Samsung MIPI DSIM bridge can be found on Exynos and NXP's
i.MX8M Mini/Nano/Plus SoCs.
Convert exynos_dsim.txt to yaml.
Used the example node from exynos5433.dtsi instead of the one used in
the legacy exynos_dsim.txt.
Signed-off-by: Jagan Teki
Signed-off-by: Fabio Estevam
--
Hi Ville,
Thank you for the patch.
On Tue, Apr 04, 2023 at 01:36:52AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Include the device and connector information in the SCDC
> debugs. Makes it easier to figure out who did what.
>
> v2: Rely on connector->ddc (Maxime)
>
> Cc: Andrzej Ha
On 3 Apr 2023 17:47:50 +0200 Paul Cercueil
> This function can be used to initiate a scatter-gather DMA transfer
> where the DMA addresses and lengths are located inside arrays.
>
> The major difference with dmaengine_prep_slave_sg() is that it supports
> specifying the lengths of each DMA transf
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout
with i.MX8MP and i.MX93.
There is no LVDS CTRL register on the i.MX6SX, so only write to
this register on the appropriate SoCs.
Add support for the i.MX6SX LDB.
Tested on a imx6sx-sdb board with a H
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register
layout with i.MX8MP and i.MX93.
Signed-off-by: Fabio Estevam
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Marek Vasut
---
Changes since v2:
- Collected Reviewed-by tags.
- Improved the Subject by not sta
On Tue, Apr 04, 2023 at 10:07:48AM +0900, Asahi Lina wrote:
> Hi, thanks for the Cc!
>
No problem.
> On 04/04/2023 09.22, Matthew Brost wrote:
> > Hello,
> >
> > As a prerequisite to merging the new Intel Xe DRM driver [1] [2], we
> > have been asked to merge our common DRM scheduler patches fi
From: Jagan Teki
Samsung MIPI DSIM bridge can be found on Exynos and NXP's
i.MX8M Mini/Nano/Plus SoCs.
Convert exynos_dsim.txt to yaml.
Used the example node from exynos5433.dtsi instead of the one used in
the legacy exynos_dsim.txt.
Signed-off-by: Jagan Teki
Signed-off-by: Fabio Estevam
--
On 3/30/23 12:42, Fabio Estevam wrote:
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register
layout with i.MX8MP and i.MX93.
Signed-off-by: Fabio Estevam
Nit: you are not adding 'support' for the IP here, you are documenting
bindings in this patch. The su
This commit provides the implementation for the new uapi motivated by the
Vulkan API. It allows user mode drivers (UMDs) to:
1) Initialize a GPU virtual address (VA) space via the new
DRM_IOCTL_NOUVEAU_VM_INIT ioctl for UMDs to specify the portion of VA
space managed by the kernel and usersp
Provide the driver indirection iterating over all DRM GPU VA spaces to
enable the common 'gpuvas' debugfs file for dumping DRM GPU VA spaces.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_debugfs.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a
The new VM_BIND UAPI uses the DRM GPU VA manager to manage the VA space.
Hence, we a need a way to manipulate the MMUs page tables without going
through the internal range allocator implemented by nvkm/vmm.
This patch adds a raw interface for nvkm/vmm to pass the resposibility
for managing the add
smatch reports
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c:610:1: warning: symbol
'gv100_disp_core_mthd_base' was not declared. Should it be static?
This variable is only used in one file so it should be static.
Signed-off-by: Tom Rix
---
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
The new VM_BIND UAPI implementation introduced in subsequent commits
will allow asynchronous jobs processing push buffers and emitting fences.
If a job times out, we need a way to recover from this situation. For
now, simply kill the channel to unblock all hung up jobs and signal
userspace that th
The new VM_BIND UAPI implementation introduced in subsequent commits
will allow asynchronous jobs processing push buffers and emitting
fences.
If a fence context is killed, e.g. due to a channel fault, jobs which
are already queued for execution might still emit new fences. In such a
case a job wo
The new (VM_BIND) UAPI exports DMA fences through DRM syncobjs. Hence,
in order to emit fences within DMA fence signalling critical sections
(e.g. as typically done in the DRM GPU schedulers run_job() callback) we
need to separate fence allocation and fence emitting.
Signed-off-by: Danilo Krummric
Move the usercopy helpers to a common driver header file to make it
usable for the new API added in subsequent commits.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_drv.h | 26 ++
drivers/gpu/drm/nouveau/nouveau_gem.c | 26 --
Initialize the GEM's DRM GPU VA manager interface in preparation for the
(u)vmm implementation, provided by subsequent commits, to make use of it.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/nouve
Provide a getter function for the client's current vmm context. Since
we'll add a new (u)vmm context for UMD bindings in subsequent commits,
this will keep the code clean.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_chan.c |
This commit adds a function to dump a DRM GPU VA space and a macro for
drivers to register the struct drm_info_list 'gpuvas' entry.
Most likely, most drivers might maintain one DRM GPU VA space per struct
drm_file, but there might also be drivers not having a fixed relation
between DRM GPU VA spac
This commit provides the interfaces for the new UAPI motivated by the
Vulkan API. It allows user mode drivers (UMDs) to:
1) Initialize a GPU virtual address (VA) space via the new
DRM_IOCTL_NOUVEAU_VM_INIT ioctl. UMDs can provide a kernel reserved
VA area.
2) Bind and unbind GPU VA space ma
Split up the MA_STATE() macro such that components using the maple tree
can easily inherit from struct ma_state and build custom tree walk
macros to hide their internals from users.
Example:
struct sample_iterator {
struct ma_state mas;
struct sample_mgr *mgr;
};
\#define SAMPLE_
On 3/30/23 12:42, Fabio Estevam wrote:
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout
with i.MX8MP and i.MX93.
There is no LVDS CTRL register on the i.MX6SX, so only write to
this register on the appropriate SoCs.
Add support for the i.MX6SX LD
Add infrastructure to keep track of GPU virtual address (VA) mappings
with a decicated VA space manager implementation.
New UAPIs, motivated by Vulkan sparse memory bindings graphics drivers
start implementing, allow userspace applications to request multiple and
arbitrary GPU VA mappings of buffe
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/drm_exec.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_exec.c b/drivers/gpu/drm/drm_exec.c
index df546cc5a227..f645d22a0863 100644
--- a/drivers/gpu/drm/drm_exec.c
+++ b/drivers/gpu/drm/drm_exec.c
@@ -62,7 +62,6 @@ sta
From: Christian König
This adds the infrastructure for an execution context for GEM buffers
which is similar to the existinc TTMs execbuf util and intended to replace
it in the long term.
The basic functionality is that we abstracts the necessary loop to lock
many different GEM buffers with auto
This patch series provides a new UAPI for the Nouveau driver in order to
support Vulkan features, such as sparse bindings and sparse residency.
Furthermore, with the DRM GPUVA manager it provides a new DRM core feature to
keep track of GPU virtual address (VA) mappings in a more generic way.
The
Hi Qiang,
On Mon, 3 Apr 2023 16:51:27 +0800 Qiang Yu wrote:
>
> I think you can just revert the following three lima commits when merge:
> * 4a66f3da99dc ("drm/lima: add show_fdinfo for drm usage stats")
> * 87767de835ed ("drm/lima: allocate unique id per drm_file")
> * bccafec957a5 ("drm/lima: a
Hi, thanks for the Cc!
On 04/04/2023 09.22, Matthew Brost wrote:
Hello,
As a prerequisite to merging the new Intel Xe DRM driver [1] [2], we
have been asked to merge our common DRM scheduler patches first as well
as develop a common solution for long running workloads with the DRM
scheduler. Th
On Mon, Apr 03, 2023 at 02:33:34PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> A pair of pre-Gen12 registers were being included in the Gen12 capture
> list. GuC was rejecting those as being invalid and logging errors
> about them. So, stop doing it.
Looks like these regist
On 04/04/2023 00:38, Jessica Zhang wrote:
On 4/2/2023 4:21 AM, Dmitry Baryshkov wrote:
On 31/03/2023 21:49, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Changes in v2:
- Moved files up to msm/ directory
- Dropped get_comp
Long running dma-fences are not allowed to be exported, a drm_syncobj is
designed to be exported to the user, so add a warn if drm_syncobj
install long running dna-fences as this is not allowed.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/drm_syncobj.c | 5 -
1 file changed, 4 insertion
If the TDR is set to a very small value it can fire before the run wq is
started in the function drm_sched_start. The run wq is expected to
running when the TDR fires, fix this ordering so this expectation is
always met.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/scheduler/sched_main.c | 4
From: Thomas Hellström
Make the drm scheduler aware of long-running dma fences by
* Enable marking a sched entity as producing long-running fences.
* Disallowing long-running fences as dependencies for non-long-running
sched entities, while long-running sched entities allow those.
Signed-off-
Rather than a global modparam for scheduling policy, move the scheduling
policy to scheduler / entity so user can control each scheduler / entity
policy.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/etnaviv/etnaviv_sched.c| 3 ++-
drive
Add generic schedule message interface which sends messages to backend
from the drm_gpu_scheduler main submission thread. The idea is some of
these messages modify some state in drm_sched_entity which is also
modified during submission. By scheduling these messages and submission
in the same thread
Hello,
As a prerequisite to merging the new Intel Xe DRM driver [1] [2], we
have been asked to merge our common DRM scheduler patches first as well
as develop a common solution for long running workloads with the DRM
scheduler. This RFC series is our first attempt at doing this. We
welcome any and
Add helper to set TDR timeout and restart the TDR with new timeout
value. This will be used in XE, new Intel GPU driver, to trigger the TDR
to cleanup drm_sched_entity that encounter errors.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/scheduler/sched_main.c | 18 ++
include/
DRM_SCHED_POLICY_SINGLE_ENTITY creates a 1 to 1 relationship between
scheduler and entity. No priorities or run queue used in this mode.
Intended for devices with firmware schedulers.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/scheduler/sched_entity.c | 58 +
drivers/gp
From: Thomas Hellström
For long-running workloads, drivers either need to open-code completion
waits, invent their own synchronization primitives or internally use
dma-fences that do not obey the cross-driver dma-fence protocol, but
without any lockdep annotation all these approaches are error pr
If the TDR is set to a value, it can fire before a job is submitted in
drm_sched_main. The job should be always be submitted before the TDR
fires, fix this ordering.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/scheduler/sched_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
In XE, the new Intel GPU driver, a choice has made to have a 1 to 1
mapping between a drm_gpu_scheduler and drm_sched_entity. At first this
seems a bit odd but let us explain the reasoning below.
1. In XE the submission order from multiple drm_sched_entity is not
guaranteed to be the same completi
On 4/3/23 23:15, Francesco Dolcini wrote:
On Mon, Apr 03, 2023 at 04:06:22PM -0500, Rob Herring wrote:
On Thu, Mar 30, 2023 at 12:17:51PM +0200, Francesco Dolcini wrote:
From: Francesco Dolcini
SN65DSI8[34] device supports burst video mode and non-burst video mode
with sync events or with syn
From: Ville Syrjälä
Include the device and connector information in the SCDC
debugs. Makes it easier to figure out who did what.
v2: Rely on connector->ddc (Maxime)
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Robert Foss
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Thierry R
On 03/04/2023 22:07, Abhinav Kumar wrote:
On 4/3/2023 11:48 AM, Dmitry Baryshkov wrote:
On 03/04/2023 21:06, Abhinav Kumar wrote:
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
This huge series attempts to restructure the DPU HW catalog into a
manageable and reviewable data set. In order to
On 4/3/2023 2:51 PM, Dmitry Baryshkov wrote:
On 04/04/2023 00:45, Jessica Zhang wrote:
On 4/2/2023 4:27 AM, Dmitry Baryshkov wrote:
On 31/03/2023 21:49, Jessica Zhang wrote:
Correct the math for slice_last_group_size so that it matches the
calculations downstream.
Fixes: c110cfd1753e ("d
Do not generate the HS front and back porch gaps, the HSA gap and
EOT packet, as these packets are not required. This makes the bridge
work with Samsung DSIM on i.MX8MM and i.MX8MP.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jagan Teki
Cc: Jernej S
Do not generate the HS front and back porch gaps, the HSA gap and
EOT packet, as these packets are not required. This makes the bridge
work with Samsung DSIM on i.MX8MM and i.MX8MP.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jagan Teki
Cc: Jernej S
On 4/1/2023 2:37 AM, Dmitry Baryshkov wrote:
On 01/04/2023 03:57, Abhinav Kumar wrote:
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
From: Konrad Dybcio
These blocks are of variable length on different SoCs. Set the
correct values where I was able to retrieve it from downstream
DTs and l
On 04/04/2023 00:45, Jessica Zhang wrote:
On 4/2/2023 4:27 AM, Dmitry Baryshkov wrote:
On 31/03/2023 21:49, Jessica Zhang wrote:
Correct the math for slice_last_group_size so that it matches the
calculations downstream.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Signed-of
On 4/2/2023 4:29 AM, Dmitry Baryshkov wrote:
On 31/03/2023 21:49, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods to configure DSC for DSI.
Changes in V2:
- *_calculate_initial_scale_value --> *_set_initial_scale_value
- Split pkt_per_line and eol_byte_num changes to a separate patch
On 4/2/2023 4:27 AM, Dmitry Baryshkov wrote:
On 31/03/2023 21:49, Jessica Zhang wrote:
Correct the math for slice_last_group_size so that it matches the
calculations downstream.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Signed-off-by: Jessica Zhang
Reviewed-by: Dmitry B
On 4/2/2023 4:21 AM, Dmitry Baryshkov wrote:
On 31/03/2023 21:49, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Changes in v2:
- Moved files up to msm/ directory
- Dropped get_comp_ratio() helper
- Used drm_int2fixp() to c
From: John Harrison
A pair of pre-Gen12 registers were being included in the Gen12 capture
list. GuC was rejecting those as being invalid and logging errors
about them. So, stop doing it.
Signed-off-by: John Harrison
Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state
ca
On Mon, Apr 03, 2023 at 04:01:17PM -0500, Rob Herring wrote:
> On Fri, Mar 31, 2023 at 11:40:01AM +0200, Francesco Dolcini wrote:
> > On Fri, Mar 31, 2023 at 10:48:15AM +0200, Krzysztof Kozlowski wrote:
> > > On 30/03/2023 11:59, Francesco Dolcini wrote:
> > > > From: Francesco Dolcini
> > > >
>
On Mon, Mar 13, 2023 at 12:30:50AM +0100, Erico Nunes wrote:
> lima maintains a context manager per drm_file, similar to amdgpu.
> In order to account for the complete usage per drm_file, all of the
> associated contexts need to be considered.
> Previously released contexts also need to be accounte
On Mon, Apr 03, 2023 at 04:06:22PM -0500, Rob Herring wrote:
> On Thu, Mar 30, 2023 at 12:17:51PM +0200, Francesco Dolcini wrote:
> > From: Francesco Dolcini
> >
> > SN65DSI8[34] device supports burst video mode and non-burst video mode
> > with sync events or with sync pulses packet transmission
On Mon, Apr 03, 2023 at 04:01:17PM -0500, Rob Herring wrote:
> On Fri, Mar 31, 2023 at 11:40:01AM +0200, Francesco Dolcini wrote:
> > On Fri, Mar 31, 2023 at 10:48:15AM +0200, Krzysztof Kozlowski wrote:
> > > On 30/03/2023 11:59, Francesco Dolcini wrote:
> > > > From: Francesco Dolcini
> > > >
>
On Thu, Mar 30, 2023 at 12:17:51PM +0200, Francesco Dolcini wrote:
> From: Francesco Dolcini
>
> SN65DSI8[34] device supports burst video mode and non-burst video mode
> with sync events or with sync pulses packet transmission as described in
> the DSI specification.
>
> Add property to select t
On Fri, Mar 31, 2023 at 11:40:01AM +0200, Francesco Dolcini wrote:
> On Fri, Mar 31, 2023 at 10:48:15AM +0200, Krzysztof Kozlowski wrote:
> > On 30/03/2023 11:59, Francesco Dolcini wrote:
> > > From: Francesco Dolcini
> > >
> > > Add new toshiba,input-rgb-mode property to describe the actual sign
On 4/3/23 20:54, Christian König wrote:
Am 03.04.23 um 21:40 schrieb Joshua Ashton:
Hello all!
I would like to propose a new API for allowing processes to control
the priority of GPU queues similar to RLIMIT_NICE/RLIMIT_RTPRIO.
The main reason for this is for compositors such as Gamescope a
On 3/30/23 18:32, Emil Velikov wrote:
>> +static int virtio_gpu_dma_fence_wait(struct virtio_gpu_submit *submit,
>> + struct dma_fence *fence)
>> +{
>> +struct dma_fence_unwrap itr;
>> +struct dma_fence *f;
>> +int err;
>> +
>> +dma_fence_unwrap_for_e
Am 03.04.23 um 21:40 schrieb Joshua Ashton:
Hello all!
I would like to propose a new API for allowing processes to control
the priority of GPU queues similar to RLIMIT_NICE/RLIMIT_RTPRIO.
The main reason for this is for compositors such as Gamescope and
SteamVR vrcompositor to be able to create
On Mon, Apr 03, 2023 at 07:39:37PM +, Yang, Fei wrote:
> >Subject: Re: [PATCH 5/7] drm/i915: use pat_index instead of cache_level
> >
> >On Mon, Apr 03, 2023 at 04:57:21PM +, Yang, Fei wrote:
> >>> Subject: Re: [PATCH 5/7] drm/i915: use pat_index instead of
> >>> cache_level
> >>>
> >>> On
Am 03.04.23 um 21:40 schrieb Joshua Ashton:
This allows AMDGPU scheduler priority above normal to be expressed
using the DRM_SCHED_PRIORITY enum.
That was rejected before, I just don't remember why exactly. Need to dig
that up again.
Christian.
Signed-off-by: Joshua Ashton
---
drivers/
Add support for the new RLIMIT_GPUPRIO when doing the priority
checks creating an amdgpu_ctx.
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/driver
This allows it to be used by other parts of the codebase without fear
of a circular include dependency being introduced.
Signed-off-by: Joshua Ashton
---
include/drm/drm_sched_priority.h | 41
include/drm/gpu_scheduler.h | 15 +---
2 files changed, 4
Introduce a new RLIMIT that allows the user to set a runtime limit on
the GPU scheduler priority for tasks.
This avoids the need for leased compositors such as SteamVR's
vrcompositor to be launched via a setcap'ed executable with
CAP_SYS_NICE.
This is required for SteamVR as it doesn't run as a D
This allows AMDGPU scheduler priority above normal to be expressed
using the DRM_SCHED_PRIORITY enum.
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +-
drivers/gpu/drm/msm/msm_gpu.h | 2 +-
include/drm/gpu_scheduler.h | 1 +
3 files changed, 3
Hello all!
I would like to propose a new API for allowing processes to control
the priority of GPU queues similar to RLIMIT_NICE/RLIMIT_RTPRIO.
The main reason for this is for compositors such as Gamescope and
SteamVR vrcompositor to be able to create realtime async compute
queues on AMD without
>Subject: Re: [PATCH 5/7] drm/i915: use pat_index instead of cache_level
>
>On Mon, Apr 03, 2023 at 04:57:21PM +, Yang, Fei wrote:
>>> Subject: Re: [PATCH 5/7] drm/i915: use pat_index instead of
>>> cache_level
>>>
>>> On Fri, Mar 31, 2023 at 11:38:28PM -0700, fei.y...@intel.com wrote:
Fro
On 4/1/23 3:35 AM, Christian Gmeiner wrote:
Hi Andrew
Okay, will split for v2.
Was there a follow-up v2 of this patchset? AFAICT this series did not
make it into the mainline kernel.
Do you have any plans to work on it? If not I would like to help out
as we have a use case where we want t
This new export type exposes to userspace the SRAM area as a DMA-BUF Heap,
this allows for allocations of DMA-BUFs that can be consumed by various
DMA-BUF supporting devices.
Signed-off-by: Andrew Davis
---
Changes from v1:
- Use existing DT flags, if both pool(device usable) and export(userspa
On 4/3/2023 11:48 AM, Dmitry Baryshkov wrote:
On 03/04/2023 21:06, Abhinav Kumar wrote:
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
This huge series attempts to restructure the DPU HW catalog into a
manageable and reviewable data set. In order to ease review and testing
I merged all the
Do not generate the HS front and back porch gaps, the HSA gap and
EOT packet, as per "SN65DSI83 datasheet SLLSEC1I - SEPTEMBER 2012
- REVISED OCTOBER 2020", page 22, these packets are not required.
This makes the TI SN65DSI83 bridge work with Samsung DSIM on i.MX8MN.
Signed-off-by: Marek Vasut
--
On 03/04/2023 21:06, Abhinav Kumar wrote:
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
This huge series attempts to restructure the DPU HW catalog into a
manageable and reviewable data set. In order to ease review and testing
I merged all the necessary fixes into this series. Also I cherry-pi
Hi Jonathan,
Le lundi 03 avril 2023 à 10:05 -0600, Jonathan Corbet a écrit :
> Paul Cercueil writes:
>
> One nit:
>
> > Document the new DMABUF based API.
> >
> > Signed-off-by: Paul Cercueil
> > Cc: Jonathan Corbet
> > Cc: linux-...@vger.kernel.org
> >
> > ---
> > v2: - Explicitly state th
There are several calls to ci_dpm_fini() in ci_dpm_init() when there
occur errors in functions like r600_parse_extended_power_table().
This is harmful as it can lead to double free situations: for
instance, r600_parse_extended_power_table() will call for
r600_free_extended_power_table() as will ci_
> -Original Message-
> From: De Marchi, Lucas
> Sent: Wednesday, March 29, 2023 8:46 PM
> To: Srivatsa, Anusha
> Cc: intel...@lists.freedesktop.org; Harrison, John C
> ; Ceraolo Spurio, Daniele
> ; dri-devel@lists.freedesktop.org; Daniel
> Vetter ; Dave Airlie
> Subject: Re: [PATCH 3/
On 03/04/23 12:33, Maíra Canal wrote:
> Hi Arthur,
>
> On 3/27/23 10:38, Arthur Grillo wrote:
>> Insert test for the drm_rect_intersect() function, it also create a
>> helper for comparing drm_rects more easily.
>>
>> Signed-off-by: Arthur Grillo
>> ---
>> drivers/gpu/drm/tests/drm_rect_test
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
This huge series attempts to restructure the DPU HW catalog into a
manageable and reviewable data set. In order to ease review and testing
I merged all the necessary fixes into this series. Also I cherry-picked
& slightly fixed Konrad's patch addin
On Mon, Apr 3, 2023 at 9:25 AM Nathan Chancellor wrote:
>
> On Mon, Apr 03, 2023 at 09:03:14AM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > This should fix a crash that was reported on ast (and possibly other
> > drivers which do not initialize vblank).
> >
> >fbcon: Taking over consol
On Fri, Mar 31, 2023 at 07:41:46PM -0700, Ashutosh Dixit wrote:
> On ATSM the PL1 limit is disabled at power up. The previous uapi assumed
> that the PL1 limit is always enabled and therefore did not have a notion of
> a disabled PL1 limit. This results in erroneous PL1 limit values when the
> PL1
On 3/27/2023 9:54 AM, Jeffrey Hugo wrote:
This series introduces a driver under the accel subsystem (QAIC -
Qualcomm AIC) for the Qualcomm Cloud AI 100 product (AIC100). AIC100 is
a PCIe adapter card that hosts a dedicated machine learning inference
accelerator.
The previous version (v4) can be
On Mon, Apr 03, 2023 at 04:57:21PM +, Yang, Fei wrote:
> > Subject: Re: [PATCH 5/7] drm/i915: use pat_index instead of cache_level
> >
> > On Fri, Mar 31, 2023 at 11:38:28PM -0700, fei.y...@intel.com wrote:
> >> From: Fei Yang
> >>
> >> Currently the KMD is using enum i915_cache_level to set
Loongson display controller IP has been integrated in both Loongson north
bridge chipsets(ls7a1000/ls7a2000) and SoCs(ls2k1000/ls2k2000), it has been
included in Loongson self-made BMC products.
This display controller is a PCI device in all of chips mentiond, it has
two display pipes which suppor
This patch add myself as maintainer to drm loongson driver
Signed-off-by: Sui Jingfeng
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9736e04d3bd3..d258c5b54407 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6919,6 +6919,13 @@ T:
> Subject: Re: [PATCH 5/7] drm/i915: use pat_index instead of cache_level
>
> On Fri, Mar 31, 2023 at 11:38:28PM -0700, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> Currently the KMD is using enum i915_cache_level to set caching policy for
>> buffer objects. This is flaky because the PAT ind
Hi, Xinlei:
Xinlei Lee (李昕磊) 於 2023年4月3日 週一 下午5:18寫道：
>
> On Mon, 2023-04-03 at 11:49 +0800, Chun-Kuang Hu wrote:
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> >
> >
> > Hi, Xinlei:
> >
> > 於 2023年3月29日 週三 下午2:43寫道：
>
On Mon, Apr 03, 2023 at 09:35:32AM -0700, Matt Roper wrote:
> On Mon, Apr 03, 2023 at 07:02:08PM +0300, Ville Syrjälä wrote:
> > On Fri, Mar 31, 2023 at 11:38:30PM -0700, fei.y...@intel.com wrote:
> > > From: Fei Yang
> > >
> > > To comply with the design that buffer objects shall have immutable
On Mon, 2023-04-03 at 18:23 +0200, Matthieu Baerts wrote:
> Since v6.3, checkpatch.pl now complains about the use of "Closes:" tags
> followed by a link [1]. It also complains if a "Reported-by:" tag is
> followed by a "Closes:" one [2].
All these patches seems sensible, thanks.
Assuming Linus ap
Hi, Julien:
Julien Stephan 於 2023年4月3日 週一 下午3:20寫道：
>
> From: Phi-bang Nguyen
>
> This is a new driver that supports the MIPI CSI CD-PHY for mediatek
> mt8365 soc
>
> Signed-off-by: Louis Kuo
> Signed-off-by: Phi-bang Nguyen
> [Julien Stephan: use regmap]
> [Julien Stephan: use GENMASK]
> Co-d
On Mon, Apr 03, 2023 at 07:02:08PM +0300, Ville Syrjälä wrote:
> On Fri, Mar 31, 2023 at 11:38:30PM -0700, fei.y...@intel.com wrote:
> > From: Fei Yang
> >
> > To comply with the design that buffer objects shall have immutable
> > cache setting through out its life cycle, {set, get}_caching ioctl
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