From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a
From: Fei Yang
This series introduce a new extension for GEM_CREATE,
1. end support for set caching ioctl [PATCH 1/2]
2. add set_pat extension for gem_create [PATCH 2/2]
v2: drop one patch that was merged separately
commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
v3: rebased
Hi Andi, :)
> -Original Message-
> From: Andi Shyti
> Sent: Friday, May 19, 2023 9:27 AM
> To: Inki Dae
> Cc: dri-devel@lists.freedesktop.org; linux-samsung-...@vger.kernel.org; Andi
> Shyti
> Subject: Re: [PATCH] drm/exynos: vidi: fix a wrong error return
>
> Hi Inki,
>
> On Fri,
The Starry-himax83102-j02 panel is a TDDI IC. From the datasheet[1],
it seems that the touch can communicate successfully only when the RST
signal is high. Since i2c_hid_core_probe comes after boe_panel_prepare
let's set the default high for RST at boe_panel_add.
[1]:
gt;ctx_mgr);
| ^
Caused by commit
2458393a4e98 ("drm/amdgpu: keep amdgpu_ctx_mgr in ctx structure")
I have used the amdgpu tree from next-20230518 for today.
There is no need to assign a result to temp varable just to return it
after a goto. Drop the temporary variable and goto and return the result
directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 ++
1 file changed, 2 insertions(+), 8
There is no need to assign a result to temp varable just to return it
two lines below. Drop the temporary variable.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use them to get the instance index.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 72
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +--
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 ++
There is no reason to split the dpu_encoder interface into separate
_init() and _setup() phases. Merge them into a single function.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 55 +
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20
1 file changed, 8
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on dpu_rm_get_wb() returning NULL for indices for which the
WB is not present on the device.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
Rework dpu_encoder initialization code, simplifying calling sequences
and separating common init parts.
Changes since v1:
- Withdrawn two pathes for a later consideration
- Changed dpu_encoder_phys_init() to return void (Abhinav)
- Added small simplifications of dpu_encoder_phys_cmd_init() and
Hi Inki,
On Fri, May 19, 2023 at 02:26:40AM +0200, Andi Shyti wrote:
> Hi Inki,
>
> On Fri, May 19, 2023 at 09:04:07AM +0900, Inki Dae wrote:
> > Fix a wrong error return by dropping an error return.
> >
> > When vidi driver is remvoed, if ctx->raw_edid isn't same as fake_edid_info
> > then
Writeback was the last user of dpu_encoder_phys_ops's atomic_check()
callback. As the code was moved to the dpu_writeback.c, the callback
becomes unused. Drop it now.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 ---
dpu_encoder_phys_wb is the only user of encoder's atomic_check callback.
Move corresponding checks to drm_writeback_connector's implementation
and drop the dpu_encoder_phys_wb_atomic_check() function.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 54
The writeback backend of the dpu_encoder is the only user of the
dpu_encoder_phys_ops::atomic_check() callback. Move corresponding code
to the DPU's drm_writeback_connector implementation (dpu_writeback.c)
and drop corresponding callback code.
Dependency chanin:
-
On 19/05/2023 02:46, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
This decision to use encoder id instead of CRTC has been there
On Thu, May 18, 2023 at 7:29 PM Fabio Estevam wrote:
>
> Hi Adam,
>
> On Thu, May 18, 2023 at 8:06 PM Adam Ford wrote:
> >
> > This series fixes the blanking pack size and the PMS calculation. It then
> > adds support to allows the DSIM to dynamically DPHY clocks, and support
> > non-burst mode
Hi Adam,
On Thu, May 18, 2023 at 8:06 PM Adam Ford wrote:
>
> This series fixes the blanking pack size and the PMS calculation. It then
> adds support to allows the DSIM to dynamically DPHY clocks, and support
> non-burst mode while allowing the removal of the hard-coded clock values
> for the
On 5/18/2023 3:37 PM, Dmitry Baryshkov wrote:
On Fri, 19 May 2023 at 01:17, Jessica Zhang wrote:
On 5/17/2023 5:19 PM, Dmitry Baryshkov wrote:
On 16/05/2023 23:20, Jessica Zhang wrote:
Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
comes with the Qualcomm HDK8350
Hi Inki,
On Fri, May 19, 2023 at 09:04:07AM +0900, Inki Dae wrote:
> Fix a wrong error return by dropping an error return.
>
> When vidi driver is remvoed, if ctx->raw_edid isn't same as fake_edid_info
> then only what we have to is to free ctx->raw_edid so that driver removing
> can work
Hi,
> -Original Message-
> From: dri-devel On Behalf Of Uwe
> Kleine-Konig
> Sent: Monday, May 15, 2023 6:16 PM
> To: Inki Dae
> Cc: linux-samsung-...@vger.kernel.org; Jingoo Han ;
> Seung-Woo Kim ; Kyungmin Park
> ; dri-devel@lists.freedesktop.org; Krzysztof
> Kozlowski ;
| ctx->ctx_mgr = &(fpriv->ctx_mgr);
| ^
Caused by commit
2458393a4e98 ("drm/amdgpu: keep amdgpu_ctx_mgr in ctx structure")
I have used the amdgpu tree from next-20230518 for today.
--
Cheers,
Stephen Rothwell
pgp8QV8SOcZyQ.pgp
Descript
Fix a wrong error return by dropping an error return.
When vidi driver is remvoed, if ctx->raw_edid isn't same as fake_edid_info
then only what we have to is to free ctx->raw_edid so that driver removing
can work correctly - it's not an error case.
Signed-off-by: Inki Dae
---
Hi Krzysztof,
On Thu, May 11, 2023 at 07:54:46PM +0200, Krzysztof Kozlowski wrote:
> Statically allocated array of pointers to hwmon_channel_info can be made
> const for safety.
>
> Acked-by: Jani Nikula
> Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Andi Shyti
Andi
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
This decision to use encoder id instead of CRTC has been there
downstream for quite sometime. So most of the
On 19/05/2023 02:33, Kuogee Hsieh wrote:
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete
Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.
Changes in V10:
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- move both dpu_encoder_unprep_dsc()
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual DSC encoders so both share same base address but with its own
different sub block address.
changes in v4:
-- delete
There are two tiers of pending flush control, main controller and
individual hardware block. Currently only the main controller of
flush mask is reset to 0 but leave out some individual pending flush
mask of particular hardware block keep previous value at
clear_pending_flush(). Reset all
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same time to make it
consistent with the location
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions
to the
Disabling the crossbar mux between DSC and PINGPONG currently
requires a bogus enum dpu_pingpong value to be passed when calling
dsc_bind_pingpong_blk() with enable=false, even though the register
value written is independent of the current PINGPONG block. Replace
that `bool enable` parameter
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
dpu_hw_pp_setup_dsc() and
From: Abhinav Kumar
Some platforms have DSC blocks which have not been declared in the catalog.
Complete DSC 1.1 support for all platforms by adding the missing blocks to
MSM8998 and SC8180X.
Changes in v9:
-- add MSM8998 and SC8180x to commit titil
Changes in v10:
-- fix grammar at commit
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].
[1]:
On 5/17/2023 4:53 PM, Abhinav Kumar wrote:
On 5/14/2023 10:06 AM, Dmitry Baryshkov wrote:
On Sat, 13 May 2023 at 01:39, Abhinav Kumar
wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
The struct dpu_rm_requirements was used to wrap display topology and
hw resources, which meant INTF
The high-speed clock is hard-coded to the burst-clock
frequency specified in the device tree. However, when
using devices like certain bridge chips without burst mode
and varying resolutions and refresh rates, it may be
necessary to set the high-speed clock dynamically based
on the desired pixel
Make the pll-clock-frequency optional. If it's present, use it
to maintain backwards compatibility with existing hardware. If it
is absent, read clock rate of "sclk_mipi" to determine the rate.
Since it can be optional, change the message from an error to
dev_info.
Signed-off-by: Adam Ford
From: Lucas Stach
Scale the blanking packet sizes to match the ratio between HS clock
and DPI interface clock. The controller seems to do internal scaling
to the number of active lanes, so we don't take those into account.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
Tested-by: Chen-Yu
The DPHY timings are currently hard coded. Since the input
clock can be variable, the phy timings need to be variable
too. To facilitate this, we need to cache the hs_clock
based on what is generated from the PLL.
The phy_mipi_dphy_get_default_config_for_hsclk function
configures the DPHY
In order to support variable DPHY timings, it's necessary
to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config
can be used to determine the nominal values for a given resolution
and refresh rate.
Signed-off-by: Adam Ford
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
According to Table 13-45 of the i.MX8M Mini Reference Manual, the min
and max values for M and the frequency range for the VCO_out
calculator were incorrect. This information was contradicted in other
parts of the mini, nano and plus manuals. After reaching out to my
NXP Rep, when confronting
This series fixes the blanking pack size and the PMS calculation. It then
adds support to allows the DSIM to dynamically DPHY clocks, and support
non-burst mode while allowing the removal of the hard-coded clock values
for the PLL for imx8m mini/nano/plus, and it allows the removal of the
On 19/05/2023 01:09, Kuogee Hsieh wrote:
On 5/17/2023 3:31 PM, Marijn Suijten wrote:
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -139,6 +139,11 @@ static inline void
dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
On Fri, 19 May 2023 at 01:17, Jessica Zhang wrote:
>
>
>
> On 5/17/2023 5:19 PM, Dmitry Baryshkov wrote:
> > On 16/05/2023 23:20, Jessica Zhang wrote:
> >> Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
> >> comes with the Qualcomm HDK8350 display expansion pack.
> >>
> >>
Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field,
drop the structure and use corresponding bool directly.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +++---
Rework SSPP and WB code to use common helper for programming QoS
settings.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 31 ++-
Drop support for DPU_PLANE_QOS_VBLANK_CTRL flag. It is not used both
in upstream driver and in vendor SDE driver.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 8
Slightly rearrainge code in dpu_plane_sspp_update_pipe() to group
QoS/LUT related functions.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git
After removal of DPU_PLANE_QOS_VBLANK_CTRL, several fields of struct
dpu_hw_pipe_qos_cfg are fixed to false/0. Drop them from the structure
(and drop the corresponding code from the functions).
The DPU_PLANE_QOS_VBLANK_AMORTIZE flag is also removed, since it is now
a NOP.
Reviewed-by: Jeykumar
This flag is always passed to _dpu_plane_set_qos_ctrl(), so drop it and
remove corresponding conditions from the mentioned function.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 27 +++
1 file changed, 8
Get rid of intermediatory configuration structure and defines. Pass the
format and the enablement bit directly to the new helper. The
WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP
and WB CDP settings.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack the real
CURSOR SSPP. Fix the condition to actually check that the plane is
CURSOR or not.
Reorder SSPP register definitions to sort them in the ascending order.
Move register bitfields after the register definitions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 64 ++---
1 file changed, 32 insertions(+), 32 deletions(-)
diff
Merge SSPP and WB code programming QoS and CDP. This allows us to drop
intermediate structures and duplicate code.
Changes since v2:
- Moved SSPP_VIG_CSC_10_OP_MODE close to other CSC10 defines (Jeykumar)
Changes since v1:
- Fixed kerneldoc for _dpu_plane_set_qos_ctrl()
- Fixed danger_safe_en
On 5/18/2023 2:36 PM, Marijn Suijten wrote:
On 2023-05-19 00:26:33, Dmitry Baryshkov wrote:
On 18/05/2023 22:41, Marijn Suijten wrote:
On 2023-04-28 15:36:46, Abhinav Kumar wrote:
Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
is same as DSPP_SC7180_MASK. Since
On 5/17/2023 5:19 PM, Dmitry Baryshkov wrote:
On 16/05/2023 23:20, Jessica Zhang wrote:
Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
comes with the Qualcomm HDK8350 display expansion pack.
The panel enables display compression (DSC v1.2) by default.
Signed-off-by:
On 5/17/2023 3:31 PM, Marijn Suijten wrote:
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -139,6 +139,11 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct
dpu_hw_ctl *ctx)
CTL_DSPP_n_FLUSH(dspp -
On 19/05/2023 00:39, Marijn Suijten wrote:
On 2023-05-19 00:06:15, Dmitry Baryshkov wrote:
On 18/05/2023 22:14, Marijn Suijten wrote:
On 2023-04-29 04:23:51, Dmitry Baryshkov wrote:
The src_blk declares a lame copy of main SSPP register space. It's
offset is always 0. It's length has been
On 2023-05-19 00:06:15, Dmitry Baryshkov wrote:
> On 18/05/2023 22:14, Marijn Suijten wrote:
> > On 2023-04-29 04:23:51, Dmitry Baryshkov wrote:
> >> The src_blk declares a lame copy of main SSPP register space. It's
> >> offset is always 0. It's length has been fixed to 0x150, while SSPP's
> >
>
On 2023-05-19 00:26:33, Dmitry Baryshkov wrote:
> On 18/05/2023 22:41, Marijn Suijten wrote:
> > On 2023-04-28 15:36:46, Abhinav Kumar wrote:
> >> Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
> >> is same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more
> >
> > is *the*
n = 0x4},
---
base-commit: 798d276b39e984345d52b933a900a71fa0815928
change-id: 20230518-dpu-sc7180-pcc-version-389a2b4ebcb2
Best regards,
--
Marijn Suijten
On 18/05/2023 22:41, Marijn Suijten wrote:
On 2023-04-28 15:36:46, Abhinav Kumar wrote:
Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
is same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more
is *the* same
And, I think, a comma is missing before DSPP_MSM8998_MASK.
On 19/05/2023 00:06, Marijn Suijten wrote:
On 2023-05-05 23:40:32, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
Is this macrotile-qseed? Not
On 21/04/2023 02:05, Konrad Dybcio wrote:
On 21.04.2023 00:41, Dmitry Baryshkov wrote:
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
[...]
+
+static const struct
Dne petek, 05. maj 2023 ob 07:21:08 CEST je Roman Beranek napisal(a):
> While the rate of TCON0's DCLK matches dotclock for parallel and LVDS
> outputs, this doesn't hold for DSI. According manuals from Allwinner,
> DCLK is an abbreviation of Data Clock, not dotclock, so go with that
> instead.
>
Hello,
syzbot has tested the proposed patch and the reproducer did not trigger any
issue:
Reported-and-tested-by: syzbot+0e22d63dcebb802b9...@syzkaller.appspotmail.com
Tested on:
commit: a4422ff2 usb: typec: qcom: Add Qualcomm PMIC Type-C dr..
git tree:
Dne petek, 05. maj 2023 ob 07:21:07 CEST je Roman Beranek napisal(a):
> TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
> however MIPI DSI output only seems to work when PLL_MIPI is selected and
> thus the choice must be hardcoded in.
>
> Currently, this driver can't
On 2023-05-05 23:40:32, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
>
> {.fl = 0, .lut = 0x0011223344556677 },
Is this macrotile-qseed? Not really following where this is supposed
On 18/05/2023 22:14, Marijn Suijten wrote:
On 2023-04-29 04:23:51, Dmitry Baryshkov wrote:
The src_blk declares a lame copy of main SSPP register space. It's
offset is always 0. It's length has been fixed to 0x150, while SSPP's
It's -> its, twice.
Ack
length is now correct. Drop the
On Thu, May 18, 2023 at 09:06:12PM +0200, Helge Deller wrote:
> * Alan Stern :
> > On Thu, May 18, 2023 at 04:16:33PM +0200, Helge Deller wrote:
> > > On 5/18/23 15:54, Alan Stern wrote:
> > > > In this case it looks like dlfb_usb_probe() or one of the routines it
> > > > calls is wrong; it
On Wed, May 17, 2023 at 5:27 PM Chia-I Wu wrote:
>
> On Tue, May 9, 2023 at 11:33 AM Chia-I Wu wrote:
> >
> > Extend the address and size validations to AMDGPU_VA_OP_UNMAP and
> > AMDGPU_VA_OP_CLEAR by moving the validations to amdgpu_gem_va_ioctl.
> >
> > Internal users of amdgpu_vm_bo_map are
On 2023-04-30 00:25:12, Dmitry Baryshkov wrote:
> The driver doesn't support hsic/memcolor and pcc SSPP subblocks.
Double space.
(doesn't support, hence the field members are unused allowing us to drop
them.)
> Drop corresponding definitions.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by:
On 2023-04-28 15:36:46, Abhinav Kumar wrote:
> Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
> is same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more
is *the* same
> than DSPP_MSM8998_MASK, lets drop the latter.
>
> Signed-off-by: Abhinav Kumar
> Reviewed-by: Dmitry
On 2023-04-28 15:36:45, Abhinav Kumar wrote:
> Gamma Correction (GC) and Inverse Gamma Correction(IGC) is
> currently unused. In addition dpu_dspp_sub_blks didn't even have an igc
> member describing the block.
>
> Drop related code from the dpu hardware catalog otherwise this becomes a
> burden
During probe, the driver registers i2c dummy devices and populates the
aux bus, which registers a device for the panel. After doing that, the
driver can still defer probe if needed. This ordering of operations is
troublesome however, because the deferred probe work will retry probing
all pending
On Thu, May 18, 2023 at 04:47:08PM +0200, Paulo Pavacic wrote:
> > So, the driver has to be panel-fannal-c3004.c and binding to be
> > fannal,c3004.yaml.
>
> I believe I have covered this and all the other problems in following
> patch which I will submit as a V3 of the conversation in a
On 2023-04-29 04:23:53, Dmitry Baryshkov wrote:
> Stop using _sspp_subblk_offset() to get offset of the csc_blk. Inline
the offset of.
> this function and use ctx->cap->sblk->csc_blk.base directly.
>
> As this was the last user, drop _sspp_subblk_offset() too.
>
> Reviewed-by: Jeykumar
On 2023-04-29 04:23:52, Dmitry Baryshkov wrote:
> Stop using _sspp_subblk_offset() to get offset of the scaler_blk. Inline
the offset of the...
> this function and use ctx->cap->sblk->scaler_blk.base directly.
>
> Reviewed-by: Jeykumar Sankaran
> Signed-off-by: Dmitry Baryshkov
Much cleaner
On 2023-04-29 04:23:51, Dmitry Baryshkov wrote:
> The src_blk declares a lame copy of main SSPP register space. It's
> offset is always 0. It's length has been fixed to 0x150, while SSPP's
It's -> its, twice.
> length is now correct. Drop the src_blk and access SSPP registers
> without
* Alan Stern :
> On Thu, May 18, 2023 at 04:16:33PM +0200, Helge Deller wrote:
> > On 5/18/23 15:54, Alan Stern wrote:
> > > On Thu, May 18, 2023 at 09:34:24AM +0200, Helge Deller wrote:
> > > > I think this is an informational warning from the USB stack,
> > >
> > > It is not informational. It
On 5/18/2023 12:05 AM, Marijn Suijten wrote:
On 2023-05-17 16:22:37, Abhinav Kumar wrote:
@@ -529,6 +539,19 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk =
{
.features = _features, \
}
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
Hi Dave, Daniel,
Fixes for 6.4.
The following changes since commit f1fcbaa18b28dec10281551dfe6ed3a3ed80e3d6:
Linux 6.4-rc2 (2023-05-14 12:51:40 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.4-2023-05-18
for you to
On Thu, May 18, 2023 at 2:43 AM Tvrtko Ursulin
wrote:
>
>
> In case you were waiting for me looking at the rest of the series, there
> was this reply from the previous round I can expand on.
>
> On 02/05/2023 08:50, Tvrtko Ursulin wrote:
> >
> > On 01/05/2023 17:58, Rob Clark wrote:
> >> On Fri,
Hi,
On 2023/5/18 21:38, Thomas Zimmermann wrote:
Hi,
I don't know the status here, but if it works, you should probably
merge it. I think you first need to get commit access to drm-misc.
That will also allow you to merge the other fixes you sent recently.
See
On Thu, May 18, 2023 at 04:16:33PM +0200, Helge Deller wrote:
> On 5/18/23 15:54, Alan Stern wrote:
> > On Thu, May 18, 2023 at 09:34:24AM +0200, Helge Deller wrote:
> > > I think this is an informational warning from the USB stack,
> >
> > It is not informational. It is a warning that the
Like commit c4f135d643823a86 ("workqueue: Wrap flush_workqueue() using a
macro") says, flush_scheduled_work() is dangerous and will be forbidden.
i915 became the last flush_scheduled_work() user, but developers cannot
find time for auditing which work items does this flush_scheduled_work()
need
On 5/18/2023 7:16 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Whenever KMD maps region larger than 64kB that is both aligned and
contiguous, set contiguous bit (52) in MMU PTE descriptor for each page
in that region.
This allows to treat 16 contiguous pages as one and reduce
number of
On 5/18/23 15:54, Alan Stern wrote:
On Thu, May 18, 2023 at 09:34:24AM +0200, Helge Deller wrote:
* syzbot :
syzbot found the following issue on:
HEAD commit:a4422ff22142 usb: typec: qcom: Add Qualcomm PMIC Type-C dr..
git tree:
On 5/18/2023 7:16 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Simplify and unify naming convention in MMU600 page tables
configuration.
All DMA addresses in page tables directly accessed by VPU are called
with _dma sufix and all CPU pointers to those page tables have _ptr
sufix.
Base
On 5/18/2023 7:16 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Future devices will have different dma bit mask, make it hw specific.
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
On 5/18/2023 7:16 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Program additional fourth level required for mappings with VA above 38bits.
Co-developed-by: Raymond Tan
Signed-off-by: Raymond Tan
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw
On Thu, May 18, 2023 at 09:34:24AM +0200, Helge Deller wrote:
> * syzbot :
> > syzbot found the following issue on:
> >
> > HEAD commit:a4422ff22142 usb: typec: qcom: Add Qualcomm PMIC Type-C dr..
> > git tree:
> > https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
On 5/18/2023 7:16 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
MTL HW only uses StreamId0 and StreamId3 that map to TBU0 and TBU2.
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
Hi,
I don't know the status here, but if it works, you should probably merge
it. I think you first need to get commit access to drm-misc. That will
also allow you to merge the other fixes you sent recently.
See
https://drm.pages.freedesktop.org/maintainer-tools/commit-access.html#drm-misc
From: Karol Wachowski
Whenever KMD maps region larger than 64kB that is both aligned and
contiguous, set contiguous bit (52) in MMU PTE descriptor for each page
in that region.
This allows to treat 16 contiguous pages as one and reduce
number of MMU page walks required what results in lower
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