On 21/06/23 13:17, Nicolas Ferre wrote:
> On 16/06/2023 at 08:44, Manikandan M - I67131 wrote:
>> On 14/06/23 20:10, Nicolas Ferre wrote:
>>> On 13/06/2023 at 20:21, Conor Dooley wrote:
On Tue, Jun 13, 2023 at 08:17:13PM +0200, Krzysztof Kozlowski wrote:
> On 13/06/2023 09:04, Manikandan
On 2023-06-23 15:12:06, Abhinav Kumar wrote:
>
>
> On 6/23/2023 1:28 PM, Marijn Suijten wrote:
> > On 2023-06-23 14:37:12, Dmitry Baryshkov wrote:
> >
> >>> In fact I asked to make it 0xf00 + 0x10 or 0xf80 + 0x10 to also cover
> >>> the CTL registers, but that change didn't make it through.
:
https://lore.kernel.org/r/20230620045919.492128-1-suhui%40nfschina.com
patch subject: [PATCH] drm/amd/amdgpu: Properly tune the size of struct
config: m68k-randconfig-r093-20230625
(https://download.01.org/0day-ci/archive/20230626/202306260550.sinebmd3-...@intel.com/config)
compiler: m68k-linux
On 2023-06-24 03:49:25, Konrad Dybcio wrote:
> On 24.06.2023 02:41, Marijn Suijten wrote:
> > SM6125 features only a single PHY (despite a secondary PHY PLL source
> > being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream
> > sources for this "trinket" SoC do not define the
On 2023-06-24 03:47:27, Konrad Dybcio wrote:
> On 24.06.2023 02:41, Marijn Suijten wrote:
> > Add definitions for the display hardware used on the Qualcomm SM6125
> > platform.
> >
> > Signed-off-by: Marijn Suijten
> > ---
> [...]
>
> > +static const struct dpu_perf_cfg sm6125_perf_data = {
> >
On 2023-06-24 11:12:52, Krzysztof Kozlowski wrote:
> On 24/06/2023 02:41, Marijn Suijten wrote:
> > SM6125 is identical to SM6375 except that while downstream also defines
> > a throttle clock, its presence results in timeouts whereas SM6375
> > requires it to not observe any timeouts.
>
> Then
On 2023-06-24 11:08:54, Krzysztof Kozlowski wrote:
> On 24/06/2023 03:45, Konrad Dybcio wrote:
> > On 24.06.2023 02:41, Marijn Suijten wrote:
> >> The "gcc_disp_gpll0_div_clk_src" clock is consumed by the driver, will
> >> be passed from DT, and should be required by the bindings.
> >>
> >> Fixes:
On 2023-06-24 03:45:02, Konrad Dybcio wrote:
> On 24.06.2023 02:41, Marijn Suijten wrote:
> > The "gcc_disp_gpll0_div_clk_src" clock is consumed by the driver, will
> > be passed from DT, and should be required by the bindings.
> >
> > Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125
On 2023-06-24 11:08:30, Krzysztof Kozlowski wrote:
> On 24/06/2023 02:41, Marijn Suijten wrote:
> > The downsteam driver for dispcc only ever gets and puts this clock
> > without ever using it in the clocktree; this unnecessary workaround was
> > never ported to mainline, hence the driver doesn't
On 2023-06-24 04:06:04, Konrad Dybcio wrote:
> > + sde_dsi_sleep: sde-dsi-sleep-state {
> > + pins = "gpio90";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> s/sde/mdss as per Dmitry's recent request
Makes sense,
On 2023-06-24 04:05:07, Konrad Dybcio wrote:
> On 24.06.2023 02:41, Marijn Suijten wrote:
> > Add the DT nodes that describe the MDSS hardware on SM6125, containing
> > one MDP (display controller) together with a single DSI and DSI PHY. No
> > DisplayPort support is added for now.
> >
> >
On 2023-06-24 03:42:46, Konrad Dybcio wrote:
> On 24.06.2023 02:40, Marijn Suijten wrote:
> > Bring up the SM6125 DPU now that all preliminary series (such as INTF
> > TE) have been merged (for me to test the hardware properly)
> We should not repeat the same mistake in the future.. Finding a
>
On 2023-06-24 03:43:21, Konrad Dybcio wrote:
> On 24.06.2023 02:40, Marijn Suijten wrote:
> > This node has always resided in the wrong spot, making it somewhat
> > harder to contribute new node entries while maintaining proper sorting
> > around it. Move the node up to sit after hsusb_phy1 where
On Sat, Jun 24, 2023 at 10:17:53AM -0700, Lucas De Marchi wrote:
> Right now context workarounds don't do a rmw and instead only write to
> the register. Since 2 separate programmings to the same register are
> coalesced into a single write, this is not problematic for
> GEN12_FF_MODE2 since both
Hi Jim,
On 6/23/23 19:23, Jim Shargo wrote:
This change adds the basic scaffolding for ConfigFS, including setting
up the default directories. It does not allow for the registration of
configfs-backed devices, which is complex and provided in a follow-up
commit.
This CL includes docs about
Hi Jim,
On 6/23/23 19:23, Jim Shargo wrote:
In many testing circumstances, we will want to just create a new device
and test against that. If we create a default device, it can be annoying
to have to manually select the new device instead of choosing the only
one that exists.
The param,
Hi Jim,
On 6/23/23 19:23, Jim Shargo wrote:
This change supports multiple CRTCs, encoders, connectors instead of one
of each per device.
Since ConfigFS-based devices will support multiple crtcs, it's useful to
move all of the writeback/composition data from being per-"output" to
being
Hi Jim,
Thanks for working on this great feature for the VKMS!
On 6/23/23 19:23, Jim Shargo wrote:
This is a small refactor to make ConfigFS support easier. Once we
support ConfigFS, there can be multiple devices instantiated by the
driver, and so moving everything into managed memory makes
On Sun, Jun 25, 2023 at 10:58:17AM +0200, Geert Uytterhoeven wrote:
> On Fri, Jun 23, 2023 at 8:50 PM Laurent Pinchart wrote:
> > On Fri, Jun 23, 2023 at 07:55:22PM +0200, Geert Uytterhoeven wrote:
> > > On Fri, Jun 23, 2023 at 6:50 PM Laurent Pinchart wrote:
> > > > On Thu, Jun 22, 2023 at
Hi Dmitry,
On Sun, Jun 25, 2023 at 2:41 PM Dmitry Osipenko
wrote:
> On 6/25/23 11:47, Geert Uytterhoeven wrote:
> > On Sun, Apr 16, 2023 at 1:55 PM Dmitry Osipenko
> > wrote:
> >> Add sync object DRM UAPI support to VirtIO-GPU driver. Sync objects
> >> support is needed by native context
Right now clocking value selection code is prioritising RGB, YUV444 modes
over YUV420 for HDMI2 sinks. However, because of the bus format selection
procedure in dw-hdmi, for HDMI2 sinks YUV420 is the format that will always
be picked during the drm bridge chain check stage.
Later on dw_hdmi_setup
The hdmi_datamap enum is no longer in use. Also reindent enable_audio's
call params.
Signed-off-by: Adrián Larumbe
Acked-by: Neil Armstrong
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 22 --
1 file changed, 4 insertions(+), 18 deletions(-)
diff --git
The current output bus format selection logic is enforcing YUV420 even
when the drm mode allows for other bus formats as well.
Fix it by adding check for 420-only drm modes.
Signed-off-by: Adrián Larumbe
Acked-by: Neil Armstrong
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 ---
1 file
This is a belated follow-up on
https://lore.kernel.org/dri-devel/20220515204412.2733803-1-adrian.laru...@collabora.com
Commit e67f6037ae1be34b2b68 ("drm/meson: split out encoder from meson_dw_hdmi")
broke 4K display modes for me, and I discovered it was because the right
pixel clock wasn't being
On 6/25/23 11:47, Geert Uytterhoeven wrote:
> Hi Dmitry,
>
> On Sun, Apr 16, 2023 at 1:55 PM Dmitry Osipenko
> wrote:
>> Add sync object DRM UAPI support to VirtIO-GPU driver. Sync objects
>> support is needed by native context VirtIO-GPU Mesa drivers, it also will
>> be used by Venus and Virgl
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 24 ---
drivers/gpu/drm/msm/hdmi/hdmi.h| 6 +
Change the MSM HDMI driver to use generic PHY subsystem. Moving PHY
drivers allows better code sharing with the rest of the PHY system.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 6 ---
drivers/gpu/drm/msm/hdmi/hdmi.c| 58 +++--
In consequent modeset calls, the atomic_pre_enable() will be called
several times without calling atomic_post_disable() inbetween. Thus
iframes will not be updated for the next mode. Fix this by setting the
iframe outside of the !power_on check.
Signed-off-by: Dmitry Baryshkov
---
In preparation to converting MSM HDMI driver to use PHY framework, which
requires phy_power_on() calls to be paired with phy_power_off(), add a
conditional call to msm_hdmi_phy_powerdown() before the call to
msm_hdmi_phy_powerup().
Signed-off-by: Dmitry Baryshkov
---
Add support for HDMI PHY on Qualcomm MSM8974 / APQ8074 platforms.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig| 2 +-
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c | 327
According to the vendor kernel [1] , the alt_iface clock should be
enabled together with the rest of HPD clocks, to make HPD to work
properly.
[1]
https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/e07a5487e521e57f76083c0a6e2f995414ac6d03
Signed-off-by: Dmitry Baryshkov
---
Add support for HDMI PHY on Qualcomm MSM8x60 / APQ8060 platforms.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-hdmi-45nm.c | 184
drivers/phy/qualcomm/phy-qcom-hdmi-preqmp.c | 32 ++--
In preparation of reworking the HDMI mode setting, switch pre_enable and
post_disable callbacks to their atomic variants.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git
Drop source files used by old HDMI PHY and HDMI PLL drivers.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 217 ---
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 51 --
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 765 ---
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 62ce1455f974..fbcf4dd91cd9 100644
---
Import register definitions from 28nm DSI and HDMI PHYs, adding more UNI
PHY registers.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-uniphy.h | 33 ++
1 file changed, 33 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.h
The MSM HDMI PHYs have been using the ad-hoc approach / API instead of
using the generic API framework. Move all the PHYs to
drivers/phy/qualcomm and rework them to use generic PHY framework. This
way all the QMP-related code is kept close. Also in future this will
allow us to use a common set of
Add the driver for pre-QMP Qualcomm HDMI PHYs. Currently it suppports
Qualcomm MSM8960 / APQ8064 platforms, other platforms will come later.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig| 14 +
drivers/phy/qualcomm/Makefile | 6 +
The "uni" PLL is shared between several PHYS: APQ8064's SATA,
MSM8974/APQ8084 HDMI, MSM8916 DSI, MSM8974/APQ8084 DSI.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c | 23 +-
drivers/phy/qualcomm/phy-qcom-uniphy.h | 32
2
Port Qualcomm QMP HDMI PHY to the generic PHY framework. Split the
generic part and the msm8996 part. When adding support for msm8992/4 and
msm8998 (which also employ QMP for HDMI PHY), one will have to provide
the PLL programming part only.
Signed-off-by: Dmitry Baryshkov
---
From: Sandor Yu
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor
://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/20230621100435.54425-1-thomas.hellstrom%40linux.intel.com
patch subject: [PATCH v2] Documentation/gpu: Add a VM_BIND async draft document
reproduce:
(https://download.01.org/0day-ci/archive/20230625
On Wed, Jun 21, 2023 at 12:31:40AM +0200, Fabio M. De Francesco wrote:
> On martedì 20 giugno 2023 20:01:48 CEST Sumitra Sharma wrote:
> > Remove unnecessary calls to kmap{,_atomic}() when acquiring
> > pages using GFP_DMA32.
> >
> > The GFP_DMA32 uses the DMA32 zone to satisfy the allocation
> >
Please open an issue here by filling the "User verification" template:
https://gitlab.freedesktop.org/freedesktop/freedesktop/-/issues/new
The parameter 'caching' has already been assigned to
'ttm->caching', so 'ttm_cached' is redundant.
Fixes: 1b4ea4c5980f ("drm/ttm: set the tt caching state at creation time")
Signed-off-by: Feng Jiang
---
drivers/gpu/drm/ttm/ttm_tt.c | 1 -
1 file changed, 1 deletion(-)
diff --git
Hi!
I want to contribute to the modetest tool a few patches, which I had
developed during my work.
https://gitlab.freedesktop.org/mesa/mesa/-/issues/9197#note_1958102
Best regards,
Vostokov Nikita
Hi Laurent,
On Fri, Jun 23, 2023 at 8:50 PM Laurent Pinchart
wrote:
> On Fri, Jun 23, 2023 at 07:55:22PM +0200, Geert Uytterhoeven wrote:
> > On Fri, Jun 23, 2023 at 6:50 PM Laurent Pinchart wrote:
> > > On Thu, Jun 22, 2023 at 11:21:36AM +0200, Geert Uytterhoeven wrote:
> > > > Unify primary
Hi Sui,
On Sat, Jun 24, 2023 at 11:33 AM Sui Jingfeng wrote:
> I'm fine with this patch but I I don't see the benefit.
>
> This reply is more about my personal question.
>
> On 2023/6/22 17:21, Geert Uytterhoeven wrote:
> > Replace the call to the legacy drm_handle_vblank() function with a call
Hi Dmitry,
On Sun, Apr 16, 2023 at 1:55 PM Dmitry Osipenko
wrote:
> Add sync object DRM UAPI support to VirtIO-GPU driver. Sync objects
> support is needed by native context VirtIO-GPU Mesa drivers, it also will
> be used by Venus and Virgl contexts.
>
> Reviewed-by; Emil Velikov
>
Variable entry is not effectively used, so delete it.
drivers/gpu/drm/nouveau/nouveau_connector.c:1298:7: warning: variable 'entry'
set but not used.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5596
Signed-off-by: Jiapeng Chong
---
On 24/06/2023 15:48, Dmitry Baryshkov wrote:
> On 24/06/2023 03:41, Marijn Suijten wrote:
>> Document availability of the 14nm DSI PHY on SM6125.
>>
>> Signed-off-by: Marijn Suijten
>> ---
>> Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
>> 1 file changed, 1
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