> From: Tvrtko Ursulin
>
> According to the comment in i915_gem_object_can_bypass_llc the
> purpose of the function is to return false if the platform/object
> has a caching mode where GPU can bypass the LLC.
>
> So far the only platforms which allegedly can do this are Jasperlake
> and
[snip]
> @@ -326,10 +330,10 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev,
> void *data,
> goto out;
> }
>
> - if (i915_gem_object_has_cache_level(obj, I915_CACHE_LLC) ||
> - i915_gem_object_has_cache_level(obj, I915_CACHE_L3_LLC))
> + if
On Wed, 12 Jul 2023 15:11:37 +0300, Dmitry Baryshkov wrote:
> Per agreement with Konrad, picked up this patch series.
>
> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
> another path that needs to be handled to ensure MDSS functions properly,
> namely the "reg bus", a.k.a
Hi Sam,
On 10-Jul-23 20:38, Sam Ravnborg wrote:
> Hi Aradhya,
>
> On Tue, Jun 06, 2023 at 01:51:39PM +0530, Aradhya Bhatia wrote:
>> With new connector model, sii902x will not create the connector, when
>> DRM_BRIDGE_ATTACH_NO_CONNECTOR is set and SoC driver will rely on format
>> negotiation to
Hey Linus,
There were a bunch of fixes lined up for 2 weeks, so we have quite a
few scattered fixes, mostly amdgpu and i915, but ttm has a bunch and
nouveau makes an appearance.
So a bit busier than usual for rc2, but nothing seems out of the ordinary.
Dave.
drm-fixes-2023-07-14-1:
drm fixes
> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, July 13, 2023 4:04 PM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 08/19] drm/i915/dp: Remove extra logs for
> printing DSC info
>
> DSC
> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, July 13, 2023 4:03 PM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check
> with 420 format inside the
https://bugzilla.kernel.org/show_bug.cgi?id=217664
Bagas Sanjaya (bagasdo...@gmail.com) changed:
What|Removed |Added
CC|
Add missing spaces to clear checkpatch errors.
ERROR: space required after that ',' (ctx:VxV)
Signed-off-by: Ran Sun
---
drivers/gpu/drm/nouveau/include/nvhw/drf.h | 80 +++---
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git
As we have dropped the variadic parts of SSPP sub-blocks declarations,
deduplicate them now, reducing memory cruft.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +++---
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 16 +++---
As the subblock info is now mostly gone, inline and drop the macro
DPU_HW_SUBBLK_INFO.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 40 ++-
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git
In preparation to deduplicating SSPP subblocks, drop the (unused)
`smart_dma_priority' field from struct dpu_sspp_sub_blks. If it is
needed later (e.g. for SmartDMA v1), it should be added to the SSPP
declarations themselves.
Signed-off-by: Dmitry Baryshkov
---
The field `id' is not used for subblocks. The handling code usually
knows, which sub-block it is now looking at. Drop the field completely.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 16 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |
The handling code also usually knows, which sub-block it is now looking
at. Drop unused 'id' field and arguments and merge some of sub-block
declarations.
Changes since v1:
- Dropped the patch dropping 'name' field (Abhinav).
- Deduplicate equivalent SBLK definitions.
- Dropped the dpu_csc_blk
The msm_gem_get_vaddr() returns an ERR_PTR() on failure, we should
use IS_ERR() to check the return value.
Fixes: 6a8bd08d0465 ("drm/msm: add sudo flag to submit ioctl")
Signed-off-by: Gaosheng Cui
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Reviewed-by: Akhil P Oommen
---
The mipi_dsi_device_register_full() returns an ERR_PTR() on failure,
we should use IS_ERR() to check the return value.
Fixes: 623a3531e9cf ("drm/panel: Add driver for Novatek NT35950 DSI DriverIC
panels")
Signed-off-by: Gaosheng Cui
---
drivers/gpu/drm/panel/panel-novatek-nt35950.c | 2 +-
1
The komeda_pipeline_get_state() returns an ERR_PTR() on failure, we should
use IS_ERR() to check the return value.
Fixes: 502932a03fce ("drm/komeda: Add the initial scaler support for CORE")
Signed-off-by: Gaosheng Cui
Reviewed-by: Liviu Dudau
---
v3:
- Update the second patch:
1. change IS_ERR to IS_ERR_OR_NULL
2. add Dmitry's R-b in this revision:
link: https://patchwork.freedesktop.org/patch/511035/?series=110745=1
Thanks!
v2:
- I'm sorry I missed some emails, these patches were submitted last year,
now let me resend it with
Add compatible value for Inanbo t28cp45tn89 and make reset GPIO non
mandatory, since it might not be connected to the CPU.
Reviewed-by: Michael Riesch
Acked-by: Rob Herring
Signed-off-by: Sebastian Reichel
---
.../devicetree/bindings/display/panel/sitronix,st7789v.yaml | 5 +++--
1 file
From: Miquel Raynal
The ST7789V LCD controller supports regular SPI wiring, as well as no Rx
data line at all. The operating system needs to know whether it can read
registers from the device or not. Let's detail this specific design
possibility by bounding the spi-rx-bus-width property.
Avoid hard-coding the default_mode and supply it from match data. One
additional layer of abstraction has been introduced, which will be
needed for specifying other panel information (e.g. bus flags) in the
next steps.
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
From: Miquel Raynal
A very basic debugging rule when a device is connected for the first
time is to access a read-only register which contains known data in
order to ensure the communication protocol is properly working. This
driver lacked any read helper which is often a critical piece for
Add polarity information via mode and bus flags, so that they are no
longer hardcoded and forward the information to the DRM stack. This is
required for adding panels with different settings.
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
While the default panel uses invert mode, some panels
require non-invert mode instead.
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git
Add support for describing the media bus format in the
panel configuration and expose that to userspace. Since
both supported formats (RGB565 and RGB666) are using 6
bits per color also hardcode that information.
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
SPI device drivers should also have a SPI ID table.
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7789v.c
Improve error handling in the probe routine, so that probe
defer errors are captured in /sys/kernel/debug/devices_deferred
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
.../gpu/drm/panel/panel-sitronix-st7789v.c| 23 ++-
1 file changed, 12 insertions(+),
The reset pin might not be software controllable from the SoC,
so make it optional.
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Miquel Raynal
The ST7789V LCD controller is also embedded in the ET028013DMA
panel. Add a compatible string to describe this other panel.
Signed-off-by: Miquel Raynal
Acked-by: Krzysztof Kozlowski
Acked-by: Maxime Ripard
Reviewed-by: Sebastian Reichel
Signed-off-by: Sebastian Reichel
UNI-T UTi260b has a Inanbo T28CP45TN89 v17 panel. I could not find
proper documentation for the panel apart from a technical drawing, but
according to the vendor U-Boot it is based on a Sitronix st7789v chip.
I generated the init sequence by modifying the default one until proper
graphics output
st7789v_spi_write initializes a message with just
a single transfer, spi_sync_transfer can be used
for that.
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git
ST7789V_COLMOD_RGB_FMT_18BITS and ST7789V_COLMOD_CTRL_FMT_18BITS
are unused in favour of MIPI_DCS_PIXEL_FMT_18BIT, remove them.
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
Move the panel size information to the mode struct, so
that different panel sizes can be specified depending
on the panel type.
Reviewed-by: Michael Riesch
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 6 --
1 file changed, 4 insertions(+), 2
From: Miquel Raynal
This panel from Emerging Display Technologies Corporation features an
ST7789V2 LCD controller panel inside which is almost identical to what
the Sitronix panel driver supports.
In practice, the module physical size is specific, and experiments show
that the display will
From: Miquel Raynal
The Sitronix datasheet explains BIT(1) of the RGBCTRL register as the
DOTCLK/PCLK edge used to sample the data lines:
“0” The data is input on the positive edge of DOTCLK
“1” The data is input on the negative edge of DOTCLK
IOW, this bit implies a falling edge and
From: Miquel Raynal
The Sitronix controller expects 9-bit words, provide this as default at
probe time rather than specifying this in each and every access.
Signed-off-by: Miquel Raynal
Reviewed-by: Sam Ravnborg
Acked-by: Maxime Ripard
Reviewed-by: Sebastian Reichel
Tested-by: Sebastian
Shenzhen INANBO Electronic Technology Co., Ltd. manufacturers TFT/OLED
LCD panels.
Reviewed-by: Michael Riesch
Acked-by: Krzysztof Kozlowski
Signed-off-by: Sebastian Reichel
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hi,
This adds panel support for Inanbo T28CP45TN89, which I found inside of a
handheld thermal camera. The panel is based on the st7789v controller. All
information is based on reverse engineering. I also appended the series
from Miquel Raynal adding EDT ET028013DMA panel support, so that I could
On 14/07/2023 03:21, Jessica Zhang wrote:
DSI 6G v2.5.x+ and DPU 7.x+ support a data-bus widen mode that allows DSI
to send 48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as recommended by the hardware programming
DSI 6G v2.5.x+ and DPU 7.x+ support a data-bus widen mode that allows DSI
to send 48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as recommended by the hardware programming guide.
Only enable this for command mode as
On Fri, 14 Jul 2023 at 01:06, Rob Clark wrote:
>
> On Thu, Jul 13, 2023 at 2:39 PM Akhil P Oommen
> wrote:
> >
> > On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
> > >
> > > On 07/07/2023 00:10, Rob Clark wrote:
> > > > From: Rob Clark
> > > >
> > > > Since the revision
On Wed, Jul 12, 2023 at 10:29 AM Mauro Carvalho Chehab
wrote:
>
> As an example for the new documentation tool, add a documentation
> for drm_buddy_test.
>
> I opted to place this on a completely different directory, in order
> to make easier to test the feature with:
>
> $ make
On Thu, Jul 13, 2023 at 1:06 PM Akhil P Oommen wrote:
>
> On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > It is better to explicitly list it. With the move to opaque chip-id's
> > for future devices, we should avoid trying to infer things like
> >
From: Florian Fainelli
74165 is a 16nm process SoC with a 10/100 integrated Ethernet PHY,
utilize the recently defined 16nm EPHY macro to configure that PHY.
Reviewed-by: Simon Horman
Reviewed-by: Andrew Lunn
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
Add maintainers entry for ASP 2.0 Ethernet driver.
Reviewed-by: Simon Horman
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
v3
- Change from gmail to broadcom emails
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
Add mdio compat string for ASP 2.0 ethernet driver.
Reviewed-by: Simon Horman
Reviewed-by: Andrew Lunn
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
drivers/net/mdio/mdio-bcm-unimac.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/mdio/mdio-bcm-unimac.c
Add support for eth_mac_stats, rmon_stats, and eth_ctrl_stats.
Signed-off-by: Justin Chen
---
.../net/ethernet/broadcom/asp2/bcmasp_ethtool.c| 77 ++
.../net/ethernet/broadcom/asp2/bcmasp_intf_defs.h | 63 +-
2 files changed, 139 insertions(+), 1
Add support for ethernet driver specific stats.
Signed-off-by: Justin Chen
---
v9
- Removed tx_realloc_offload, this stat is no longer relevant with
skb_cow_head().
- Added tx_timeout_cnt
v8
- Address maybe uninit variable warning
Add support for wake on network filters. The max match is 256 bytes.
Signed-off-by: Justin Chen
---
drivers/net/ethernet/broadcom/asp2/bcmasp.c| 595 +
drivers/net/ethernet/broadcom/asp2/bcmasp.h| 40 ++
.../net/ethernet/broadcom/asp2/bcmasp_ethtool.c|
Add support for eee mode.
Signed-off-by: Justin Chen
---
drivers/net/ethernet/broadcom/asp2/bcmasp.h| 4 ++
.../net/ethernet/broadcom/asp2/bcmasp_ethtool.c| 61 ++
drivers/net/ethernet/broadcom/asp2/bcmasp_intf.c | 6 +++
3 files changed, 71 insertions(+)
Add support for the Broadcom ASP 2.0 Ethernet controller which is first
introduced with 72165. This controller features two distinct Ethernet
ports that can be independently operated.
Reviewed-by: Simon Horman
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
v9
- Reworked
Add support for Wake-On-Lan magic packet and magic packet with password.
Signed-off-by: Justin Chen
---
v9
- Fixed some spacing issues
drivers/net/ethernet/broadcom/asp2/bcmasp.c| 144 +
drivers/net/ethernet/broadcom/asp2/bcmasp.h| 18 +++
From: Florian Fainelli
Add a binding document for the Broadcom ASP 2.0 Ethernet
controller.
Reviewed-by: Conor Dooley
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
v7
- Added "unevaluatedProperties: False"
v6
- Moved compatible to the top
- Changed
The ASP 2.0 Ethernet controller uses a brcm unimac.
Reviewed-by: Simon Horman
Acked-by: Conor Dooley
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
Add support for the Broadcom ASP 2.0 Ethernet controller which is first
introduced with 72165.
Florian Fainelli (2):
dt-bindings: net: Brcm ASP 2.0 Ethernet controller
net: phy: bcm7xxx: Add EPHY entry for 74165
Justin Chen (9):
dt-bindings: net: brcm,unimac-mdio: Add asp-v2.0
net:
On Fri, Jul 07, 2023 at 02:40:47AM +0200, Konrad Dybcio wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > There are cases where there are differences due to SoC integration.
> > Such as cache-coherency support, and (in the next patch) e-fuse to
> > speedbin mappings.
>
On Thu, Jul 13, 2023 at 2:39 PM Akhil P Oommen wrote:
>
> On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
> >
> > On 07/07/2023 00:10, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > Since the revision becomes an opaque identifier with future GPUs, move
> > > away from
On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > Since the revision becomes an opaque identifier with future GPUs, move
> > away from treating different ranges of bits as having a given meaning.
> > This
Log the IB addresses used by the hung job along with the stuck ring
name. Note that due to nested IBs, the one that caused the reset itself
may be in not listed address.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++
Even if there's nothing currently parsing amdgpu's coredump files, if
we eventually have such tools they will be glad to find a version field
to properly read the file.
Create a version number to be displayed on top of coredump file, to be
incremented when the file format or content get changed.
If a kernel thread caused the reset, the information available to be
logged will be limited, so return early in the dump function.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
During a GPU reset, a normal memory reclaim could block to reclaim
memory. Giving that coredump is a best effort mechanism, it shouldn't
disturb the reset path. Change its memory allocation flag to a
nonblocking one.
Signed-off-by: André Almeida
---
v2: New patch
Instead of storing coredump information inside amdgpu_device struct,
move if to a proper separated struct and allocate it dynamically. This
will make it easier to further expand the logged information.
Signed-off-by: André Almeida
---
v2: Replace GFP_KERNEL with GPF_NOWAIT
Hi,
The goal of this patchset is to improve debugging device resets on amdgpu.
The first patch creates a new module parameter to disable soft recoveries,
ensuring every recovery go through the full device reset, making easier to
generate resets from userspace tools like [0] and [1]. This is
Create a module parameter to disable soft recoveries on amdgpu, making
every recovery go through the device reset path. This option makes
easier to force device resets for testing and debugging purposes.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
On Wed, Jul 12, 2023 at 10:29 AM Mauro Carvalho Chehab
wrote:
> As an example for the new documentation tool, add a documentation
> for drm_buddy_test.
>
> I opted to place this on a completely different directory, in order
> to make easier to test the feature with:
>
> $ make
On Thu, Jul 13, 2023 at 1:03 PM Dmitry Baryshkov
wrote:
>
> On 13/07/2023 01:25, Rob Clark wrote:
> > From: Rob Clark
> >
> > In an error path where the submit is free'd without the job being run,
> > the hw_fence pointer is simply a kzalloc'd block of memory. In this
> > case we should just
On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > There are cases where there are differences due to SoC integration.
> > Such as cache-coherency support, and (in the next patch) e-fuse to
> > speedbin
On Wed, May 17, 2023 at 4:08 AM Alexandru Ardelean wrote:
>
> From: Bogdan Togorean
>
> For ADV7533 and ADV7535 low refresh rate is selected using
> bits [3:2] of 0x4a main register.
> So depending on ADV model write 0xfb or 0x4a register.
>
> Signed-off-by: Bogdan Togorean
> Signed-off-by:
On Tue, May 16, 2023 at 7:44 PM Alexandru Ardelean wrote:
>
> From: Bogdan Togorean
>
> For ADV7533 and ADV7535 low refresh rate is selected using
> bits [3:2] of 0x4a main register.
> So depending on ADV model write 0xfb or 0x4a register.
>
Ping on this patch :)
> Signed-off-by: Bogdan
On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
>
> From: Rob Clark
>
> It is better to explicitly list it. With the move to opaque chip-id's
> for future devices, we should avoid trying to infer things like
> generation from the numerical value.
>
> Signed-off-by: Rob Clark
> ---
On 13/07/2023 01:25, Rob Clark wrote:
From: Rob Clark
In an error path where the submit is free'd without the job being run,
the hw_fence pointer is simply a kzalloc'd block of memory. In this
case we should just kfree() it, rather than trying to decrement it's
reference count. Fortunately
On 04/07/2023 19:36, Rob Clark wrote:
From: Rob Clark
These fields are deprecated. But any userspace new enough to support
a690 also knows how to identify the GPU based on chip-id.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 --
On 05/07/2023 17:42, Rob Clark wrote:
On Tue, Jul 4, 2023 at 10:20 AM Dmitry Baryshkov
wrote:
On Tue, 4 Jul 2023 at 19:36, Rob Clark wrote:
From: Rob Clark
Recently, a WARN_ON() was introduced to ensure that revn is filled before
adreno_is_aXYZ is called. This however doesn't work very
On 11/07/2023 20:54, Rob Clark wrote:
From: Rob Clark
The incorrect size was causing "CP | AHB bus error" when snapshotting
the GPU state on a6xx gen4 (a660 family).
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/26
Signed-off-by: Rob Clark
What about:
Fixes: 1707add81551
From: Ville Syrjälä
Currently dma_resv_get_fences() will leak the previously
allocated array if the fence iteration got restarted and
the krealloc_array() fails.
Free the old array by hand, and make sure we still clear
the returned *fences so the caller won't end up accessing
freed memory. Some
On Fri, Jul 07, 2023 at 01:22:56AM +0200, Konrad Dybcio wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > Even in the ocmem case, the allocated ocmem buffer size should match the
> > requested size.
> >
> > Signed-off-by: Rob Clark
> > ---
> [...]
>
> > +
> > +
On Thu, 13 Jul 2023 at 22:08, Akhil P Oommen wrote:
>
> On Thu, Jul 13, 2023 at 10:05:55AM +0800, Gaosheng Cui wrote:
> >
> > The msm_gem_get_vaddr() returns an ERR_PTR() on failure, we should
> > use IS_ERR() to check the return value.
> >
> > Fixes: 6a8bd08d0465 ("drm/msm: add sudo flag to
On Fri, Jun 30, 2023 at 09:20:43AM -0700, Rob Clark wrote:
>
> From: Rob Clark
>
> The range is actually len+1.
>
> Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>
On Thu, Jul 13, 2023 at 02:13:16PM -0500, Andrew Davis wrote:
> This new export type exposes to userspace the SRAM area as a DMA-BUF Heap,
> this allows for allocations of DMA-BUFs that can be consumed by various
> DMA-BUF supporting devices.
What devices exactly?
And what userspace
On Thu, Jul 13, 2023 at 02:13:16PM -0500, Andrew Davis wrote:
> +int sram_add_dma_heap(struct sram_dev *sram,
> + struct sram_reserve *block,
> + phys_addr_t start,
> + struct sram_partition *part)
> +{
> + struct sram_dma_heap
On 7/13/23 09:36, Jim Cromie wrote:
> Add some basic info on classmap usage and api
>
> Signed-off-by: Jim Cromie
> ---
> .../admin-guide/dynamic-debug-howto.rst | 64 ++-
> 1 file changed, 63 insertions(+), 1 deletion(-)
>
> diff --git
This new export type exposes to userspace the SRAM area as a DMA-BUF Heap,
this allows for allocations of DMA-BUFs that can be consumed by various
DMA-BUF supporting devices.
Signed-off-by: Andrew Davis
---
Changes from v2:
- Make sram_dma_heap_allocate static (kernel test robot)
- Rebase on
On Thu, Jul 13, 2023 at 10:05:55AM +0800, Gaosheng Cui wrote:
>
> The msm_gem_get_vaddr() returns an ERR_PTR() on failure, we should
> use IS_ERR() to check the return value.
>
> Fixes: 6a8bd08d0465 ("drm/msm: add sudo flag to submit ioctl")
> Signed-off-by: Gaosheng Cui
> Reviewed-by: Abhinav
Hi Jim,
On 7/13/23 09:36, Jim Cromie wrote:
> Signed-off-by: Jim Cromie
> ---
> lib/Kconfig.debug | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
> index d4fbbcc395d2..82d11ac63758 100644
> --- a/lib/Kconfig.debug
> +++
On Wed, Jul 12, 2023 at 02:27:45PM +0200, Peter Zijlstra wrote:
> On Wed, Jul 12, 2023 at 11:04:16AM +0200, Geert Uytterhoeven wrote:
> > Hoi Peter,
> >
> > On Wed, Jul 12, 2023 at 10:05 AM Peter Zijlstra
> > wrote:
> > > On Tue, Jul 11, 2023 at 11:39:17AM -1000, Tejun Heo wrote:
> > > > I
On Tue, Jul 11, 2023 at 10:54:07AM -0700, Rob Clark wrote:
>
> From: Rob Clark
>
> The incorrect size was causing "CP | AHB bus error" when snapshotting
> the GPU state on a6xx gen4 (a660 family).
>
> Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/26
> Signed-off-by: Rob Clark
> ---
On Thu, Jul 13, 2023 at 11:39 PM Abhinav Kumar
wrote:
>
>
>
> On 7/12/2023 10:41 AM, Marek Vasut wrote:
> > On 7/9/23 03:03, Abhinav Kumar wrote:
> >>
> >>
> >> On 7/7/2023 1:47 AM, Neil Armstrong wrote:
> >>> On 07/07/2023 09:18, Neil Armstrong wrote:
> Hi,
>
> On 06/07/2023
On 7/13/2023 11:28 AM, Marek Vasut wrote:
On 7/13/23 20:09, Abhinav Kumar wrote:
On 7/12/2023 10:41 AM, Marek Vasut wrote:
On 7/9/23 03:03, Abhinav Kumar wrote:
On 7/7/2023 1:47 AM, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir
On 7/13/23 20:09, Abhinav Kumar wrote:
On 7/12/2023 10:41 AM, Marek Vasut wrote:
On 7/9/23 03:03, Abhinav Kumar wrote:
On 7/7/2023 1:47 AM, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir wrote:
On Wed, 5 Jul 2023 at 11:09, Dmitry
On 7/12/2023 10:41 AM, Marek Vasut wrote:
On 7/9/23 03:03, Abhinav Kumar wrote:
On 7/7/2023 1:47 AM, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir wrote:
On Wed, 5 Jul 2023 at 11:09, Dmitry Baryshkov
wrote:
[Adding freedreno@
Hi Jim
On Thu, Jul 13, 2023 at 10:36:23AM -0600, Jim Cromie wrote:
> We currently have 3 defns for __UNIQUE_ID(); gcc and clang are using
> __COUNTER__ for real uniqueness, 3rd just uses __LINE__, which should
> fail on this (and harder to avoid situations):
>
> DECLARE_FOO(); DECLARE_FOO();
>
On Thu, 13 Jul 2023 12:05:36 +0200
Christian Brauner wrote:
> Hey everyone,
>
> This simplifies the eventfd_signal() and eventfd_signal_mask() helpers
> by removing the count argument which is effectively unused.
We have a patch under review which does in fact make use of the
signaling value:
On Thu, Jul 13, 2023 at 05:39:36PM +0200, Uwe Kleine-König wrote:
> On Thu, Jul 13, 2023 at 10:41:45AM -0400, Sean Paul wrote:
> > On Thu, Jul 13, 2023 at 9:04 AM Uwe Kleine-König
> > > But even with the one-patch-per-rename approach I'd consider the
> > > renaming a net win, because ease of
Provide the driver indirection iterating over all DRM GPU VA spaces to
enable the common 'gpuvas' debugfs file for dumping DRM GPU VA spaces.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_debugfs.c | 39 +++
1 file changed, 39 insertions(+)
diff --git
The new VM_BIND UAPI uses the DRM GPU VA manager to manage the VA space.
Hence, we a need a way to manipulate the MMUs page tables without going
through the internal range allocator implemented by nvkm/vmm.
This patch adds a raw interface for nvkm/vmm to pass the resposibility
for managing the
This commit provides the implementation for the new uapi motivated by the
Vulkan API. It allows user mode drivers (UMDs) to:
1) Initialize a GPU virtual address (VA) space via the new
DRM_IOCTL_NOUVEAU_VM_INIT ioctl for UMDs to specify the portion of VA
space managed by the kernel and
The new VM_BIND UAPI implementation introduced in subsequent commits
will allow asynchronous jobs processing push buffers and emitting
fences.
If a fence context is killed, e.g. due to a channel fault, jobs which
are already queued for execution might still emit new fences. In such a
case a job
1 - 100 of 340 matches
Mail list logo
