: 92a09c47464d040866cf2b4cd052bc60555185fb
patch link:
https://lore.kernel.org/r/20250509031524.2604087-5-andrewjballance%40gmail.com
patch subject: [PATCH 04/11] rust: io: add PortIo
config: x86_64-randconfig-073-20250512
(https://download.01.org/0day-ci/archive/20250513/202505131314.oziwfdr4
There is a spelling mistake of 'restictions' in comments which
should be 'restrictions'.
This typo was not listed in scripts/spelling.txt, thus it was more
difficult to detect. Add it for convenience.
This typo is reported by GitHub Copilot code review. [1]
[1]. https://github.com/deepin-communi
User request for remote heap allocation is supported using ioctl
interface but support for unmap is missing. This could result in
memory leak issues. Add unmap user request support for remote heap.
Fixes: 532ad70c6d449 ("misc: fastrpc: Add mmap request assigning for static PD
pool")
Cc: sta...@ke
The initially allocated memory is not properly included in the pool,
leading to potential issues with memory management. Set the number
of pages to one to ensure that the initially allocated memory is
correctly added to the Audio PD memory pool.
Fixes: 0871561055e66 ("misc: fastrpc: Add support fo
Add missing bug fixes in memory areas. This patch series carries
following fixes:
- Add proper checks to fastrpc_buf_free to avoid potential issues.
- Add multiple fixes for remote heap which is used by Audio PD.
Ekansh Gupta (5):
misc: fastrpc: Add NULL check to fastrpc_buf_free to prevent cras
Remote heap allocations are not organized in a maintainable manner,
leading to potential issues with memory management. As the remote
heap allocations are maintained in fl mmaps list, the allocations
will go away if the audio daemon process is killed but there are
chances that audio PD might still
fastrpc_req_munmap_impl() is called to unmap any buffer. The buffer is
getting removed from the list after it is unmapped from DSP. This can
create potential race conditions if any other thread removes the entry
from list while unmap operation is ongoing. Remove the entry before
calling unmap opera
The fastrpc_buf_free function currently does not handle the case where
the input buffer pointer (buf) is NULL. This can lead to a null pointer
dereference, causing a crash or undefined behavior when the function
attempts to access members of the buf structure. Add a NULL check to
ensure safe handli
On Fri, May 9, 2025 at 8:45 AM Jani Nikula
wrote:
> On Fri, 09 May 2025, Maxime Ripard wrote:
> > On Thu, May 08, 2025 at 05:27:21PM +0300, Jani Nikula wrote:
> >> On Mon, 05 May 2025, Anusha Srivatsa wrote:
> >> > On Mon, May 5, 2025 at 2:54 AM Maxime Ripard
> wrote:
> >> >
> >> >> Hi Jani,
>
On 4/25/25 07:50, Leandro Ribeiro wrote:
On 3/26/25 20:47, Alex Hung wrote:
It is to be used to enable HDR by allowing userpace to create and pass
3D LUTs to kernel and hardware.
new drm_colorop_type: DRM_COLOROP_3D_LUT.
Signed-off-by: Alex Hung
---
v8:
- Fix typo in subject (Simon Ser
On 5/12/25 18:52, Melissa Wen wrote:
On 04/29, Alex Hung wrote:
This adds support for a 3D LUT.
The color pipeline now consists of the following colorops:
1. 1D curve colorop
2. Multiplier
3. 3x4 CTM
4. 1D curve colorop
5. 1D LUT
6. 3D LUT
7. 1D curve colorop
8. 1D LUT
Signed-off-by: Alex H
Thank you for the review.
I re-sent updated patch, please take a look.
Best regards,
Hyejeong
On Mon, May 12, 2025 at 03:16:33PM +0200, Christian König wrote:
> On 5/12/25 13:12, Hyejeong Choi wrote:
> > smp_store_mb() inserts memory barrier after storing operation.
> > It is different with what
smp_store_mb() inserts memory barrier after storing operation.
It is different with what the comment is originally aiming so Null
pointer dereference can be happened if memory update is reordered.
Signed-off-by: Hyejeong Choi
---
drivers/dma-buf/dma-resv.c | 5 +++--
1 file changed, 3 insertions
: 92a09c47464d040866cf2b4cd052bc60555185fb
patch link:
https://lore.kernel.org/r/20250509031524.2604087-2-andrewjballance%40gmail.com
patch subject: [PATCH 01/11] rust: helpers: io: use macro to generate io
accessor functions
config: x86_64-randconfig-073-20250512
(https://download.01.org/0day-ci
From: Wayne Lin
[ Upstream commit fcf6a49d79923a234844b8efe830a61f3f0584e4 ]
[Why]
When unplug one of monitors connected after mst hub, encounter null pointer
dereference.
It's due to dc_sink get released immediately in early_unregister() or
detect_ctx(). When
commit new state which directly
From: Chaoyi Chen
This series convert cdn-dp-rockchip.txt to yaml.
PATCH 1 try to improve coding style on the existing rk3399 cdn-dp
node.
PATCH 2 try to convert cdn-dp-rockchip.txt to yaml.
Changes in v3:
- Link to V2:
https://lore.kernel.org/all/20250509070247.868-1-ker...@airkyi.com/
- Add
From: Chaoyi Chen
Let's make the ports nodes of cdn_dp in the same style as the other
display interface, and match the style of ports's yaml.
Signed-off-by: Chaoyi Chen
---
(no changes since v1)
arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 10 +-
1 file changed, 9 insertions(+), 1
From: Chaoyi Chen
Convert cdn-dp-rockchip.txt to yaml.
Signed-off-by: Chaoyi Chen
---
Changes in v3:
- Add more description about phy/extcon
- Fix some coding style
Changes in v2:
- Rename binding file name to match compatible
- Add more description about grf/phy/extcon
- Fix coding style
Dear maintainer:
I have changed the patch as your suggestion.
v1->v2:make a new function for hdr info reset.
From: "feijuan.li"
Date: Fri, 18 Apr 2025 14:56:49 +
Subject: [PATCH v2] drm/edid: fixed the bug that hdr metadata was not reset
When DP connected to a device with HDR capability,
t
On 04/29, Alex Hung wrote:
> This adds support for a 3D LUT.
>
> The color pipeline now consists of the following colorops:
> 1. 1D curve colorop
> 2. Multiplier
> 3. 3x4 CTM
> 4. 1D curve colorop
> 5. 1D LUT
> 6. 3D LUT
> 7. 1D curve colorop
> 8. 1D LUT
>
> Signed-off-by: Alex Hung
> Reviewed-b
Hi Danila,
On Wed, Apr 23, 2025 at 12:31:24AM +0300, Danila Tikhonov wrote:
> Add the SM7150 CCI device string compatible.
>
> Signed-off-by: Danila Tikhonov
Acked-by: Andi Shyti
Thanks,
Andi
Hi,
with v6.9 and later there is no output on the BananaPI HDMI connector.
I have bisected the issue to the following commit:
358e76fd613a ("drm/sun4i: hdmi: Consolidate atomic_check and mode_valid")
With this patch, sun4i_hdmi_connector_clock_valid() is occasionally
called with clock=0, ca
On 06. 05. 25, 15:41, Thomas Gleixner wrote:
On Wed, Mar 19 2025 at 10:28, Jiri Slaby wrote:
Hi,
tl;dr if patches are agreed upon, I ask subsys maintainers to take the
respective ones via their trees (as they are split per subsys), so that
the IRQ tree can take only the rest. That would minimi
Hi all (and i hope you won't feel spammed).
I have a Raspberry Pi 4B i want to use with HDMI0, but i can't make it
work (tried lot of kernel versions), and i'd appreciate some guidance.
Overview of dmesg (6.15-rc6 with some trace/stack dump of mine):
[0.212555] simple-framebuffer 3e40f000.fra
On Fri, May 9 2025 at 03:01:13 PM +, Steven J Abner
wrote:
On Fri, May 9 2025 at 02:05:16 PM +, Alex Deucher
wrote:
bisect between 6.2.16 and 6.2.17 to identify the commit which broke
Are you asking for a 'diff' output of drm and amdgpu directories
between 6.2.16 (last of the 6.2 se
smp_store_mb() inserts memory barrier after storing operation.
It is different with what the comment is originally aiming so Null
pointer dereference can be happened if memory update is reordered.
Signed-off-by: Hyejeong Choi
---
drivers/dma-buf/dma-resv.c | 5 +++--
1 file changed, 3 insertions
* Alex Deucher (alexdeuc...@gmail.com) wrote:
> On Sun, May 11, 2025 at 8:13 AM Dr. David Alan Gilbert
> wrote:
> >
> > * Christophe JAILLET (christophe.jail...@wanadoo.fr) wrote:
> > > Le 18/04/2025 à 02:21, li...@treblig.org a écrit :
> > > > From: "Dr. David Alan Gilbert"
> > > >
> > > > radeo
On Mon, May 12, 2025 at 1:30 PM Song Liu wrote:
>
> On Mon, May 12, 2025 at 10:41 AM T.J. Mercier wrote:
> >
> > Use the same test buffers as the traditional iterator and a new BPF map
> > to verify the test buffers can be found with the open coded dmabuf
> > iterator.
> >
> > Signed-off-by: T.J.
On 5/9/25 9:21 AM, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Add gpu and gmu nodes for qcs8300 chipset.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 91
> +++
> 1 file changed, 91 insertions(+
To notify userspace about which app (if any) made the device get in a
wedge state, make use of drm_wedge_app_info parameter, filling it with
the app PID and name.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +--
drivers/gpu/drm/amd/amdgpu/amdg
When a device get wedged, it might be caused by a guilty application.
For userspace, knowing which app was the cause can be useful for some
situations, like for implementing a policy, logs or for giving a chance
for the compositor to let the user know what app caused the problem.
This is an optiona
This patchset implements a request made by Xaver Hugl about wedge events:
"I'd really like to have the PID of the client that triggered the GPU
reset, so that we can kill it if multiple resets are triggered in a
row (or switch to software rendering if it's KWin itself) and show a
user-friendly not
Add a section about "App information" for the wedge API.
Signed-off-by: André Almeida
---
v3:
- Change "app that caused ..." to "app involved ..."
- Clarify that devcoredump have more information about what happened
- Update that PID and APP will be empty if there's no app info
---
Documentat
On Mon, May 12, 2025 at 10:41 AM T.J. Mercier wrote:
>
> Use the same test buffers as the traditional iterator and a new BPF map
> to verify the test buffers can be found with the open coded dmabuf
> iterator.
>
> Signed-off-by: T.J. Mercier
> Acked-by: Christian König
Acked-by: Song Liu
With
On Mon, May 12, 2025 at 4:07 PM Steven J Abner wrote:
>
> On Fri, May 9 2025 at 03:01:13 PM +, Steven J Abner
> wrote:
> > On Fri, May 9 2025 at 02:05:16 PM +, Alex Deucher
> > wrote:
> >> bisect between 6.2.16 and 6.2.17 to identify the commit which broke
> >
> > Are you asking for a 'd
On Thu, May 08, 2025 at 10:15:15PM -0500, Andrew Ballance wrote:
> From: Fiona Behrens
>
> Replace the Io struct with a new MMIo struct that uses the different
> traits (`IoAccess`, `IoAccess64`, `IoAccessRelaxed` and
> `IoAccess64Relaxed).
> This allows to later implement PortIo and a generic Io
On 29/04/2025 22:11, Alex Hung wrote:
Typo in the commit msg: mutliplier -> multiplier
This introduces a new drm_colorop_type: DRM_COLOROP_MULTIPLIER.
It's a simple multiplier to all pixel values. The value is
specified via a S31.32 fixed point provided via the
"MULTIPLIER" property.
Review
AIC100 devices generates Reliability, Availability, Serviceability events
via MHI QAIC_STATUS channel. Support such events and print a structured
log with details of the events, and if the event describes an uncorrected
error, reset the device to put it back into service. As these events may
not al
Hi Lyude,
> On 5 Mar 2025, at 19:59, Lyude Paul wrote:
>
> Next up is filling out some of the basic connector hotplugging callbacks -
> which we'll need for setting up the fbdev helpers for KMS devices. Note
> that connector hotplugging in DRM follows a BFL scheme: pretty much all
> probing is p
On 04/29, Alex Hung wrote:
> From: Harry Wentland
>
> This adds support for the BT.709/BT.2020 transfer functions
> on all current 1D curve plane colorops, i.e., on DEGAM, SHAPER,
> and BLND blocks.
>
> With this change the following IGT subtests pass:
> kms_colorop --run plane-XR30-XR30-bt2020_
Hi Prabhakar,
Thanks for the patch.
> -Original Message-
> From: Prabhakar
> Sent: 12 May 2025 19:23
> Subject: [PATCH v5 07/12] drm: renesas: rz-du: mipi_dsi: Make "rst" reset
> control optional for
> RZ/V2H(P)
>
> From: Lad Prabhakar
>
> In preparation for adding support for the Re
On Thu, Apr 24, 2025 at 06:02:48PM +0200, Danilo Krummrich wrote:
> This patch series adds the nova-drm skeleton driver.
Applied to nova-next, thanks!
On Mon, May 12, 2025 at 11:58 AM Song Liu wrote:
>
> On Mon, May 12, 2025 at 10:41 AM T.J. Mercier wrote:
> [...]
> > +
> > +static int udmabuf;
>
> static int udmabuf = -1;
>
> > +static const char udmabuf_test_buffer_name[DMA_BUF_NAME_LEN] =
> > "udmabuf_test_buffer_for_iter";
> > +static size
On Mon, May 12, 2025 at 10:41 AM T.J. Mercier wrote:
[...]
> +
> +static int udmabuf;
static int udmabuf = -1;
> +static const char udmabuf_test_buffer_name[DMA_BUF_NAME_LEN] =
> "udmabuf_test_buffer_for_iter";
> +static size_t udmabuf_test_buffer_size;
> +static int sysheap_dmabuf;
static int
On 04/29, Alex Hung wrote:
> Expose one 1D curve colorop with support for
> DRM_COLOROP_1D_CURVE_SRGB_EOTF and program HW to perform
> the sRGB transform when the colorop is not in bypass.
>
> With this change the following IGT test passes:
> kms_colorop --run plane-XR30-XR30-srgb_eotf
>
> The co
From: Lad Prabhakar
Add DSI support for Renesas RZ/V2H(P) SoC.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v4->v5:
- No changes
v3->v4
- In rzv2h_dphy_find_ulpsexit() made the array static const.
v2->v3:
- Simplifed V2H DSI timings array
From: Lad Prabhakar
The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of
the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the
D-PHY registers differ. Additionally, the number of resets for DSI on
RZ/V2H(P) is two compared to three on the RZ/G2L.
To accom
From: Lad Prabhakar
Add clock and reset entries for the DSI and LCDC peripherals.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v4->v5:
- No changes
v3->v4:
- No changes
v2->v3:
- Reverted CSDIV0_DIVCTL2() to use DDIV_PACK()
- Renamed pllet
From: Lad Prabhakar
Add support for PLLDSI and PLLDSI divider clocks.
Introduce the `renesas-rzv2h-dsi.h` header to centralize and share
PLLDSI-related data structures, limits, and algorithms between the RZ/V2H
CPG and DSI drivers.
The DSI PLL is functionally similar to the CPG's PLLDSI, but ha
From: Lad Prabhakar
Hi All,
This patch series adds DU/DSI clocks and provides support for the
MIPI DSI interface on the RZ/V2H(P) SoC. It was originally part of
series [0], but has now been split into 4 patches due to dependencies
on the clock driver, making it easier to review and merge.
[0]
On 04/29, Alex Hung wrote:
> From: Harry Wentland
>
> Add the default Bypass pipeline and ensure it passes the
> kms_colorop test plane-XR30-XR30-bypass.
>
> Signed-off-by: Alex Hung
> Signed-off-by: Harry Wentland
> Reviewed-by: Daniel Stone
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_plane
On Sun, May 11, 2025 at 07:47:44PM -0300, André Almeida wrote:
> Add a section about "App information" for the wedge API.
>
> Signed-off-by: André Almeida
> ---
> Documentation/gpu/drm-uapi.rst | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/Documentation/gpu/drm-uapi.
On 5/7/2025 9:24 AM, Lizhi Hou wrote:
On 5/6/25 23:59, Jacek Lawrynowicz wrote:
Hi,
On 5/6/2025 5:41 PM, Lizhi Hou wrote:
On 5/6/25 02:20, Jacek Lawrynowicz wrote:
Use FW names from linux-firmware repo instead of deprecated ones.
Fixes: c140244f0cfb ("accel/ivpu: Add initial Panther Lake su
On 5/6/2025 3:13 AM, Jacek Lawrynowicz wrote:
- Fix missing alloc log when drm_gem_handle_create() fails in
drm_vma_node_allow() and open callback is not called
- Add ivpu_bo->ctx_id that enables to log the actual context
id instead of using 0 as default
- Add couple WARNs and errors so we
On 04/29, Alex Hung wrote:
> Create a new macro for_each_new_colorop_in_state to access new
> drm_colorop_state updated from uapi.
>
> Reviewed-by: Simon Ser
> Signed-off-by: Alex Hung
> Reviewed-by: Daniel Stone
> ---
> include/drm/drm_atomic.h | 20
> 1 file changed, 20
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.
Update the `mipi_dsi_host_attach()` function to check this flag before
From: Lad Prabhakar
In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch
introduces a mechanism to pass SoC-specific information via OF data in the
DSI driver. This enables the driver to adapt dynamically to various
SoC-specific requirements without hardcoding configuration
From: Lad Prabhakar
Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
`rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
supported display modes.
On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
possible. To ensure compatibility with both RZ/G2L and R
From: Lad Prabhakar
Add LPCLK clock support in the RZ/G2L MIPI DSI driver via the optional
clock API. This clock is required by some SoCs like RZ/V2H(P) for proper
DPHY configuration, whereas it is absent on others like RZ/G2L.
Introduce a new `lpclk` field in the `rzg2l_mipi_dsi` structure and
From: Lad Prabhakar
Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.
Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late
From: Lad Prabhakar
Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.
These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
Co-developed-by: Fabrizio Castro
Signed-off-by: F
From: Lad Prabhakar
Simplify the high-speed clock frequency (HSFREQ) calculation by removing
the redundant multiplication and division by 8. The updated equation:
hsfreq = (mode->clock * bpp) / (dsi->lanes);
produces the same result while improving readability and clarity.
Additionally, up
From: Lad Prabhakar
Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
VCLK rate instead of the mode clock. The relationship between HSCLK and
VCLK is:
vclk * bpp <= hsclk * 8 * lanes
Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that
HSFREQ accurately
From: Lad Prabhakar
In preparation for adding support for the Renesas RZ/V2H(P) SoC, make the
"rst" reset control optional in the MIPI DSI driver. The RZ/V2H(P) SoC
does not provide this reset line, and attempting to acquire it using the
mandatory API causes probe failure.
Switching to devm_rese
From: Lad Prabhakar
Hi All,
This patch series adds support for the Display Unit (DU) and prepares
the MIPI DSI driver to support the Renesas RZ/V2H(P) SoC. These patches
were originally part of series [0], but I have split them into two parts
to make them easier to review and merge.
This patch
From: Lad Prabhakar
The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabh
From: Lad Prabhakar
The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
Compression Processor (FCPVD), Video Signal Processor (VSPD), and
Display Unit (DU).
There is one LCDC unit available on the RZ/V2H(P) SoC which is connected
to the DSI.
Signed-off-by: Lad Prabhakar
Reviewe
From: Lad Prabhakar
The DU block on the RZ/V2H(P) SoC is identical to the one found on the
RZ/G2L SoC. However, it only supports the DSI interface, whereas the
RZ/G2L supports both DSI and DPI interfaces.
Due to this difference, a SoC-specific compatible string
'renesas,r9a09g057-du' is added fo
From: Austin Zheng
[ Upstream commit eba692ca3abca258b3214a6e4126afefad1822f0 ]
[Why]
Memory allocation occurs within dml21_validate() for adding phantom planes.
May cause kernel to be tainted due to usage of FP Start.
[How]
Move FP start from dml21_validate to before mode programming/mode supp
From: Austin Zheng
[ Upstream commit eba692ca3abca258b3214a6e4126afefad1822f0 ]
[Why]
Memory allocation occurs within dml21_validate() for adding phantom planes.
May cause kernel to be tainted due to usage of FP Start.
[How]
Move FP start from dml21_validate to before mode programming/mode supp
On 5/12/25 11:14, Tvrtko Ursulin wrote:
>
> On 12/05/2025 09:19, Christian König wrote:
>> On 5/9/25 17:33, Tvrtko Ursulin wrote:
>>> With the goal of reducing the need for drivers to touch fence->ops, we
>>> add explicit flags for struct dma_fence_array and struct dma_fence_chain
>>> and make the
Use the same test buffers as the traditional iterator and a new BPF map
to verify the test buffers can be found with the open coded dmabuf
iterator.
Signed-off-by: T.J. Mercier
Acked-by: Christian König
---
.../testing/selftests/bpf/bpf_experimental.h | 5 +++
.../selftests/bpf/prog_tests/dma
This test creates a udmabuf, and a dmabuf from the system dmabuf heap,
and uses a BPF program that prints dmabuf metadata with the new
dmabuf_iter to verify they can be found.
Signed-off-by: T.J. Mercier
Acked-by: Christian König
---
tools/testing/selftests/bpf/config| 3 +
.../se
This open coded iterator allows for more flexibility when creating BPF
programs. It can support output in formats other than text. With an open
coded iterator, a single BPF program can traverse multiple kernel data
structures (now including dmabufs), allowing for more efficient analysis
of kernel d
Rename the debugfs list and mutex so it's clear they are now usable
without the need for CONFIG_DEBUG_FS. The list will always be populated
to support the creation of a BPF iterator for dmabufs.
Signed-off-by: T.J. Mercier
Reviewed-by: Christian König
Acked-by: Song Liu
---
drivers/dma-buf/dma
The dmabuf iterator traverses the list of all DMA buffers.
DMA buffers are refcounted through their associated struct file. A
reference is taken on each buffer as the list is iterated to ensure each
buffer persists for the duration of the bpf program execution without
holding the list mutex.
Sign
Until CONFIG_DMABUF_SYSFS_STATS was added [1] it was only possible to
perform per-buffer accounting with debugfs which is not suitable for
production environments. Eventually we discovered the overhead with
per-buffer sysfs file creation/removal was significantly impacting
allocation and free times
Hi Melissa,
The patchset looks good to me but there is WIP dcn401 code, meaning
dcn20 and dcn401 are different.
I will check how to refactor code so this patchset can fit better.
Thanks
On 4/30/25 08:20, Melissa Wen wrote:
Hi,
I've been examining dcn401 code to figure out what is causing a
On Wed, Apr 23, 2025 at 12:31:29AM GMT, Danila Tikhonov wrote:
> description:
> - Qualcomm SC7180/SC7280 SoC Peripheral Authentication Service loads and
> boots
> - firmware on the Qualcomm DSP Hexagon cores.
> + Qualcomm SC7180/SC7280/SM7150 SoC Peripheral Authentication Service loads
> and
On Wed, Apr 23, 2025 at 12:31:30AM GMT, Danila Tikhonov wrote:
> Add DSP Peripheral Authentication Service support for the SM7150
> platform.
>
> Signed-off-by: Danila Tikhonov
> ---
> drivers/remoteproc/qcom_q6v5_pas.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/remotep
On Wed, Apr 23, 2025 at 12:31:28AM GMT, Danila Tikhonov wrote:
> SM7150 is fully compatible with the existing SC7180 GPU Clock
> Controller driver. Define corresponding compatible string, having the
> qcom,sc7180-gpucc as a fallback.
>
> Signed-off-by: Danila Tikhonov
> ---
> .../devicetree/bind
On Wed, Apr 23, 2025 at 12:31:27AM GMT, Danila Tikhonov wrote:
> Document the SM7150 SMMU block.
>
> Signed-off-by: Danila Tikhonov
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysz
On Wed, Apr 23, 2025 at 12:31:25AM GMT, Danila Tikhonov wrote:
> Update the documentation for clock rpmh driver on SM7150 SoCs.
>
> Signed-off-by: Danila Tikhonov
> ---
> .../bindings/clock/qcom,rpmhcc.yaml | 53 ++-
> 1 file changed, 29 insertions(+), 24 deletions(-)
>
On Wed, Apr 23, 2025 at 12:31:24AM GMT, Danila Tikhonov wrote:
> Add the SM7150 CCI device string compatible.
>
> Signed-off-by: Danila Tikhonov
> ---
> Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Krzysztof Kozlowski
Best rega
On Mon, May 12, 2025 at 02:34:22PM +0200, David Hildenbrand wrote:
> Let's just have it in a single function. The resulting function is
> certainly small enough and readable.
>
> Signed-off-by: David Hildenbrand
Nice, great bit of refactoring :) the new version is considerably clearer.
Reviewed-
On Mon, May 12, 2025 at 02:34:17PM +0200, David Hildenbrand wrote:
> Let's use our new interface. In remap_pfn_range(), we'll now decide
> whether we have to track (full VMA covered) or only lookup the
> cachemode (partial VMA covered).
>
> Remember what we have to untrack by linking it from the VM
Hi Lyude,
This patch is similar to the last one, I see that most of my
comments also apply here.
> On 5 Mar 2025, at 19:59, Lyude Paul wrote:
>
> The next step is adding a set of basic bindings to create a plane, which
> has to happen before we can create a CRTC (since we need to be able to at
> On 5 Mar 2025, at 19:59, Lyude Paul wrote:
>
> We start off by introducing wrappers for the first important type of mode
> object: a DRM display connector. This introduces Connector DriverConnector> and ConnectorState. Both
> DriverConnector and DriverConnectorState must be implemented by KM
On Sun, 11 May 2025 22:31:09 +1200, Ryan Walklin wrote:
> v10 of this patch series adding support for the Allwinner DE33 display
> engine. This version is largely based on the previous v8 patch, with Chris's
> changes to the mixer bindings in particular from v9 to add names for the new
> registe
Hi Biju,
Thank you for the review.
On Sun, May 4, 2025 at 2:00 PM Biju Das wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -Original Message-
> > From: Prabhakar
> > Sent: 30 April 2025 21:41
> > Subject: [PATCH v4 14/15] drm: renesas: rz-du: mipi_dsi: Add support for
> > LPCL
On Sun, May 11, 2025 at 10:31:09PM +1200, Ryan Walklin wrote:
> Hi all,
>
> v10 of this patch series adding support for the Allwinner DE33 display
> engine. This version is largely based on the previous v8 patch, with Chris's
> changes to the mixer bindings in particular from v9 to add names for
On Mon, May 12, 2025 at 3:58 AM Bagas Sanjaya wrote:
>
> Documentation/userspace-api/media/glossary.rst:170: WARNING: duplicate term
> description of SPI, other instance in gpu/amdgpu/amdgpu-glossary
>
> That's because SPI of amdgpu (Shader Processor Input) shares the same
> global glossary term
On Mon, May 12, 2025 at 02:34:15PM +0200, David Hildenbrand wrote:
> ... by factoring it out from track_pfn_remap() into
> pfnmap_setup_cachemode() and provide pfnmap_setup_cachemode_pfn() as
> a replacement for track_pfn_insert().
>
> For PMDs/PUDs, we keep checking a single pfn only. Add some doc
On Sun, May 11, 2025 at 8:13 AM Dr. David Alan Gilbert
wrote:
>
> * Christophe JAILLET (christophe.jail...@wanadoo.fr) wrote:
> > Le 18/04/2025 à 02:21, li...@treblig.org a écrit :
> > > From: "Dr. David Alan Gilbert"
> > >
> > > radeon_doorbell_free() was added in 2013 by
> > > commit 75efdee11b
On Sun, May 11, 2025 at 07:47:43PM -0300, André Almeida wrote:
> When a device get wedged, it might be caused by a guilty application.
> For userspace, knowing which app was the cause can be useful for some
> situations, like for implementing a policy, logs or for giving a chance
> for the composit
Hi Biju,
Thank you for the review.
On Sun, May 4, 2025 at 1:41 PM Biju Das wrote:
>
> Hi Prabhakar,
>
> > -Original Message-
> > From: Prabhakar
> > Sent: 30 April 2025 21:41
> > Subject: [PATCH v4 09/15] drm: renesas: rz-du: mipi_dsi: Add OF data support
> >
> > From: Lad Prabhakar
>
Goal here is cut over to gpusvm and remove xe_hmm, relying instead on
common code. The core facilities we need are get_pages(), unmap_pages()
and free_pages() for a given useptr range, plus a vm level notifier
lock, which is now provided by gpusvm.
v2:
- Reuse the same SVM vm struct we use for f
We now use the same notifier lock for SVM and userptr, with that we can
combine xe_pt_userptr_pre_commit and xe_pt_svm_pre_commit.
v2: (Matt B)
- Re-use xe_svm_notifier_lock/unlock for userptr.
- Combine svm/userptr handling further down into op_check_svm_userptr.
Suggested-by: Matthew Brost
This will simplify compiling out the bits that depend on DRM_GPUSVM in a
later patch. Without this we end up littering the code with ifdef
checks, plus it becomes hard to be sure that something won't blow at
runtime due to something not being initialised, even though it passed
the build. Should be
Export get/unmap/free pages API. We also need to tweak the SVM init to
allow skipping much of the unneeded parts.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/drm_gpusvm.c | 66
include/d
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