From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>

Add LPCLK clock support in the RZ/G2L MIPI DSI driver via the optional
clock API. This clock is required by some SoCs like RZ/V2H(P) for proper
DPHY configuration, whereas it is absent on others like RZ/G2L.

Introduce a new `lpclk` field in the `rzg2l_mipi_dsi` structure and
conditionally acquire the "lpclk" clock using `devm_clk_get_optional()`
during probe. This allows LPCLK-aware SoCs to pass the clock via device
tree without impacting existing platforms.

Co-developed-by: Fabrizio Castro <fabrizio.castro...@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro...@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
Reviewed-by: Biju Das <biju.das...@bp.renesas.com>
---
v4->v5:
- Made use of devm_clk_get_optional() for lpclk
- Added Reviewed tag from Biju

v3->v4
- No changes

v2->v3:
- No changes

v1->v2:
- Added LPCLK as feature flag
---
 drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c 
b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index 35f0bceac055..98d2f30ae79d 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -62,6 +62,7 @@ struct rzg2l_mipi_dsi {
        struct drm_bridge *next_bridge;
 
        struct clk *vclk;
+       struct clk *lpclk;
 
        enum mipi_dsi_pixel_format format;
        unsigned int num_data_lanes;
@@ -790,6 +791,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_device 
*pdev)
        if (IS_ERR(dsi->vclk))
                return PTR_ERR(dsi->vclk);
 
+       dsi->lpclk = devm_clk_get_optional(dsi->dev, "lpclk");
+       if (IS_ERR(dsi->lpclk))
+               return PTR_ERR(dsi->lpclk);
+
        dsi->rstc = devm_reset_control_get_optional_exclusive(dsi->dev, "rst");
        if (IS_ERR(dsi->rstc))
                return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
-- 
2.49.0

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