Hi, Yongqiang:
On Mon, 2019-12-02 at 17:03 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> add ctm property support
>
> Change-Id: I8111da7b309b1809c6302e7748dd9fd06dc97bde
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 15 ++-
>
relevant display controller registers
> with critical time limation.
>
> Signed-off-by: YT Shen
> Signed-off-by: CK Hu
> Signed-off-by: Philipp Zabel
> Signed-off-by: Bibby Hsieh
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc
ace can support cpu/cmdq function
> at the same time.
>
> Signed-off-by: YT Shen
> Signed-off-by: CK Hu
> Signed-off-by: Philipp Zabel
> Signed-off-by: Bibby Hsieh
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +-
> driv
Hi, Bibby:
On Wed, 2019-12-04 at 17:44 +0800, Bibby Hsieh wrote:
> Support to async updates of cursors by using the new atomic
> interface for that.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 75 +---
>
Hi, Bibby:
You move the mutex protection to [PATCH v2 6/6] drm/mediatek: apply CMDQ
control flow, but the race condition exist in this patch. So you should
move that back in this patch.
Regards,
CK
On Tue, 2019-12-03 at 15:10 +0800, Bibby Hsieh wrote:
> Support to async updates of cursors by
Hi, Bibby:
On Tue, 2019-12-03 at 15:10 +0800, Bibby Hsieh wrote:
> layer_on and layer_off both are unused external function,
> remove them from mtk_ddp_comp_funcs structure.
>
Reviewed-by: CK Hu
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_d
Hi, Yongqiang:
On Tue, 2019-12-03 at 15:43 +0800, Yongqiang Niu wrote:
> On Tue, 2019-12-03 at 13:48 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> >
> > On Wed, 2019-11-27 at 09:17 +0800, yongqiang@mediatek.com wrote:
> > > From: Yongqiang Niu
> > >
&
Hi, Yongqiang:
I would like the title could clearly express what does this patch do. I
think what this patch do is to implement prepare/unprepare interface for
dpi driver. And you could describe why do this in commit message.
On Wed, 2019-11-27 at 09:17 +0800, yongqiang@mediatek.com wrote:
Hi, Bibby:
On Tue, 2019-12-03 at 13:58 +0800, Bibby Hsieh wrote:
> On Tue, 2019-12-03 at 09:38 +0800, CK Hu wrote:
> > Hi, Bibby:
> >
> > On Thu, 2019-11-28 at 10:42 +0800, Bibby Hsieh wrote:
> > > Unlike other SoCs, MT8183 does not have "shadow"
> &g
Hi, Yongqiang:
On Wed, 2019-11-27 at 09:17 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Problem:
> overlay hangup when external display hotplut test
>
> Fix:
> disable overlay when crtc disable
I think you do two things in this patch. The first is to config layer
before
Hi, Yongqiang:
On Mon, 2019-12-02 at 17:03 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> add ctm property support
>
> Change-Id: I8111da7b309b1809c6302e7748dd9fd06dc97bde
Remove this Change-Id.
> Signed-off-by: Yongqiang Niu
> ---
>
Hi, Bibby:
On Tue, 2019-12-03 at 10:56 +0800, CK Hu wrote:
> Hi, Bibby:
>
> On Thu, 2019-11-28 at 10:42 +0800, Bibby Hsieh wrote:
> > The CMDQ (Command Queue) in MT8183 is used to help
> > update all relevant display controller registers
> > with critical time limati
ace can support cpu/cmdq function
> at the same time.
>
> Signed-off-by: YT Shen
> Signed-off-by: CK Hu
> Signed-off-by: Philipp Zabel
> Signed-off-by: Bibby Hsieh
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +-
> driv
relevant display controller registers
> with critical time limation.
>
> Signed-off-by: YT Shen
> Signed-off-by: CK Hu
> Signed-off-by: Philipp Zabel
> Signed-off-by: Bibby Hsieh
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c
Hi, Bibby:
On Thu, 2019-11-28 at 10:42 +0800, Bibby Hsieh wrote:
> Support to async updates of cursors by using the new atomic
> interface for that.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 35 +
>
Hi, Yongqiang:
On Mon, 2019-12-02 at 16:24 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Mon, 2019-12-02 at 15:31 +0800, yongqiang@mediatek.com wrote:
> > From: Yongqiang Niu
> >
> > add ctm property support
> >
> > Signed-off-by: Yongqiang Niu
Hi, Yongqiang:
On Mon, 2019-12-02 at 15:31 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> add ctm property support
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 7 +++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 59
>
o
> event objects being leaked in the kernel and to events not being sent
> out. Fix it.
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/medi
Hi, Bibby:
On Thu, 2019-11-28 at 10:42 +0800, Bibby Hsieh wrote:
> The DRM core atomic helper now supports asynchronous commits natively.
> The custom drm implementation isn't needed anymore, remove it.
Reviewed-by: CK Hu
Regards,
CK
>
> Signed-off-by: Bibby Hsieh
> ---
>
are only
> 2 layer nr in external display, and this condition will never happen:
> if (plane->index < (count + mtk_ddp_comp_layer_nr(comp)))
>
> Fix this by using the offset of the plane to mtk_crtc->planes as index,
> instead of plane->index.
Reviewed-by: CK Hu
Regards,
Hi, Yongqiang:
On Tue, 2019-11-26 at 14:47 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch fix up 1440x900 dp display black screen issue
> the computed result will overflow rdma1 fifo max size
> when external display pixel clock bigger than 74MHZ
>
>
Hi, Pi-Hsun:
On Mon, 2019-11-18 at 14:18 +0800, Pi-Hsun Shih wrote:
> The mtk_drm_ddp_comp_for_plane can return NULL, but the usage doesn't
> check for it. Add check for it.
Reviewed-by: CK Hu
>
> Fixes: d6b53f68356f ("drm/mediatek: Add helper to get component for a pla
contain one
> function.
Acked-by: CK Hu
>
> Signed-off-by: Daniel Vetter
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: Matthias Brugger
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-media...@lists.infradead.org
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c
Hi Dave, Daniel:
This round add new color format support and reflect function.
Regards,
CK
The following changes since commit
631005b255aab5f846f7ca03606613f898d70207:
drm/mediatek: add no_clk into ddp private data (2019-10-09 16:58:13
+0800)
are available in the Git repository at:
Hi, Sean:
On Wed, 2019-11-06 at 09:42 -0500, Sean Paul wrote:
> On Wed, Nov 6, 2019 at 4:07 AM CK Hu wrote:
> >
> > Hi, Sean:
> >
> > On Tue, 2019-11-05 at 16:10 -0500, Sean Paul wrote:
> > > From: Sean Paul
> > >
> > > Now that we suppo
Hi, Sean:
On Tue, 2019-11-05 at 16:10 -0500, Sean Paul wrote:
> From: Sean Paul
>
> Now that we support both reflections, we can expose 180 degree rotation
> and rely on the simplify routine to convert that into REFLECT_X |
> REFLECT_Y
>
Patch 1 ~ 6 of this series looks good to me.
For this
Hi, Sean:
On Fri, 2019-11-01 at 09:26 -0400, Sean Paul wrote:
> From: Sean Paul
>
> Expose the rotation property and handle REFLECT_Y rotations.
>
> Cc: Fritz Koenig
> Cc: Daniele Castagna
> Cc: Miguel Casas
> Cc: Mark Yacoub
> Signed-off-by: Sean Paul
> ---
>
> The hardware also
Hi, Sean:
On Fri, 2019-11-01 at 09:26 -0400, Sean Paul wrote:
> From: Sean Paul
>
> Expose the rotation property and handle REFLECT_Y rotations.
>
> Cc: Fritz Koenig
> Cc: Daniele Castagna
> Cc: Miguel Casas
> Cc: Mark Yacoub
> Signed-off-by: Sean Paul
> ---
>
> The hardware also
Hi, Bibby:
On Fri, 2019-10-25 at 13:38 +0800, Bibby Hsieh wrote:
> Support to async updates of cursors by using the new atomic
> interface for that.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 32 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h
Hi, Bibby:
On Fri, 2019-10-25 at 13:38 +0800, Bibby Hsieh wrote:
> Support to async updates of cursors by using the new atomic
> interface for that.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 32 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h
Hi, Bibby:
On Fri, 2019-10-25 at 13:38 +0800, Bibby Hsieh wrote:
> In order to commit state asynchronously, we change
> .atomic_commit to drm_atomic_helper_commit().
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 11
>
1519/)
> support gce on mt8183 platform
> (https://patchwork.kernel.org/cover/11208315/)
>
> Changes since v1:
> - remove unnecessary change
> - fixup indent
>
> Signed-off-by: YT Shen
> Signed-off-by: CK Hu
> Signed-off-by: Philipp Zabel
> Signed-off-by: Bibby
Hi, Sean:
On Wed, 2019-10-23 at 15:51 -0400, Sean Paul wrote:
> From: Sean Paul
>
> These formats are handled in the rdma code, but for some reason they're
> not published as supported formats for the planes. So add them to the
> list.
Applied to mediatek-drm-fixes-5.4 [1], thanks.
[1]
Hi, Rob:
On Wed, 2019-10-23 at 17:56 -0500, Rob Herring wrote:
> On Wed, Oct 23, 2019 at 4:06 PM CK Hu wrote:
> >
> > Hi, Rob:
> >
> > On Wed, 2019-10-23 at 12:42 -0500, Rob Herring wrote:
> > > On Tue, Oct 22, 2019 at 12:07 PM Matthias Brugger
't use the CMA helpers is it
> > > sets DMA_ATTR_NO_KERNEL_MAPPING and does a vmap() on demand. Using
> > > vmap() is not even guaranteed to work as DMA buffers may not have a
> > > struct page. Now that the CMA helpers support setting
> > > DMA_ATTR_NO_KERNEL_MAPPING as needed or n
CK Hu (1):
drm/mediatek: add no_clk into ddp private data
Jitao Shi (12):
dt-bindings: display: mediatek: update dsi supported chips
drm/mediatek: separate mipi_tx to different file
drm/mediatek: add mipi_tx driver
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
>
I've rewrite this patch and applied to mediatek-drm-next-5.5 [1] with
the title "drm/mediatek: add no_clk into ddp private data",
Hi, Yongqiang:
To make process more smoothly, I've applied some stable patches of this
series in mediatek-drm-next-5.5 [1]. The applied patches include
dt-bindings, CCORR, DITHER, OVL, Mutex related patches. The non-applied
patches include mmsys related patches. Please based on the applied
tek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 13 ++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> b/drivers/gp
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 43
> +++---
> 1 file changed, 35 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> b
tek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 24
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_dd
m/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 41
> +-
> 1 file changed, 30 insertions(+), 11 deletions(-)
>
>
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add ovl0/ovl_2l0 usecase
> in ovl->ovl_2l0 direct link usecase:
> 1. the crtc support layer number will 4+2
> 2. ovl_2l0 background color input select ovl0 when crtc init
>
ts/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/
> input select for these hardware.
> this is preparation patch for ovl/ovl_2l usecase
>
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
>
ek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ov
reparation for ovl-2l and
> ovl share the same driver.
>
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers
hd_l not
> used.
>
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 23
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32
> +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
> 2 files changed, 34 insertions(+)
>
> diff --git a/drivers/g
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32
> +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
> 2 files changed, 34 insertions(+)
>
> diff --git a/drivers/g
ne tune add frame size control coding style
> - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL
> - use div_u64 when 80ULL / dsi->data_rate.
>
> Changes since v3
> - add one more 'tab' for bitwise define.
> - add Tested-by: Ryan Case
> and R
Hi, Jitao:
On Mon, 2019-09-23 at 13:36 +0800, CK Hu wrote:
> Hi, Jitao:
>
> On Fri, 2019-09-20 at 17:04 +0800, Jitao Shi wrote:
> > Update device tree binding documentation for the dsi for
> > Mediatek MT8183 SoCs.
> >
> > Signed-off-by: Jitao Shi
> > A
Hi, Jitao:
On Fri, 2019-09-20 at 17:04 +0800, Jitao Shi wrote:
> This patch add mt8183 mipi_tx driver.
> And also support other chips that use the same binding and driver.
Reviewed-by: CK Hu
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/Makefile
Hi, Jitao:
On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> Add dphy reset after setting lanes number to avoid dphy fifo effor.
Reviewed-by: CK Hu
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 9 +
> 1 file changed, 9 insertions(
_BURST
> hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> else
> hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
>
> Note:
> //(2: 1 for sync, 1 for phy idle)
> data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
>
> bpp: bit per pixel
Hi, Jitao:
On Thu, 2019-09-19 at 14:57 +0800, Jitao Shi wrote:
> Config the different CMDQ reg address in driver data.
Reviewed-by: CK Hu
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 27 ++-
> 1 file changed, 22 insertio
Hi, Jitao:
On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> The writeb() is unavailable in mt8173. Because the mt8173 dsi module
> doesn't support 8bit mode access.
Reviewed-by: CK Hu
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 4 +++-
&g
Hi, Jitao:
On Fri, 2019-09-20 at 17:04 +0800, Jitao Shi wrote:
> Update device tree binding documentation for the dsi for
> Mediatek MT8183 SoCs.
>
> Signed-off-by: Jitao Shi
> Acked-by: Rob Herring
This version is different with previous version [1], so I think you
should drop the 'Acked-by'
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add support for mediatek SOC MT8183
> 1.ovl_2l share driver with ovl
> 2.rdma1 share drive with rdma0, but fifo size is different
> 3.add mt8183 mutex private data, and mmsys
V_ROUND_UP_ULL
> - use div_u64 when 80ULL / dsi->data_rate.
>
> Changes since v3
> - add one more 'tab' for bitwise define.
> - add Tested-by: Ryan Case
> and Reviewed-by: CK Hu .
> - remove compare da_hs_zero to da_hs_prepare.
>
> Changes since v
Hi, Jitao:
For this series, applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
On Wed, 2019-08-07 at 16:46 +0800, Jitao Shi wrote:
> Change since v5:
> - remove mipi_tx->ref_clk
> - remove mt8183 pll
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add mutex description for mt8183 display
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Update device tree binding documention for the display subsystem for
> Mediatek MT8183 SOCs
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Update device tree binding documention for the display subsystem for
> Mediatek MT8183 SOCs
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Update device tree binding documention for the display subsystem for
> Mediatek MT8183 SOCs
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
Hi, Yongqiang:
On Fri, 2019-08-30 at 13:58 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> > From: Yongqiang Niu
> >
> > This patch add ovl0/ovl_2l0 usecase
> > in ovl->ovl_2l0 direct link us
ace can support cpu/cmdq function
> at the same time.
>
> Signed-off-by: YT Shen
> Signed-off-by: CK Hu
> Signed-off-by: Philipp Zabel
> Signed-off-by: Bibby Hsieh
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +-
> driv
Hi, Bibby:
On Fri, 2019-08-30 at 15:38 +0800, Bibby Hsieh wrote:
> Moving the driver to atomic helpers regressed cursor responsiveness,
> because cursor updates need their own atomic commits, which have to be
> serialized with other commits, that might include fence waits. To avoid
> this, in
Hi, Bibby:
On Fri, 2019-08-30 at 15:38 +0800, Bibby Hsieh wrote:
> Currently we use a single mutex to allow only a single atomic
> update at a time. In truth, though, we really only want to
> ensure that only a single atomic update is allowed per CRTC.
>
> In other words, for each atomic update,
relevant display controller registers
> with critical time limation.
>
> Signed-off-by: YT Shen
> Signed-off-by: CK Hu
> Signed-off-by: Philipp Zabel
> Signed-off-by: Bibby Hsieh
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add support for mediatek SOC MT8183
> 1.ovl_2l share driver with ovl
> 2.rdma1 share drive with rdma0, but fifo size is different
> 3.add mt8183 mutex private data, and mmsys
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from RDMA0 to DSI0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from DITHER0 to DSI0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from OVL_2L1 to RDMA1
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 6 ++
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> this patch add add connection from OVL_2L0 to RDMA0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 1
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from RDMA1 to DSI0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from RDMA0 to COLOR0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from OVL0 to OVL_2L0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
> 1 file changed, 6 insertions(+),
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add ovl0/ovl_2l0 usecase
> in ovl->ovl_2l0 direct link usecase:
> 1. the crtc support layer number will 4+2
> 2. ovl_2l0 background color input select ovl0 when crtc init
>
secase should move to mtk_ddp_sout_sel
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 90
> +-
> 1 file changed, 45 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/m
Hi, Yongqiang:
On Fri, 2019-08-30 at 13:27 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> > From: Yongqiang Niu
> >
> > This patch add mmsys private data for ddp path config
> > al
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add mmsys private data for ddp path config
> all these register offset and value will be different in future SOC
> add these define into mmsys private data
> u32
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Here is two modifition in this patch:
> 1.bls->dpi0 and rdma1->dsi are differen usecase,
> Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase
> 2.remove DISP_REG_CONFIG_DPI_SEL
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Update device tree binding documention for the display subsystem for
> Mediatek MT8183 SOCs
>
> Signed-off-by: Yongqiang Niu
> ---
>
Hi Dave, Daniel:
This include PRIME buffer and of_node fixes.
Regards,
CK
The following changes since commit
5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
https://github.com/ckhu-mediatek/linux.git-tags
Hi, Nishka:
On Sat, 2019-07-06 at 19:00 +0530, Nishka Dasgupta wrote:
> Each iteration of for_each_child_of_node puts the previous
> node, but in the case of a goto from the middle of the loop, there is
> no put, thus causing a memory leak. Hence add an of_node_put before the
> goto in two
Hi, Alexandre:
On Mon, 2019-07-29 at 14:33 +0900, Alexandre Courbot wrote:
> The default DMA segment size was used when importing PRIME buffers,
> which resulted in a chance of them not being contiguous in the virtual
> IO space of the device and mtk_gem_prime_import_sg_table() complaining
> that
Hi, Jitao:
On Sun, 2019-08-11 at 18:40 +0800, Jitao Shi wrote:
> Config the different CMDQ reg address in driver data.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 29 -
> 1 file changed, 24 insertions(+), 5 deletions(-)
>
> diff --git
Hi, Jitao:
On Wed, 2019-08-07 at 14:02 +0800, Jitao Shi wrote:
> The factor depends on the divider of DPI in MT8183, therefore,
> we should fix this factor to the right and new one.
>
Reviewed-by: CK Hu
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/media
Hi, Rob:
On Wed, 2019-07-24 at 14:16 -0600, Rob Herring wrote:
> On Tue, Jul 09, 2019 at 06:33:45AM +0800, yongqiang@mediatek.com wrote:
> > From: Yongqiang Niu
> >
> > This patch add RDMA1 description for mt8183 display
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> >
Hi, Alexandre:
On Tue, 2019-07-23 at 14:34 +0900, Alexandre Courbot wrote:
> This driver requires imported PRIME buffers to appear contiguously in
> its IO address space. Make sure this is the case by setting the maximum
> DMA segment size to a better value than the default 64K on the DMA
>
Hi, YueHaibing:
On Wed, 2019-07-24 at 01:33 +, YueHaibing wrote:
> Remove duplicated include.
>
> Signed-off-by: YueHaibing
Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/dr
Hi, Sam:
You could apply this patch into drm-misc-next by yourself, thanks.
Regards,
CK
On Fri, 2019-07-19 at 09:30 +0800, CK Hu wrote:
> On Thu, 2019-07-18 at 18:15 +0200, Sam Ravnborg wrote:
> > Do not rely on including drm.h from drm_file.h,
> > as the include in drm_file.h
On Thu, 2019-07-18 at 18:15 +0200, Sam Ravnborg wrote:
> Do not rely on including drm.h from drm_file.h,
> as the include in drm_file.h will be dropped.
>
Acked-by: CK Hu
> Signed-off-by: Sam Ravnborg
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: Matthias Brugger
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:34 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
> 1 file changed, 6 insertions(+),
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:34 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> distinguish ovl and ovl_2l by layer_nr when get comp
> id
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:34 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add ovl0/ovl_2l0 usecase
> in ovl->ovl_2l0 direct link usecase:
> 1. the crtc support layer number will 4+2
> 2. ovl_2l0 background color input select ovl0 when crtc init
>
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