give us an alternate interface to do unicast per-instance
save/restore operations, so we should be very clear about which
registers on the list are MCR registers (and in the future which
save/restore behavior we want for them).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_
cate the register definitions for those registers in
preparation for upcoming patches that will handle MCR registers in a
special manner.
The registers adjusted are:
* MISCCPCTL
* SAMPLER_INSTDONE
* ROW_INSTDONE
* ROW_CHICKEN2
* HALF_SLICE_CHICKEN1
* HALF_SLICE_CHICKEN3
Signed-off-by: Ma
The fault registers are multicast registers, replicated per-mslice
starting on Xe_HP. When checking for faults, we should check each
mslice's instance of the register rather than just one of the instances.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c
refix to "XEHP_" to help clarify that we're using the
newer multicast form of the register.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +-
2 files changed, 9 insertions(+), 9 dele
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper
---
dr
eg_t. We
may want to think about better ways to handle heterogeneous lists of MCR
and non-MCR registers, or possibly just convert those to lists of u32
offsets since we're not actually using them to perform MMIO accesses.
Cc: Daniele Ceraolo Spurio
Cc: Lucas De Marchi
Cc: Tvrtko Ursuli
hosting 2 8 bit numbers to holding a
> > > i915_engine_class_instance struct
> > >
> > > Cc: Ashutosh Dixit
> > > Cc: Matt Roper
> > > Cc: Joonas Lahtinen
> > > UMD (mesa):
> > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_req
soon, so the information reported here will become
increasingly valuable once that happens.
v2:
- Adding missing 'static' on intel_steering_types[] (Jose, sparse)
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/d
d-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 22 +---
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 6b944de48666..2d5d011e01db 100644
ering, we set the
steering for all entries in the guc list that do not require a special
steering (e.g. mslice) to the default settings; this will cost us a few
extra writes during engine reset but allows us to keep the steering
logic simple.
Cc: John Harrison
Cc: Matt Roper
Signed-off-by: Da
2013088509 suggests that
we leave the multicast bit enabled when performing read operations, so
we follow suit here.
Cc: Harish Chegondi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 75 ++---
drivers/gp
soon, so the information reported here will become
increasingly valuable once that happens.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 46 +
drivers/gpu/drm/i915/gt/intel_gt.h | 2 +
drivers/gpu/drm/i915/gt
save/restore list
Matt Roper (2):
drm/i915: Report steering details in debugfs
drm/i915: Add support for steered register writes
drivers/gpu/drm/i915/gt/intel_gt.c | 75 +
drivers/gpu/drm/i915/gt/intel_gt.h | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_debu
On Fri, Mar 11, 2022 at 11:01:01PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 11, 2022 at 12:52:33PM -0800, Lucas De Marchi wrote:
> > On Fri, Mar 11, 2022 at 12:43:40PM -0800, Matt Roper wrote:
> > >On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> > >>
On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> > On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > > Xe_HP removed "slice" as a first-class unit in the hardware design.
On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > Xe_HP removed "slice" as a first-class unit in the hardware design.
> > Instead we now have a single pool of subslices (which are now refer
irement for sseu
topology. We'll also document some of the constants to make it a little
bit more clear what they represent.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_sseu.h | 47 +++-
2 files chan
whether each DSS is accessible for geometry and/or compute.
- Rename "rcs_topology" to "sseu_topology" since the information
reported is common to both RCS and CCS engines now.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 48 +-
MattR/Tvrtko)
Cc: Matt Roper
Cc: Prathap Kumar Valsan
Cc: John Harrison
Cc: Joonas Lahtinen
Cc: Jani Nikula
Cc: Tvrtko Ursulin
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 50 ++
drivers/gpu/drm/i915/gt/intel
batch-level vs
command-level vs object-level).
v2 (MattR):
- Move debugfs interface to a separate patch. (Jani)
Cc: Matt Roper
Cc: Prathap Kumar Valsan
Cc: John Harrison
Cc: Joonas Lahtinen
Cc: Jani Nikula
Cc: Tvrtko Ursulin
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Matt Roper
On Fri, Mar 04, 2022 at 12:13:12PM +0200, Jani Nikula wrote:
> On Thu, 03 Mar 2022, Matt Roper wrote:
> > From: Akeem G Abodunrin
> >
> > Starting with DG2, preemption can no longer be controlled using userspace
> > on a per-context basis. Instead, the hardware
ag earlier and use it for the pre-emption w/a
> test.
>
> Fixes: c674c5b9342e ("drm/i915/xehp: CCS should use RCS setup functions")
> Cc: Tvrtko Ursulin
> Cc: Daniele Ceraolo Spurio
> Cc: Aravind Iddamsetty
> Cc: Matt Roper
> Cc: Tvrtko Ursulin
> Cc: Danie
batch-level vs
command-level vs object-level).
As a result of this - for debugging purposes, this patch adds debugfs
interface to configure (disable/enable) preemption globally.
Jira: VLK-27831
Cc: Matt Roper
Cc: Prathap Kumar Valsan
Cc: John Harrison
Cc: Joonas Lahtinen
Signed-off-by: Akeem
From: Stuart Summers
If RCS is not enumerated, GuC will return invalid parameters.
Make sure we do not send RCS supported when we have not enumerated
it.
Cc: Vinay Belgaumkar
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
1
ome of the general setup
(RCU_MODE programming, initialization of certain workarounds, etc.).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 5 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 ++
drivers/gpu/drm/i915/gt/intel_execlists_submis
On Sun, Feb 27, 2022 at 10:22:20PM +0530, Ramalingam C wrote:
> Matt,
>
> Thanks for the review.
>
> On 2022-02-18 at 17:47:22 -0800, Matt Roper wrote:
> > On Sat, Feb 19, 2022 at 12:17:52AM +0530, Ramalingam C wrote:
> > > From: Ayaz A Siddiqui
> > >
we've determined that we're
running on an Xe_HP platform where the logic makes sense (and won't
overflow).
Cc: Stuart Summers
Cc: Vinay Belgaumkar
Cc: Ashutosh Dixit
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
dri
On Tue, Mar 01, 2022 at 03:15:45PM -0800, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> Tell GuC that CCS is enabled by setting a bit in its ADS.
>
> Cc: Vinay Belgaumkar
> Original-author: Michel Thierry
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by:
ume() vfunc. (Umesh)
Bspec: 46034
Original-author: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Cc: Umesh Nerlige Ramappa
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
Reviewed-by: Umesh Nerlige Rama
On Tue, Mar 01, 2022 at 03:15:49PM -0800, Matt Roper wrote:
> From: Srinivasan Shanmugam
>
> Registers that exist in the shared render/compute reset domain need to
> be placed on an engine workaround list to ensure that they are properly
> re-applied whenever an RCS or CCS engin
On Tue, Mar 01, 2022 at 03:51:21PM -0800, Umesh Nerlige Ramappa wrote:
> On Tue, Mar 01, 2022 at 03:15:44PM -0800, Matt Roper wrote:
> > We have to specify in the Render Control Unit Mode register
> > when CCS is enabled.
> >
> > v2:
> > - Move RCU_MODE programmi
On Tue, Mar 01, 2022 at 03:15:47PM -0800, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> HW resources are divided across the active CCS engines at the compute
> slice level, with each CCS having priority on one of the cslices.
> If a compute slice has no enabled DSS, its
w
function will internally be added to the first present RCS or CCS
engine's workaround list to ensure they get applied (and only get
applied once rather than being needlessly re-applied several times).
Co-author: Srinivasan Shanmugam
Signed-off-by: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio
From: Daniele Ceraolo Spurio
Tell GuC that CCS is enabled by setting a bit in its ADS.
Cc: Vinay Belgaumkar
Original-author: Michel Thierry
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
1 file changed, 1 insertion
, L3SQCREG1_CCS0,
GEN12_MERT_MOD_CTRL, and GEN12_GAMCNTRL_CTRL) that are incorrectly
implemented on the 'gt' workaround list and need to be moved
accordingly.
Cc: Matt Roper
Signed-off-by: Srinivasan Shanmugam
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarou
-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 +
.../drm/i915/gt/intel_execlists_submission.c| 16
drivers/gpu/drm/i915/gt/intel_gt_regs.h
From: Matthew Brost
A different emit breadcrumbs ring programming is required for compute /
render and we don't have UMD user so just reject parallel submission for
these engine classes.
Signed-off-by: Matthew Brost
Signed-off-by: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio
---
dr
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 +++
drivers/gpu/drm/i915/gt/intel_sseu.c | 17 ---
drivers/gpu/drm/i915/gt/intel_sseu.h | 4 +++-
3 files changed, 42 insertions(+), 4 deletions
and relies on the
existing context priority to set it to low/normal/high.
Bspec: 46145, 46260
Original-author: Michel Thierry
Cc: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Prasad Nallani
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/d
damsetty
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm
This is a more appropriate header for these definitions.
v2:
- Cleanup whitespace. (Lucas)
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 34 ---
drivers/gpu/drm/i915
bits must not be set
v2:
- Drop unwanted blank line. (Lucas)
Bspec: 47112
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34
and CCS3 are in a new one.
BSpec: 50844, 54029, 54030, 53223, 53224.
Original-author: Michel Thierry
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915
45544
Original-author: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Signed-off-by: Rodrigo Vivi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin #v1
---
drivers/gpu/drm/i915/gt/inte
-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3190b7b462a9..3150c0847f65 100644
--- a/drivers/gpu
K) condition on fusing check with a simple IP
version test to omit pre-Xe_HP platforms.
- Fix a handful of checkpatch warnings.
Daniele Ceraolo Spurio (3):
drm/i915/xehp: compute engine pipe_control
drm/i915/xehp/guc: enable compute engine inside GuC
drm/i915/xehp: handle fused off CCS eng
On Mon, Feb 28, 2022 at 09:42:43AM -0800, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> HW resources are divided across the active CCS engines at the compute
> slice level, with each CCS having priority on one of the cslices.
> If a compute slice has no enabled DSS, its
Platforms with FlatCCS do not use auxiliary planes for compression
control data and thus do not need traditional aux table invalidation
(and the registers no longer even exist).
Original-author: CQ Tang
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 28
and relies on the
existing context priority to set it to low/normal/high.
Bspec: 46145, 46260
Original-author: Michel Thierry
Cc: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Prasad Nallani
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/d
This is a more appropriate header for these definitions.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 34 ---
drivers/gpu/drm/i915/gt/intel_lrc.h | 34 +++
3 files
, L3SQCREG1_CCS0,
GEN12_MERT_MOD_CTRL, and GEN12_GAMCNTRL_CTRL) that are incorrectly
implemented on the 'gt' workaround list and need to be moved
accordingly.
Cc: Matt Roper
Signed-off-by: Srinivasan Shanmugam
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarou
From: Matthew Brost
A different emit breadcrumbs ring programming is required for compute /
render and we don't have UMD user so just reject parallel submission for
these engine classes.
Signed-off-by: Matthew Brost
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_cont
w
function will internally be added to the first present RCS or CCS
engine's workaround list to ensure they get applied (and only get
applied once rather than being needlessly re-applied several times).
Co-author: Srinivasan Shanmugam
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/inte
From: Daniele Ceraolo Spurio
Tell GuC that CCS is enabled by setting a bit in its ADS.
Cc: Vinay Belgaumkar
Original-author: Michel Thierry
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h| 3 +++
drivers/gpu/drm/i915/gt/uc
already fully
saturate the HW, so consider it fused off.
v2(José):
- moved it to its own function
- fixed definition of ccs_mask
Cc: Stuart Summers
Cc: Vinay Belgaumkar
Cc: Ashutosh Dixit
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers
45544
Original-author: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Signed-off-by: Rodrigo Vivi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin #v1
---
drivers/gpu/drm/i915/gt/inte
and CCS3 are in a new one.
BSpec: 50844, 54029, 54030, 53223, 53224.
Original-author: Michel Thierry
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915
-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3190b7b462a9..3150c0847f65 100644
--- a/drivers/gpu
damsetty
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm
: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17
bits must not be set
Bspec: 47112
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 35 +++-
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 +
2
ed out.
Daniele Ceraolo Spurio (3):
drm/i915/xehp: compute engine pipe_control
drm/i915/xehp/guc: enable compute engine inside GuC
drm/i915/xehp: handle fused off CCS engines
Matt Roper (8):
drm/i915/xehp: Define compute class and engine
drm/i915/xehp: CCS shares the render reset domain
On Thu, Feb 10, 2022 at 10:36:36AM -0800, Michael Cheng wrote:
> Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
> This will prevent compile errors on non-x86 platforms.
>
> Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
> ---
> drive
e ordering of clflush wrt to the system.
>*/
> if (flushes & CLFLUSH_AFTER)
> - clflushopt(addr);
> + drm_clflush_virt_range(addr, sizeof(addr));
Ditto.
Aside from those,
Reviewed-by: Matt Roper
> } else
>
64 depending on architecture). Not that it will really
change the behavior since it all works out to a single cacheline in the
end.
Aside from that,
Reviewed-by: Matt Roper
>
> inactive = process_csb(engine, inactive); /* drain preemption events */
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
ssues a clflush for the first and last entries
rather than the range from 0..reset_value, but since there are only a
maximum of 12 u64 entries, which fits into two cachelines, the end
result should be the same either way.
Reviewed-by: Matt Roper
>
> /* Once more for luck and our trusty paranoia */
> ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
this function is only used from a selftest, not
from real driver codepaths, so the extra flushing shouldn't have any
negative impact on end users.
Reviewed-by: Matt Roper
> Signed-off-by: Michael Cheng
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
> 1 file
g., I think a lot of these were based
on feedback from Tvrtko?
>
> Signed-off-by: Michael Cheng
Change appears to accurately implement the same type of cache flush as
what we have on the x86 backend.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/drm_cache.c | 6 ++
> 1 file changed,
the only places we're using
that value are the programming of BLIT_CCTL (bspec 45807) and
RING_CMD_CCTL (bspec 45826), both of which are supposed to be using
GO:Memory instead of GO:L3. So maybe we should fix the uc_index value
for those platforms and then use "rq->engine->gt->mocs.uc_index << 1"
here. Might be worth renaming the field to "uc_index_gomemory" just to
make it more explicit what it's representing to prevent mistakes during
enablement of future platforms.
Matt
> + cs = i915_flush_dw(cs, offset, MI_FLUSH_LLC | MI_FLUSH_CCS);
> +
> + if (ccs_ring_size & 1)
> + *cs++ = MI_NOOP;
> + }
> intel_ring_advance(rq, cs);
> return 0;
> }
> @@ -711,7 +848,7 @@ intel_context_migrate_clear(struct intel_context *ce,
> if (err)
> goto out_rq;
>
> - err = emit_clear(rq, offset, len, value);
> + err = emit_clear(rq, offset, len, value, is_lmem);
>
> /* Arbitration is re-enabled between requests. */
> out_rq:
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
TC1 in the intel_setup_outputs() function. I
think I previously had that in a separate patch, but it went missing
when we reorganized and refactored some of these patches
Matt
On Tue, Feb 15, 2022 at 11:21:52AM +0530, Ramalingam C wrote:
> From: Matt Roper
>
> DG2 supports a 5th displ
jälä ; Shankar, Uma
> > ; Roper, Matthew D ;
> > Dhanavanthri, Swathi ; De Marchi, Lucas
> > ; Souza, Jose ; C,
> > Ramalingam
> >
> > Subject: [PATCH 1/3] drm/i915/dg2: Enable 5th display
> >
> > From: Matt Roper
> >
> > DG2 supports a 5th
On Tue, Feb 15, 2022 at 06:58:17PM -0800, Vinay Belgaumkar wrote:
> This will ensure correct values for Gen12+ platforms.
>
> Cc: Matt Roper
> Signed-off-by: Vinay Belgaumkar
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 5 +++--
&g
On Wed, Jan 26, 2022 at 01:39:43AM -0800, Lucas De Marchi wrote:
> Remove the local yesno() implementation and adopt the str_yes_no() from
> linux/string_helpers.h.
>
> Signed-off-by: Lucas De Marchi
> Acked-by: Daniel Vetter
> Acked-by: Jani Nikula
Reviewed-by: Matt Roper
re's an open-coded version of this in display/intel_pps.c,
intel_pps_backlight_power(). Up to you whether you squash it into this
patch or convert it as a follow-up. Either way.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
&g
e's two open-coded versions of this in intel_dp_hdcp.c
(intel_dp_mst_hdcp_stream_encryption() and
intel_dp_mst_hdcp2_stream_encryption()) that you might want to convert
as well. Up to you whether you squash them into this patch or convert
them as a separate patch. Either way,
On Wed, Jan 26, 2022 at 01:39:46AM -0800, Lucas De Marchi wrote:
> Remove the local onoff() implementation and adopt the
> str_on_off() from linux/string_helpers.h.
>
> Signed-off-by: Lucas De Marchi
> Acked-by: Daniel Vetter
> Acked-by: Jani Nikula
Reviewed-by: Matt Roper
z|it points to gt0/
> ├── gt_RP0_freq_mhz|
> └── gt_RP1_freq_mhz|
> └── gt_RPn_freq_mhz -+
>
> Signed-off-by: Andi Shyti
> Signed-off-by: Lucas De Marchi
> Cc: Matt Roper
> Cc: Sujaritha Sundaresan
> Cc: Tvrtko Ursulin
Eve
is initialized for now; the other
> tiles will be detected and plugged in by future patches once the
> necessary infrastructure is in place to handle them.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Tvrtko Ursulin
> Signed
difference is that in i915_perf.c I'm using
>
> to_gt(perf->i915)
>
> instead of
>
> to_gt(perf->i915)->ggtt->vm.gt
>
Reviewed-by: Matt Roper
> Andi
>
> drivers/gpu/drm/i915/gvt/dmabuf.c| 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-
o_gt(perf->i915)
>
> if two GTs are sharing the same ggtt, what would the ggtt->vm.gt
> link be?
>From the git history, it doesn't look like this really needs to care
about the GGTT at all; I think it was just unintentionally written in a
roundabout manner when intel_gt w
128315aec517 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream
> *stream)
> struct drm_i915_gem_object *bo;
> struct i915_vma *vma;
> const u64 delay_ti
th the future
> refactoring.
>
> Signed-off-by: Michał Winiarski
> Cc: Michal Wajdeczko
> Signed-off-by: Andi Shyti
> Reviewed-by: Sujaritha Sundaresan
> Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++---
> drivers/gp
rastructure).
Otherwise,
Reviewed-by: Matt Roper
Matt
>
> Suggested-by: Matt Roper
> Signed-off-by: Andi Shyti
> Cc: Michał Winiarski
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c| 7 +--
> drivers/gpu/drm/i915/gt/intel_gt.h| 2 +-
>
value = i915->ggtt.num_fences;
> + value = to_gt(i915)->ggtt->num_fences;
> break;
> case I915_PARAM_HAS_OVERLAY:
> value = !!i915->overlay;
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 170bba913c30..128315aec517 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1630,7 +1630,7 @@ static int alloc_noa_wait(struct i915_perf_stream
> *stream)
> struct drm_i915_gem_object *bo;
> struct i915_vma *vma;
> const u64 delay_ticks = 0x -
> - intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
> +
> intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915)->ggtt->vm.gt,
>
> atomic64_read(&stream->perf->noa_programming_delay));
> const u32 base = stream->engine->mmio_base;
> #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> @@ -3542,7 +3542,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>
> static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> {
> - return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
> + return intel_gt_clock_interval_to_ns(to_gt(perf->i915)->ggtt->vm.gt,
>2ULL << exponent);
> }
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
th the future
> refactoring.
>
> Signed-off-by: Michał Winiarski
> Cc: Michal Wajdeczko
> Signed-off-by: Andi Shyti
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/selftests/i915_gem.c| 8
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c| 6 +++-
th the future
> refactoring.
>
> Signed-off-by: Michał Winiarski
> Cc: Michal Wajdeczko
> Signed-off-by: Andi Shyti
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +++---
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 6 ++
th the future
> refactoring.
>
> Signed-off-by: Michał Winiarski
> Cc: Michal Wajdeczko
> Signed-off-by: Andi Shyti
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
&g
th the future
> refactoring.
>
> Signed-off-by: Michał Winiarski
> Cc: Michal Wajdeczko
> Signed-off-by: Andi Shyti
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +-
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
&g
y: Andi Shyti
> Cc: Michal Wajdeczko
> Cc: Matt Roper
> ---
...
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 14216cc471b1..02fc7641b82e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/driver
ise_ggtt(struct drm_i915_private *i915,
>u64 hole_start, u64 hole_end,
>unsigned long end_time))
> {
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> u64 hole_start, hole_end, last = 0;
> struct drm_mm_node *node;
> IGT_TIMEOUT(end_time);
> @@ -1182,7 +1182,7 @@ static int igt_ggtt_page(void *arg)
> const unsigned int count = PAGE_SIZE/sizeof(u32);
> I915_RND_STATE(prng);
> struct drm_i915_private *i915 = arg;
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct drm_i915_gem_object *obj;
> intel_wakeref_t wakeref;
> struct drm_mm_node tmp;
> @@ -2110,7 +2110,7 @@ int i915_gem_gtt_live_selftests(struct drm_i915_private
> *i915)
> SUBTEST(igt_cs_tlb),
> };
>
> - GEM_BUG_ON(offset_in_page(i915->ggtt.vm.total));
> + GEM_BUG_ON(offset_in_page(to_gt(i915)->ggtt->vm.total));
>
> return i915_subtests(tests, i915);
> }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
> b/drivers/gpu/drm/i915/selftests/i915_request.c
> index 92a859b34190..7f66f6d299b2 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
> @@ -843,7 +843,7 @@ static struct i915_vma *empty_batch(struct
> drm_i915_private *i915)
>
> intel_gt_chipset_flush(to_gt(i915));
>
> - vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> + vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
> if (IS_ERR(vma)) {
> err = PTR_ERR(vma);
> goto err;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
> b/drivers/gpu/drm/i915/selftests/i915_vma.c
> index 1f10fe36619b..6ac15d3bc5bc 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_vma.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
> @@ -967,7 +967,7 @@ static int igt_vma_remapped_gtt(void *arg)
> intel_wakeref_t wakeref;
> int err = 0;
>
> - if (!i915_ggtt_has_aperture(&i915->ggtt))
> + if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
> return 0;
>
> obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 8aa7b1d33865..2f12f8748262 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -69,7 +69,7 @@ static void mock_device_release(struct drm_device *dev)
> i915_gem_drain_workqueue(i915);
> i915_gem_drain_freed_objects(i915);
>
> - mock_fini_ggtt(&i915->ggtt);
> + mock_fini_ggtt(to_gt(i915)->ggtt);
> destroy_workqueue(i915->wq);
>
> intel_region_ttm_device_fini(i915);
> @@ -195,7 +195,7 @@ struct drm_i915_private *mock_gem_device(void)
> mock_init_contexts(i915);
>
> mock_init_ggtt(i915, &i915->ggtt);
> - to_gt(i915)->vm = i915_vm_get(&i915->ggtt.vm);
> + to_gt(i915)->vm = i915_vm_get(&to_gt(i915)->ggtt->vm);
>
> mkwrite_device_info(i915)->platform_engine_mask = BIT(0);
> to_gt(i915)->info.engine_mask = BIT(0);
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c
> b/drivers/gpu/drm/i915/selftests/mock_gtt.c
> index 13bb0c3c3f0d..82867424d203 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
> @@ -132,7 +132,7 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct
> i915_ggtt *ggtt)
> ggtt->vm.vma_ops.clear_pages = clear_pages;
>
> i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
> - to_gt(i915)->ggtt = ggtt;
> + intel_gt_init_hw_early(to_gt(i915), ggtt);
> }
>
> void mock_fini_ggtt(struct i915_ggtt *ggtt)
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
On Fri, Dec 10, 2021 at 03:07:56AM +0200, Andi Shyti wrote:
> Use to_gt() helper consistently throughout the codebase.
> Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
>
> Signed-off-by: Andi Shyti
Reviewed-by: Matt Roper
> ---
> Hi,
>
> the inli
e here intentional? It doesn't seem like there's
> > any reason to drop it, and if it was intentional the whitespace isn't
> > quite right.
>
> No, it wasn't intentional and it's strange that checkpatch
> didn't catch it. I will resend this on
i
> Cc: Rodrigo Vivi
> Cc: Tvrtko Ursulin
Reviewed-by: Matt Roper
If you decide to not drop i915->ggtt completely in the previous patch,
we might want to make a simimlar naming change to that field as well.
Matt
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> 1 fil
unsigned int count = PAGE_SIZE/sizeof(u32);
> I915_RND_STATE(prng);
> struct drm_i915_private *i915 = arg;
> - struct i915_ggtt *ggtt = &i915->ggtt;
> + struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> struct drm_i915_gem_object *obj;
> intel_wakeref_t wakeref;
> struct drm_mm_node tmp;
> @@ -2110,7 +2110,7 @@ int i915_gem_gtt_live_selftests(struct drm_i915_private
> *i915)
> SUBTEST(igt_cs_tlb),
> };
>
> - GEM_BUG_ON(offset_in_page(i915->ggtt.vm.total));
> + GEM_BUG_ON(offset_in_page(to_gt(i915)->ggtt->vm.total));
>
> return i915_subtests(tests, i915);
> }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
> b/drivers/gpu/drm/i915/selftests/i915_request.c
> index 92a859b34190..7f66f6d299b2 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
> @@ -843,7 +843,7 @@ static struct i915_vma *empty_batch(struct
> drm_i915_private *i915)
>
> intel_gt_chipset_flush(to_gt(i915));
>
> - vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> + vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
> if (IS_ERR(vma)) {
> err = PTR_ERR(vma);
> goto err;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
> b/drivers/gpu/drm/i915/selftests/i915_vma.c
> index 1f10fe36619b..6ac15d3bc5bc 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_vma.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
> @@ -967,7 +967,7 @@ static int igt_vma_remapped_gtt(void *arg)
> intel_wakeref_t wakeref;
> int err = 0;
>
> - if (!i915_ggtt_has_aperture(&i915->ggtt))
> + if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
> return 0;
>
> obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 8aa7b1d33865..2f12f8748262 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -69,7 +69,7 @@ static void mock_device_release(struct drm_device *dev)
> i915_gem_drain_workqueue(i915);
> i915_gem_drain_freed_objects(i915);
>
> - mock_fini_ggtt(&i915->ggtt);
> + mock_fini_ggtt(to_gt(i915)->ggtt);
> destroy_workqueue(i915->wq);
>
> intel_region_ttm_device_fini(i915);
> @@ -195,7 +195,7 @@ struct drm_i915_private *mock_gem_device(void)
> mock_init_contexts(i915);
>
> mock_init_ggtt(i915, &i915->ggtt);
> - to_gt(i915)->vm = i915_vm_get(&i915->ggtt.vm);
> + to_gt(i915)->vm = i915_vm_get(&to_gt(i915)->ggtt->vm);
>
> mkwrite_device_info(i915)->platform_engine_mask = BIT(0);
> to_gt(i915)->info.engine_mask = BIT(0);
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c
> b/drivers/gpu/drm/i915/selftests/mock_gtt.c
> index f0b87de0aca3..41fae5c9ea34 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
> @@ -130,7 +130,7 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct
> i915_ggtt *ggtt)
> ggtt->vm.vma_ops.clear_pages = clear_pages;
>
> i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
> - to_gt(i915)->ggtt = ggtt;
> + intel_gt_init_hw_early(to_gt(i915), ggtt);
> }
>
> void mock_fini_ggtt(struct i915_ggtt *ggtt)
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
boost_frequency(rps));
> }
> @@ -287,7 +287,7 @@ static ssize_t gt_boost_freq_mhz_store(struct device
> *kdev,
> const char *buf, size_t count)
> {
> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> - struct intel_rps *rps = &dev_priv->gt.rps;
> + struct intel_rps *rps = &to_gt(dev_priv)->rps;
> ssize_t ret;
> u32 val;
>
> @@ -304,7 +304,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
>struct device_attribute *attr, char *buf)
> {
> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> - struct intel_rps *rps = &dev_priv->gt.rps;
> + struct intel_rps *rps = &to_gt(dev_priv)->rps;
>
> return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps,
> rps->efficient_freq));
> }
> @@ -312,7 +312,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
> static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct
> device_attribute *attr, char *buf)
> {
> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> - struct intel_gt *gt = &dev_priv->gt;
> + struct intel_gt *gt = to_gt(dev_priv);
> struct intel_rps *rps = >->rps;
>
> return sysfs_emit(buf, "%d\n", intel_rps_get_max_frequency(rps));
> @@ -323,7 +323,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
>const char *buf, size_t count)
> {
> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> - struct intel_gt *gt = &dev_priv->gt;
> + struct intel_gt *gt = to_gt(dev_priv);
> struct intel_rps *rps = >->rps;
> ssize_t ret;
> u32 val;
> @@ -340,7 +340,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
> static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct
> device_attribute *attr, char *buf)
> {
> struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
> - struct intel_gt *gt = &i915->gt;
> + struct intel_gt *gt = to_gt(i915);
> struct intel_rps *rps = >->rps;
>
> return sysfs_emit(buf, "%d\n", intel_rps_get_min_frequency(rps));
> @@ -351,7 +351,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
>const char *buf, size_t count)
> {
> struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
> - struct intel_rps *rps = &i915->gt.rps;
> + struct intel_rps *rps = &to_gt(i915)->rps;
> ssize_t ret;
> u32 val;
>
> @@ -381,7 +381,7 @@ static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO,
> gt_rp_mhz_show, NULL);
> static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute
> *attr, char *buf)
> {
> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> - struct intel_rps *rps = &dev_priv->gt.rps;
> + struct intel_rps *rps = &to_gt(dev_priv)->rps;
> u32 val;
>
> if (attr == &dev_attr_gt_RP0_freq_mhz)
> diff --git a/drivers/gpu/drm/i915/intel_gvt.c
> b/drivers/gpu/drm/i915/intel_gvt.c
> index 4e70c1a9ef2e..cf6e98962d82 100644
> --- a/drivers/gpu/drm/i915/intel_gvt.c
> +++ b/drivers/gpu/drm/i915/intel_gvt.c
> @@ -109,7 +109,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> - if (intel_uc_wants_guc_submission(&dev_priv->gt.uc)) {
> + if (intel_uc_wants_guc_submission(&to_gt(dev_priv)->uc)) {
> drm_err(&dev_priv->drm,
> "i915 GVT-g loading failed due to Graphics
> virtualization is not yet supported with GuC submission\n");
> return -EIO;
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
> b/drivers/gpu/drm/i915/intel_wopcm.c
> index 5e511bb891f9..f06d21005106 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -220,7 +220,7 @@ static bool __wopcm_regs_locked(struct intel_uncore
> *uncore,
> void intel_wopcm_init(struct intel_wopcm *wopcm)
> {
> struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
> - struct intel_gt *gt = &i915->gt;
> + struct intel_gt *gt = to_gt(i915);
> u32 guc_fw_size = intel_uc_fw_get_upload_size(>->uc.guc.fw);
> u32 huc_fw_size = intel_uc_fw_get_upload_size(>->uc.huc.fw);
> u32 ctx_rsvd = context_reserved_size(i915);
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
o_i915(i915_kdev);
> +
> + return &to_gt(i915)->pxp;
> }
>
> static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
On Thu, Dec 09, 2021 at 03:25:08PM +0200, Andi Shyti wrote:
> Use to_gt() helper consistently throughout the codebase.
> Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
>
> Signed-off-by: Andi Shyti
> Cc: Michał Winiarski
Reviewed-by: Matt Roper
> ---
&g
> - ppgtt = i915_ppgtt_create(&i915->gt, I915_BO_ALLOC_PM_EARLY);
> + ppgtt = i915_ppgtt_create(to_gt(i915), I915_BO_ALLOC_PM_EARLY);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
gt_pm_get(to_gt(i915));
> + cancel_delayed_work_sync(&to_gt(i915)->requests.retire_work);
> }
>
> static void restore_retire_worker(struct drm_i915_private *i915)
> {
> igt_flush_test(i915);
> - intel_gt_pm_put(&i915->gt);
> + intel_gt_pm_put(to_gt(i915));
>
i915_private *i915)
> SUBTEST(live_engine_reset_workarounds),
> };
>
> - if (intel_gt_is_wedged(&i915->gt))
> + if (intel_gt_is_wedged(to_gt(i915)))
> return 0;
>
> - return intel_gt_live_subtests(tests, &i915->gt);
> + return intel_gt_live_subtests(tests, to_gt(i915));
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 22c1c12369f2..13b27b8ff74e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -623,7 +623,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> if (unlikely(ret < 0))
> return ret;
>
> - intel_guc_pm_intrmsk_enable(&i915->gt);
> + intel_guc_pm_intrmsk_enable(to_gt(i915));
>
> slpc_get_rp_values(slpc);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> index fb0e4a7bd8ca..e8cd030137e5 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> @@ -115,7 +115,7 @@ int intel_guc_live_selftests(struct drm_i915_private
> *i915)
> static const struct i915_subtest tests[] = {
> SUBTEST(intel_guc_scrub_ctbs),
> };
> - struct intel_gt *gt = &i915->gt;
> + struct intel_gt *gt = to_gt(i915);
>
> if (intel_gt_is_wedged(gt))
> return 0;
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> index 50953c8e8b53..1297ddbf7f88 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> @@ -167,7 +167,7 @@ int intel_guc_multi_lrc_live_selftests(struct
> drm_i915_private *i915)
> static const struct i915_subtest tests[] = {
> SUBTEST(intel_guc_multi_lrc_basic),
> };
> - struct intel_gt *gt = &i915->gt;
> + struct intel_gt *gt = to_gt(i915);
>
> if (intel_gt_is_wedged(gt))
> return 0;
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
501 - 600 of 1038 matches
Mail list logo
