[PATCH 5/5] drm/msm/A6xx: Add support for using system cache(llc)

h from it. Similarly DOMAIN_ATTR_USE_UPSTREAM_HINT is another domain level attribute used by the IOMMU driver to set the right attributes to cache the hardware pagetables into the system cache. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/m

[PATCH 3/5] drm/msm/adreno: Add registers in the GPU CX domain

Add the registers needed for configuring the system cache slice info and other parameters in the GPU. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xm

[PATCH 0/5] Adreno A6xx system cache support

soon by Vivek. Sharat Masetty (5): drm/msm: rearrange the gpu_rmw() function arm64:dts:sdm845: Add support for GPU LLCC drm/msm/adreno: Add registers in the GPU CX domain drm/msm: Pass mmu features to generic layers drm/msm/A6xx: Add support for using system cache(llc) arch/arm64/boot

[PATCH 1/5] drm/msm: rearrange the gpu_rmw() function

The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_drv

[PATCH 2/5] arm64:dts:sdm845: Add support for GPU LLCC

Add client side bindings required for the GPU to use the last level system cache. Also add a register range in the GPU CX domain. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-)

[PATCH 4/5] drm/msm: Pass mmu features to generic layers

supports. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/

[PATCH 3/6] drm/msm/A6xx: Implement preemption for A6XX targets

-call level or a bin boundary level preemption. This patch enables the basic preemption level, with more fine grained preemption support to follow. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx

[PATCH 5/6] drm/msm/Adreno: Refactor some preemption code

The preemption state machine related code is same across Adreno targets, so move the common code to a common header file to avoid code duplication. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 26 --- drivers/gpu/d

[PATCH 4/6] drm/msm/A6xx: Enable preemption for A6xx targets

This patch simply increases the number of available ringbuffers, therefore enabling preemption. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/

[PATCH 1/6] drm/msm: Add submitqueue setup and close

This patch adds a bit of infrastructure to give the different Adreno targets the flexibility to setup the submitqueues per their needs. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.h | 7 +++ drivers/gpu/drm/msm/msm_submitqueue.

[PATCH 6/6] drm/msm/A6xx: Enable L1 preemption level

This patch enables L1 level which is a finer grained preemption at either a draw call or a bin boundary. The worst case switching latency is higher in this case but that is a trade off we make for enabling faster preemption. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drive

[PATCH 2/6] drm/msm: Add new PM4 type7 opcodes

-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index fb605a3..f0fd80e 100644 --- a/drivers/gpu/d

[PATCH 0/6] Preemption support for A6xx targets

evels each with different granularities and different switch-out-switch-in times. This series starts off by adding basic preemption support for A6xx targets, leading up to the tip of the stack which enables L1 level preemption. This is a more fine grained version and faster than the default leve

[PATCH] rnndb/adreno: Add more PM4 opcodes

Add CP_SECURE_MODE and CP_SET_PSEUDO_REG opcodes needed for A6xx hardware features. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- rnndb/adreno/adreno_pm4.xml | 5 + 1 file changed, 5 insertions(+) diff --git a/rnndb/adreno/adreno_pm4.xml b/rnndb/adreno/adreno_pm4.xml

[PATCH 3/4] drm/msm/A6xx: Implement preemption for A6XX targets

-call level or a bin boundary level preemption. This patch enables the basic preemption level, with more fine grained preemption support to follow. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx

[PATCH 4/4] drm/msm/A6xx: Enable preemption for A6xx targets

This patch simply increases the number of available ringbuffers, therefore enabling preemption. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/

[PATCH 2/4] drm/msm: Add new PM4 type7 opcodes

-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index fb605a3..f0fd80e 100644 --- a/drivers/gpu/d

[PATCH 1/4] drm/msm: Add submitqueue setup and close

This patch adds a bit of infrastructure to give the different Adreno targets the flexibility to setup the submitqueues per their needs. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.h | 7 +++ drivers/gpu/drm/msm/msm_submitqueue.

[PATCH 0/4] Preemption support for A6xx targets

vels, each with different granularities and different switch-out--switch-in times. While this patch only enables the first preemption level i.e. preemption at the ringbuffer level, support for more finer grained preemption levels will follow after more testing. Sharat Masetty (4): drm/msm: Add submitq

[PATCH] drm/msm: Memory leak bug fix

This patch fixes a possible memory leak in get_pages() Prakash Kamliya (1): drm/msm: fix leak in failed get_pages drivers/gpu/drm/msm/msm_gem.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) -- 1.9.1 ___ dri-devel mailing

[PATCH] drm/msm: fix leak in failed get_pages

leanup. Signed-off-by: Prakash Kamliya <pkaml...@codeaurora.org> Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gem.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/m

[PATCH] drm/msm: fix leak in failed get_pages

leanup. Signed-off-by: Prakash Kamliya <pkaml...@codeaurora.org> Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gem.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/m

[PATCH] drm/msm: Memory leak bug fix

This patch fixes a possible memory leak in get_pages() Prakash Kamliya (1): drm/msm: fix leak in failed get_pages drivers/gpu/drm/msm/msm_gem.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) -- 1.9.1 ___ dri-devel mailing

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