8c835cabb192f6b6e0a4a5f6660 Mon Sep 17 00:00:00 2001
> From: Keith Packard
> Date: Mon, 22 Jul 2013 18:12:28 -0700
> Subject: [PATCH 4/5] drm/i915: Add async page flip support for IVB
>
> This adds the necesary register defines for async page flipping
> through the command ring, and
> Generally I think checking our current sw state instead of reading hw
> registers would be safer, e.g. in case we start to queue up more than
> one pageflip. For async pageflips in benchmark mode "flip as fast as
> you can queue" would be a sensible mode.
Ok, I've moved the tiling checks to the
Daniel Vetter writes:
> On Wed, Jul 24, 2013 at 06:40:16PM -0700, Keith Packard wrote:
>> Daniel Vetter writes:
>>
>> > We could just unconditionally increase the alignement in
>> > intel_pin_and_fence_fb_obj - we already have more strict requirements due
>> > to a bunch of w/a in other
On Wed, Jul 24, 2013 at 06:40:16PM -0700, Keith Packard wrote:
> Daniel Vetter writes:
>
> > We could just unconditionally increase the alignement in
> > intel_pin_and_fence_fb_obj - we already have more strict requirements due
> > to a bunch of w/a in other places. So shouldn't hurt at all
On Wed, Jul 24, 2013 at 01:26:32PM -0700, Keith Packard wrote:
> Daniel Vetter writes:
>
> > Matching tiling modes is actually already a requirement on gen4+ (since
> > the tiling bit and the linear/tiled offset registers can't be changed with
> > a MI_DISPLAY_FLIP command).
>
> Async flip has
On Wed, Jul 24, 2013 at 06:40:16PM -0700, Keith Packard wrote:
Daniel Vetter dan...@ffwll.ch writes:
We could just unconditionally increase the alignement in
intel_pin_and_fence_fb_obj - we already have more strict requirements due
to a bunch of w/a in other places. So shouldn't hurt at
for patch #4 that just adds the alignment
requirement there. Do you want any other changes in this series?
From 9a51e7118fce58c835cabb192f6b6e0a4a5f6660 Mon Sep 17 00:00:00 2001
From: Keith Packard kei...@keithp.com
Date: Mon, 22 Jul 2013 18:12:28 -0700
Subject: [PATCH 4/5] drm/i915: Add async page
: [PATCH 4/5] drm/i915: Add async page flip support for IVB
This adds the necesary register defines for async page flipping
through the command ring, and then hooks those up for Ivybridge (gen7)
page flipping.
Signed-off-by: Keith Packard kei...@keithp.com
---
drivers/gpu/drm/i915/i915_reg.h
Generally I think checking our current sw state instead of reading hw
registers would be safer, e.g. in case we start to queue up more than
one pageflip. For async pageflips in benchmark mode flip as fast as
you can queue would be a sensible mode.
Ok, I've moved the tiling checks to the
Daniel Vetter writes:
> We could just unconditionally increase the alignement in
> intel_pin_and_fence_fb_obj - we already have more strict requirements due
> to a bunch of w/a in other places. So shouldn't hurt at all really.
That seems like a fine plan; 32kB isn't that onerous. Do you want
Daniel Vetter writes:
> Matching tiling modes is actually already a requirement on gen4+ (since
> the tiling bit and the linear/tiled offset registers can't be changed with
> a MI_DISPLAY_FLIP command).
Async flip has a harder requirement -- you must use X tiling, both
before and after the
Daniel Vetter dan...@ffwll.ch writes:
Matching tiling modes is actually already a requirement on gen4+ (since
the tiling bit and the linear/tiled offset registers can't be changed with
a MI_DISPLAY_FLIP command).
Async flip has a harder requirement -- you must use X tiling, both
before and
Daniel Vetter dan...@ffwll.ch writes:
We could just unconditionally increase the alignement in
intel_pin_and_fence_fb_obj - we already have more strict requirements due
to a bunch of w/a in other places. So shouldn't hurt at all really.
That seems like a fine plan; 32kB isn't that onerous. Do
On Mon, Jul 22, 2013 at 06:50:01PM -0700, Keith Packard wrote:
> This adds the necesary register defines for async page flipping
> through the command ring, and then hooks those up for Ivybridge (gen7)
> page flipping.
>
> Signed-off-by: Keith Packard
> ---
> drivers/gpu/drm/i915/i915_reg.h
On Mon, Jul 22, 2013 at 06:50:01PM -0700, Keith Packard wrote:
This adds the necesary register defines for async page flipping
through the command ring, and then hooks those up for Ivybridge (gen7)
page flipping.
Signed-off-by: Keith Packard kei...@keithp.com
---
This adds the necesary register defines for async page flipping
through the command ring, and then hooks those up for Ivybridge (gen7)
page flipping.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 40
This adds the necesary register defines for async page flipping
through the command ring, and then hooks those up for Ivybridge (gen7)
page flipping.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/i915_reg.h | 6 +
drivers/gpu/drm/i915/intel_display.c | 46
This adds the necesary register defines for async page flipping
through the command ring, and then hooks those up for Ivybridge (gen7)
page flipping.
Signed-off-by: Keith Packard kei...@keithp.com
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 40
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