Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Sanitycheck MMIO access early in driver load

2023-03-22 Thread Andrzej Hajda
On 21.03.2023 23:43, Andi Shyti wrote: Hi Matt, We occasionally see the PCI device in a non-accessible state at the point the driver is loaded. When this happens, all BAR accesses will read back as 0x. Rather than reading registers and misinterpreting their (invalid) values, let's

Re: [PATCH v2 1/2] drm/i915: Sanitycheck MMIO access early in driver load

2023-03-21 Thread Andi Shyti
Hi Matt, > > We occasionally see the PCI device in a non-accessible state at the > > point the driver is loaded. When this happens, all BAR accesses will > > read back as 0x. Rather than reading registers and > > misinterpreting their (invalid) values, let's specifically check for > >

Re: [PATCH v2 1/2] drm/i915: Sanitycheck MMIO access early in driver load

2023-03-21 Thread Matt Roper
On Tue, Mar 21, 2023 at 06:09:35PM +0100, Andi Shyti wrote: > From: Matt Roper > > We occasionally see the PCI device in a non-accessible state at the > point the driver is loaded. When this happens, all BAR accesses will > read back as 0x. Rather than reading registers and >

Re: [PATCH v2 1/2] drm/i915: Sanitycheck MMIO access early in driver load

2023-03-21 Thread Andi Shyti
> We occasionally see the PCI device in a non-accessible state at the > point the driver is loaded. When this happens, all BAR accesses will > read back as 0x. Rather than reading registers and > misinterpreting their (invalid) values, let's specifically check for > 0x in a

[PATCH v2 1/2] drm/i915: Sanitycheck MMIO access early in driver load

2023-03-21 Thread Andi Shyti
From: Matt Roper We occasionally see the PCI device in a non-accessible state at the point the driver is loaded. When this happens, all BAR accesses will read back as 0x. Rather than reading registers and misinterpreting their (invalid) values, let's specifically check for 0x