[PATCH v6 08/15] drm/exynos: dsi: rename pll_clk to sclk_clk

2015-06-22 Thread Inki Dae
+ Samsung SoC mailing list. On 2015년 06월 12일 21:59, Hyungwon Hwang wrote: > This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk > is actually not the pll input clock for dsi. The pll input clock comes > from the board's oscillator directly. But for the backward >

[PATCH v6 08/15] drm/exynos: dsi: rename pll_clk to sclk_clk

2015-06-12 Thread Hyungwon Hwang
This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk is actually not the pll input clock for dsi. The pll input clock comes from the board's oscillator directly. But for the backward compatibility, the old clock name "pll_clk" is also OK. Signed-off-by: Hyungwon Hwang ---