On Tue, 14 Dec 2010 12:09:49 -0800, "Segovia, Benjamin" wrote:
> Perfect. It is still a good temporary solution. For coherency, my goal is top
> ensure it without the need of MI_FLUSH or pipe control. So, EUs must be able
> to do it themselves
> For ILK
> * on CPU, I used _mm_clflush (as the
On Tue, 14 Dec 2010 12:09:49 -0800, Segovia, Benjamin
benjamin.sego...@intel.com wrote:
Perfect. It is still a good temporary solution. For coherency, my goal is top
ensure it without the need of MI_FLUSH or pipe control. So, EUs must be able
to do it themselves
For ILK
* on CPU, I used
.uk]
Sent: Tuesday, December 14, 2010 2:00 AM
To: Segovia, Benjamin; Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
On Mon, 13 Dec 2010 20:32:42 -0800, "Segovia, Benjamin" wrote:
> To be more explicit, my concern is that I read that Chris Wilson pro
using surface
descriptors.
Cheers,
Ben
From: Chris Wilson [ch...@chris-wilson.co.uk]
Sent: Tuesday, December 14, 2010 2:59 AM
To: Segovia, Benjamin; Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
On Mon, 13 Dec 2010 20:32:42
On Mon, 13 Dec 2010 20:32:42 -0800, "Segovia, Benjamin" wrote:
> To be more explicit, my concern is that I read that Chris Wilson proposed a
> patch preventing the VM to swap pages still in GTT. I did not see any trace
> of this patch in the main line yet.
No, because the mm maintainers
On Mon, 13 Dec 2010 20:32:42 -0800, Segovia, Benjamin
benjamin.sego...@intel.com wrote:
To be more explicit, my concern is that I read that Chris Wilson proposed a
patch preventing the VM to swap pages still in GTT. I did not see any trace
of this patch in the main line yet.
No, because
using surface
descriptors.
Cheers,
Ben
From: Chris Wilson [ch...@chris-wilson.co.uk]
Sent: Tuesday, December 14, 2010 2:59 AM
To: Segovia, Benjamin; Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
On Mon, 13 Dec 2010 20:32:42
]
Sent: Tuesday, December 14, 2010 2:00 AM
To: Segovia, Benjamin; Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
On Mon, 13 Dec 2010 20:32:42 -0800, Segovia, Benjamin
benjamin.sego...@intel.com wrote:
To be more explicit, my concern is that I read that Chris Wilson
and mapped in user space, my buffer can be safely used by
both CPUs and GPUs and that the VM will never swap it?
Ben
Original Message-
From: Segovia, Benjamin
Sent: Monday, December 13, 2010 8:20 PM
To: Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
I have been
, December 10, 2010 8:15 PM
To: Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
Thanks for the answer
I actually have no a rather simple prototype doing shared memory between CPU
and GPU. Basically:
1/ I create a buffer B
2/ I map B and get a pointer to it
3/ I exec a batch buffer with B
, December 10, 2010 8:15 PM
To: Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
Thanks for the answer
I actually have no a rather simple prototype doing shared memory between CPU
and GPU. Basically:
1/ I create a buffer B
2/ I map B and get a pointer to it
3/ I exec a batch buffer with B
functions. However, I am not sure I can get symbols from i915 properly. Is a
i915 patch the only solution?
Cheers,
Ben
From: Zhenyu Wang [zhen...@linux.intel.com]
Sent: Monday, December 06, 2010 11:00 PM
To: Segovia, Benjamin
Cc: DRI
Subject: Re: Intel DRM
functions. However, I am not sure I can get symbols from i915 properly. Is a
i915 patch the only solution?
Cheers,
Ben
From: Zhenyu Wang [zhen...@linux.intel.com]
Sent: Monday, December 06, 2010 11:00 PM
To: Segovia, Benjamin
Cc: DRI
Subject: Re: Intel DRM
On 2010.12.06 15:18:02 -0800, Segovia, Benjamin wrote:
> Hello all,
> is the kernel driver configured to support reads/writes to LLC (last level
> cache i.e. L3) on SNB?
Now it's under limited use for the buffer that is sure to be cached,
e.g hw status page, etc. code lives in
Hello all,
is the kernel driver configured to support reads/writes to LLC (last level
cache i.e. L3) on SNB?
Cheers,
Ben
Hello all,
is the kernel driver configured to support reads/writes to LLC (last level
cache i.e. L3) on SNB?
Cheers,
Ben
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On 2010.12.06 15:18:02 -0800, Segovia, Benjamin wrote:
Hello all,
is the kernel driver configured to support reads/writes to LLC (last level
cache i.e. L3) on SNB?
Now it's under limited use for the buffer that is sure to be cached,
e.g hw status page, etc. code lives in
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