On Mon, 3 Oct 2011 16:21:08 -0700, Jesse Barnes
wrote:
> Agreed; fortunately shutting everything off when no outputs are
> active should be simpler than trying flip the bits on & off every mode
> set. :)
We'd have to track when outputs are shut off; just tracking per clock
doesn't seem any
On Mon, 03 Oct 2011 16:18:48 -0700
Keith Packard wrote:
> On Mon, 3 Oct 2011 14:14:23 -0700, Jesse Barnes
> wrote:
>
> > Now... is keeping the various refclks enabled costing us any power?
> > IOW, should we be trying to disable them when everything has been
> > DPMS'd off too?
>
> That's
On Mon, 3 Oct 2011 14:14:23 -0700, Jesse Barnes
wrote:
> Now... is keeping the various refclks enabled costing us any power?
> IOW, should we be trying to disable them when everything has been
> DPMS'd off too?
That's the same as tracking usage and enabling/disabling on the fly as
modes are
On Wed, 28 Sep 2011 15:22:48 -0300
Paulo Zanoni wrote:
> 2011/9/27 Keith Packard :
> > Here's a patch sequence which cleans up a bunch of PCH refclk related
> > bits.
>
> For the series: Tested-by: Paulo Zanoni
>
> Tested all the patches on Ironlake (LVDS + VGA). Fixes fd.o bug #38750 for me.
On Mon, 3 Oct 2011 14:14:23 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Now... is keeping the various refclks enabled costing us any power?
IOW, should we be trying to disable them when everything has been
DPMS'd off too?
That's the same as tracking usage and enabling/disabling on
2011/9/27 Keith Packard :
> Here's a patch sequence which cleans up a bunch of PCH refclk related
> bits.
For the series: Tested-by: Paulo Zanoni
Tested all the patches on Ironlake (LVDS + VGA). Fixes fd.o bug #38750 for me.
I also tested the patch you sent today 1 hour ago (inline in one of
On Wed, 28 Sep 2011 15:22:48 -0300, Paulo Zanoni wrote:
> I also tested the patch you sent today 1 hour ago (inline in one of
> the emails) and things still work with it. I'll keep using these
> patches since they fix my laptop. Any problem will be reported.
Thanks. I think we're failing to
2011/9/27 Keith Packard kei...@keithp.com:
Here's a patch sequence which cleans up a bunch of PCH refclk related
bits.
For the series: Tested-by: Paulo Zanoni paulo.r.zan...@intel.com
Tested all the patches on Ironlake (LVDS + VGA). Fixes fd.o bug #38750 for me.
I also tested the patch you
On Wed, 28 Sep 2011 15:22:48 -0300, Paulo Zanoni przan...@gmail.com wrote:
I also tested the patch you sent today 1 hour ago (inline in one of
the emails) and things still work with it. I'll keep using these
patches since they fix my laptop. Any problem will be reported.
Thanks. I think we're
On Mon, 26 Sep 2011 23:11:37 -0700, Keith Packard wrote:
> Ok, so I'd love to know where in any PCH reference matter someone has
> found a place where the reference clock for any of the PLLs is
> anything other than 120MHz. Can someone find a reference for other
> frequencies?
Oddly in the
On Tue, 27 Sep 2011 10:01:33 +0100, Chris Wilson
wrote:
> Oddly in the diagram SSC4 is given as a 100MHz clock that can be used for
> any output other than DP_A. However, the configuration register marks that
> as being a test-only mode.
Ok, it's all irrelevant -- the only configurations using
Here's a patch sequence which cleans up a bunch of PCH refclk related
bits. There are a couple of questionable patches that I'd like to see
people look at:
[PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings
[PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time
Here's the
Here's a patch sequence which cleans up a bunch of PCH refclk related
bits. There are a couple of questionable patches that I'd like to see
people look at:
[PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings
[PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time
Here's the
On Mon, 26 Sep 2011 23:11:37 -0700, Keith Packard kei...@keithp.com wrote:
Ok, so I'd love to know where in any PCH reference matter someone has
found a place where the reference clock for any of the PLLs is
anything other than 120MHz. Can someone find a reference for other
frequencies?
On Tue, 27 Sep 2011 10:01:33 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Oddly in the diagram SSC4 is given as a 100MHz clock that can be used for
any output other than DP_A. However, the configuration register marks that
as being a test-only mode.
Ok, it's all irrelevant -- the only
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