As it turns out, the aux block being off was not the real problem here,
as transition from D3 to D0 is mandated by the DP spec to take a maximum
of 1ms, whereas we're allowed a 100ms timeframe to respond to ESI irqs.
The real problem here is a bit more subtle.
When doing a modeset where the
Hi All,
This is extension to Lukasz Spintzyk earlier draft of damage interface for drm.
Bascially a new plane property is added called "DAMAGE_CLIPS" which is simply
an array of drm_rect (exported to userspace as drm_mode_rect). The clips
represents damage in framebuffer coordinate of attached fb
This patch adds a helper which should be called by driver which enable
damage (by calling drm_plane_enable_damage_clips) from atomic_check
hook. This helper for now set the damage to NULL for the planes on crtc
which need full modeset.
The driver also need to check for other crtc properties which
From: Lukasz Spintzyk
Optional plane property to mark damaged regions on the plane in
framebuffer coordinates of the framebuffer attached to the plane.
The layout of blob data is simply an array of drm_mode_rect with maximum
array size limited by
With damage property in drm_plane_state, this patch adds helper iterator
to traverse the damage clips. Iterator will return the damage rectangles
in framebuffer, plane or crtc coordinates as need by driver
implementation.
Signed-off-by: Deepak Rawat
---
On Thursday 05 April 2018 12:53 AM, Sean Paul wrote:
On Wed, Apr 04, 2018 at 12:07:41PM -0700, Rodrigo Vivi wrote:
On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
In both HDMI and DP, device count is represented by 6:0 bits of a
register(BInfo/Bstatus)
So macro for bitmasking
As it turns out, the aux block being off was not the real problem here,
as transition from D3 to D0 is mandated by the DP spec to take a maximum
of 1ms, whereas we're allowed a 100ms timeframe to respond to ESI irqs.
The real problem here is a bit more subtle.
When doing a modeset where the
https://bugs.freedesktop.org/show_bug.cgi?id=104034
Timothy Arceri changed:
What|Removed |Added
Resolution|--- |FIXED
https://bugs.freedesktop.org/show_bug.cgi?id=104082
b...@nord-west.org changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Resolution|FIXED
https://bugs.freedesktop.org/show_bug.cgi?id=100105
--- Comment #3 from Jan Vesely ---
(In reply to Jan Vesely from comment #2)
> It looks like our vstore_half_rtn is not working as expected, which is weird
> because it passes CTS.
I take this back.
vstore_half_rtn
https://bugs.freedesktop.org/show_bug.cgi?id=105026
Timothy Arceri changed:
What|Removed |Added
Status|NEW |RESOLVED
Hi Kieran,
On Wednesday, 4 April 2018 19:00:10 EEST Kieran Bingham wrote:
> Hi Laurent,
>
> Thank you for the patch.
>
> I don't envy you on having to deal with this one ... it's a bit of a pain
> ...
Yes it was a bit painful :-/ The devil was both in the big picture and the
details this
These comments answer all the questions I had for myself when
implementing a driver using the GPU scheduler.
Signed-off-by: Eric Anholt
---
include/drm/gpu_scheduler.h | 46 +
1 file changed, 42 insertions(+), 4 deletions(-)
diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=105869
--- Comment #2 from Pierre-Loup A. Griffais ---
[18:11:28] can someone reply here
https://bugs.freedesktop.org/show_bug.cgi?id=105869 that version is 5.0.1-4
from Debian Testing, if I ever find another bug I'll
https://bugs.freedesktop.org/show_bug.cgi?id=93216
Timothy Arceri changed:
What|Removed |Added
Status|NEW |NEEDINFO
---
https://bugs.freedesktop.org/show_bug.cgi?id=100105
--- Comment #2 from Jan Vesely ---
Latest update:
diff --git a/src/cluda_opencl.h b/src/cluda_opencl.h
index 6e0095c..8ba2d14 100644
--- a/src/cluda_opencl.h
+++ b/src/cluda_opencl.h
@@ -48,7 +48,7 @@ typedef struct
https://bugs.freedesktop.org/show_bug.cgi?id=100105
Jan Vesely changed:
What|Removed |Added
See Also|
https://bugs.freedesktop.org/show_bug.cgi?id=100105
Jan Vesely changed:
What|Removed |Added
See Also|
https://bugs.freedesktop.org/show_bug.cgi?id=99549
Timothy Arceri changed:
What|Removed |Added
Status|NEW |RESOLVED
https://bugs.freedesktop.org/show_bug.cgi?id=93216
Axel Davy changed:
What|Removed |Added
Resolution|--- |FIXED
Hi Tomi,
On Wednesday, 4 April 2018 10:37:05 EEST Tomi Valkeinen wrote:
> On 04/04/18 00:11, Laurent Pinchart wrote:
> > I assume access to DMM-mapped buffers to be way more frequent than access
> > to the DMM registers. If that's the case, this partial workaround should
> > only slightly lower
Hi,
Here is an preliminary version of the MIPI-DSI support for the Allwinner
SoCs.
This controller can be found on a number of recent SoCs, such as the
A31, A33 or the A64.
Given the sparse documentation, there's a number of obscure areas, but
the current implementation has been tested with a
The "CPU" (or Intel 8080) interface uses a different interrupt called
TRI_FINISH (most likely TRI being for trigger) to notify the end of frames,
and hence the VBLANK period.
And that interrupt to the possible VBLANK interrupts source.
Reviewed-by: Chen-Yu Tsai
Signed-off-by:
On 04/04/2018 11:56 AM, Daniel Vetter wrote:
On Wed, Apr 04, 2018 at 11:10:08AM +0200, Thomas Hellstrom wrote:
On 04/04/2018 10:43 AM, Daniel Vetter wrote:
On Wed, Apr 04, 2018 at 10:22:21AM +0200, Thomas Hellstrom wrote:
Hi,
On 04/04/2018 08:58 AM, Daniel Vetter wrote:
On Wed, Apr 4, 2018
Hi Tomi,
On Wednesday, 4 April 2018 13:02:04 EEST Tomi Valkeinen wrote:
> On 04/04/18 12:51, Laurent Pinchart wrote:
> > On Wednesday, 4 April 2018 10:37:05 EEST Tomi Valkeinen wrote:
> >> On 04/04/18 00:11, Laurent Pinchart wrote:
> >>> I assume access to DMM-mapped buffers to be way more
On 26/03/18 19:21, Benoit Parrot wrote:
> Currently available display mode from a connector are filtered out
> based only on pixel clock capability. However we also need to filter
> out wider mode if we cannot handle them based on available pipeline
> capabilities.
>
> Signed-off-by: Benoit
On 2018-04-04 15:56, Daniel Vetter wrote:
On Wed, Apr 04, 2018 at 02:34:40PM +0530, Rajesh Yadav wrote:
MSM display controller hardware (DPU) has an inbuilt RSC block
which can control power resources and bus bandwidth voting
based on frame timing parameters w/o DPU driver intervention.
In
Op 04-04-18 om 13:37 schreef Rob Clark:
> On Wed, Apr 4, 2018 at 6:36 AM, Maarten Lankhorst
> wrote:
>> Op 04-04-18 om 12:21 schreef Daniel Vetter:
>>> On Wed, Apr 04, 2018 at 12:03:00PM +0200, Daniel Vetter wrote:
On Tue, Apr 03, 2018 at 06:42:23PM -0400,
On Wed, Apr 4, 2018 at 5:56 AM, Daniel Vetter wrote:
> On Wed, Apr 04, 2018 at 11:10:08AM +0200, Thomas Hellstrom wrote:
>> On 04/04/2018 10:43 AM, Daniel Vetter wrote:
>> > On Wed, Apr 04, 2018 at 10:22:21AM +0200, Thomas Hellstrom wrote:
>> > > Hi,
>> > >
>> > > On 04/04/2018
Most of the other cross-driver gfx infrastructure (dma_buf, dma_fence)
also gets cross posted to all the relevant gfx/memory lists. Doing the
same for ION means people won't miss relevant patches.
Cc: Laura Abbott
Cc: Sumit Semwal
Cc:
On 04/04/18 13:28, Laurent Pinchart wrote:
> Hi Tomi,
>
> On Wednesday, 4 April 2018 13:02:04 EEST Tomi Valkeinen wrote:
>> On 04/04/18 12:51, Laurent Pinchart wrote:
>>> On Wednesday, 4 April 2018 10:37:05 EEST Tomi Valkeinen wrote:
On 04/04/18 00:11, Laurent Pinchart wrote:
> I assume
Hi Tomi,
On Wednesday, 4 April 2018 13:50:43 EEST Tomi Valkeinen wrote:
> On 04/04/18 00:11, Laurent Pinchart wrote:
> >> + dma_async_issue_pending(dmm->wa_dma_chan);
> >> + status = dma_sync_wait(dmm->wa_dma_chan, cookie);
> >
> > dma_sync_wait() has a 5s timeout. You're calling this function
Hi Tomi,
On Wednesday, 4 April 2018 13:33:02 EEST Tomi Valkeinen wrote:
> On 04/04/18 13:28, Laurent Pinchart wrote:
> > On Wednesday, 4 April 2018 13:02:04 EEST Tomi Valkeinen wrote:
> >> On 04/04/18 12:51, Laurent Pinchart wrote:
> >>> On Wednesday, 4 April 2018 10:37:05 EEST Tomi Valkeinen
On Wed, Apr 04, 2018 at 11:10:08AM +0200, Thomas Hellstrom wrote:
> On 04/04/2018 10:43 AM, Daniel Vetter wrote:
> > On Wed, Apr 04, 2018 at 10:22:21AM +0200, Thomas Hellstrom wrote:
> > > Hi,
> > >
> > > On 04/04/2018 08:58 AM, Daniel Vetter wrote:
> > > > On Wed, Apr 4, 2018 at 12:42 AM, Rob
Most of the Allwinner SoCs since the A31 share the same MIPI-DSI
controller.
While that controller is mostly undocumented, the code is out there and has
been cleaned up in order to be integrated into DRM. However, there's still
some dark areas that are a bit unclear about how the block exactly
The LHR050H41 from BananaPi is a 1280x700 4-lanes DSI panel based on the
ILI9881c from Ilitek.
Acked-by: Rob Herring
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.txt | 20
1
The Allwinner SoCs usually come with a DSI encoder. Add a binding for it.
Reviewed-by: Rob Herring
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 93 +++-
1 file changed, 93 insertions(+)
create
The LHR050H41 panel is the panel shipped with the BananaPi M2-Magic, and is
based on the Ilitek ILI9881c Controller. Add a driver for it, modelled
after the other Ilitek controller drivers.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/panel/Kconfig
The BananaPi M2M has an optional 1280x720 DSI panel. Since that panel is
optional, we can only show a DT patch that would show how to enable it.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 39 +-
1 file changed,
The DSI controller needs a particular interface (CPU aka 8080) with some
modifications from the TCON in order to run.
Make sure the TCON is able to provide it when we are using the DSI output.
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
The A33 has a MIPI-DSI block, along with its D-PHY. Let's add it in order
to use it in the relevant boards.
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun8i-a33.dtsi | 44 +-
1 file
On 29 March 2018 at 08:17, Daniel Vetter wrote:
> On Wed, Mar 28, 2018 at 04:11:39PM +0100, Emil Velikov wrote:
>> On 28 March 2018 at 15:49, Chris Wilson wrote:
>> > Quoting Emil Velikov (2018-03-28 02:24:48)
>> >> From: Deepak Sharma
https://bugs.freedesktop.org/show_bug.cgi?id=99236
Timothy Arceri changed:
What|Removed |Added
Status|NEW |RESOLVED
On 04/04/2018 12:28 PM, Thomas Hellstrom wrote:
On 04/04/2018 11:56 AM, Daniel Vetter wrote:
On Wed, Apr 04, 2018 at 11:10:08AM +0200, Thomas Hellstrom wrote:
On 04/04/2018 10:43 AM, Daniel Vetter wrote:
On Wed, Apr 04, 2018 at 10:22:21AM +0200, Thomas Hellstrom wrote:
Hi,
On 04/04/2018
On Tue, Apr 03, 2018 at 06:42:23PM -0400, Rob Clark wrote:
> Add an atomic helper to implement dirtyfb support. This is needed to
> support DSI command-mode panels with x11 userspace (ie. when we can't
> rely on pageflips to trigger a flush to the panel).
>
> To signal to the driver that the
On Wed, Apr 04, 2018 at 02:34:40PM +0530, Rajesh Yadav wrote:
> MSM display controller hardware (DPU) has an inbuilt RSC block
> which can control power resources and bus bandwidth voting
> based on frame timing parameters w/o DPU driver intervention.
> In absence of RSC HW, DPU driver controls
On 04/04/18 00:11, Laurent Pinchart wrote:
>> +dma_async_issue_pending(dmm->wa_dma_chan);
>> +status = dma_sync_wait(dmm->wa_dma_chan, cookie);
>
> dma_sync_wait() has a 5s timeout. You're calling this function with a
> spinlock
> held. The end result might be slightly better than a
On Wed, Apr 4, 2018 at 6:21 AM, Daniel Vetter wrote:
> On Wed, Apr 04, 2018 at 12:03:00PM +0200, Daniel Vetter wrote:
>> On Tue, Apr 03, 2018 at 06:42:23PM -0400, Rob Clark wrote:
>> > Add an atomic helper to implement dirtyfb support. This is needed to
>> > support DSI
https://bugs.freedesktop.org/show_bug.cgi?id=105883
Bug ID: 105883
Summary: booting with kernel using amd-staging-drm-next on
2400G hangs
Product: DRI
Version: DRI git
Hardware: x86-64 (AMD64)
OS: Linux
On 04/04/18 12:51, Laurent Pinchart wrote:
> Hi Tomi,
>
> On Wednesday, 4 April 2018 10:37:05 EEST Tomi Valkeinen wrote:
>> On 04/04/18 00:11, Laurent Pinchart wrote:
>>> I assume access to DMM-mapped buffers to be way more frequent than access
>>> to the DMM registers. If that's the case, this
On Wed, Apr 04, 2018 at 12:03:00PM +0200, Daniel Vetter wrote:
> On Tue, Apr 03, 2018 at 06:42:23PM -0400, Rob Clark wrote:
> > Add an atomic helper to implement dirtyfb support. This is needed to
> > support DSI command-mode panels with x11 userspace (ie. when we can't
> > rely on pageflips to
On 2018-04-03 02:03 PM, Daniel Vetter wrote:
> On Tue, Apr 3, 2018 at 1:52 PM, Daniel Vetter wrote:
>> On Tue, Apr 3, 2018 at 1:13 PM, Lucas Stach wrote:
>>> Hi Daniel,
>>>
>>> Am Dienstag, den 03.04.2018, 12:01 +0200 schrieb Daniel Vetter:
On Tue, Apr 3,
Op 04-04-18 om 12:21 schreef Daniel Vetter:
> On Wed, Apr 04, 2018 at 12:03:00PM +0200, Daniel Vetter wrote:
>> On Tue, Apr 03, 2018 at 06:42:23PM -0400, Rob Clark wrote:
>>> Add an atomic helper to implement dirtyfb support. This is needed to
>>> support DSI command-mode panels with x11
On Wed, Apr 4, 2018 at 6:36 AM, Maarten Lankhorst
wrote:
> Op 04-04-18 om 12:21 schreef Daniel Vetter:
>> On Wed, Apr 04, 2018 at 12:03:00PM +0200, Daniel Vetter wrote:
>>> On Tue, Apr 03, 2018 at 06:42:23PM -0400, Rob Clark wrote:
Add an atomic helper to
On 2018-04-05 01:51, Sean Paul wrote:
On Wed, Apr 04, 2018 at 02:34:40PM +0530, Rajesh Yadav wrote:
MSM display controller hardware (DPU) has an inbuilt RSC block
which can control power resources and bus bandwidth voting
based on frame timing parameters w/o DPU driver intervention.
In absence
On 4/4/2018 2:54 AM, Jordan Crouse wrote:
On Fri, Mar 23, 2018 at 12:49:51PM +0530, Sharat Masetty wrote:
The last level system cache can be partitioned to 32
different slices of which GPU has two slices preallocated.
The "gpu" slice is used for caching GPU buffers and
the "gpuhtw" slice is
https://bugs.freedesktop.org/show_bug.cgi?id=105680
--- Comment #7 from Marta Löfstedt ---
(In reply to Jose Roberto de Souza from comment #6)
> Done: https://patchwork.freedesktop.org/series/41156/
Thanks for the patch, we'll need a drmtip run to see if it works,
https://bugs.freedesktop.org/show_bug.cgi?id=105883
--- Comment #4 from Edward Kigwana ---
Try
options amdgpu dpm=0 dc=1 and seee if it still locks up.
--
You are receiving this mail because:
You are the assignee for the
On 4/4/2018 2:52 AM, Jordan Crouse wrote:
On Fri, Mar 23, 2018 at 12:49:48PM +0530, Sharat Masetty wrote:
Add client side bindings required for the GPU to use the last level
system cache. Also add a register range in the GPU CX domain.
Reviewed-by: Jordan Crouse
On 2018-04-04 17:49, Daniel Vetter wrote:
On Wed, Apr 04, 2018 at 04:53:51PM +0530, rya...@codeaurora.org wrote:
On 2018-04-04 15:56, Daniel Vetter wrote:
> On Wed, Apr 04, 2018 at 02:34:40PM +0530, Rajesh Yadav wrote:
> > MSM display controller hardware (DPU) has an inbuilt RSC block
> > which
On Wed, Apr 04, 2018 at 07:40:32AM -0400, Rob Clark wrote:
> On Wed, Apr 4, 2018 at 5:56 AM, Daniel Vetter wrote:
> > On Wed, Apr 04, 2018 at 11:10:08AM +0200, Thomas Hellstrom wrote:
> >> On 04/04/2018 10:43 AM, Daniel Vetter wrote:
> >> > On Wed, Apr 04, 2018 at 10:22:21AM
On Wed, Apr 4, 2018 at 2:05 PM, Rob Clark wrote:
> On Wed, Apr 4, 2018 at 7:49 AM, Maarten Lankhorst
> wrote:
>> Op 04-04-18 om 13:37 schreef Rob Clark:
>>> On Wed, Apr 4, 2018 at 6:36 AM, Maarten Lankhorst
>>>
://github.com/0day-ci/linux/commits/Xidong-Wang/drm-i915-Do-not-use-kfree-to-free-kmem_cache_alloc-return-value/20180404-193341
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a1-201813 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce
On 04/04/2018 03:30 AM, Daniel Vetter wrote:
Most of the other cross-driver gfx infrastructure (dma_buf, dma_fence)
also gets cross posted to all the relevant gfx/memory lists. Doing the
same for ION means people won't miss relevant patches.
No problem from me, the rate of checkpatch fixups
On Wed, Apr 4, 2018 at 7:49 AM, Maarten Lankhorst
wrote:
> Op 04-04-18 om 13:37 schreef Rob Clark:
>> On Wed, Apr 4, 2018 at 6:36 AM, Maarten Lankhorst
>> wrote:
>>> Op 04-04-18 om 12:21 schreef Daniel Vetter:
On Wed, Apr
On Wed, Apr 04, 2018 at 01:46:37PM +0200, Thomas Hellstrom wrote:
> On 04/04/2018 12:28 PM, Thomas Hellstrom wrote:
> > On 04/04/2018 11:56 AM, Daniel Vetter wrote:
> > > On Wed, Apr 04, 2018 at 11:10:08AM +0200, Thomas Hellstrom wrote:
> > > > On 04/04/2018 10:43 AM, Daniel Vetter wrote:
> > > >
Op 04-04-18 om 14:05 schreef Rob Clark:
> On Wed, Apr 4, 2018 at 7:49 AM, Maarten Lankhorst
> wrote:
>> Op 04-04-18 om 13:37 schreef Rob Clark:
>>> On Wed, Apr 4, 2018 at 6:36 AM, Maarten Lankhorst
>>> wrote:
Op 04-04-18
Op 04-04-18 om 14:26 schreef Daniel Vetter:
> On Wed, Apr 4, 2018 at 2:05 PM, Rob Clark wrote:
>> On Wed, Apr 4, 2018 at 7:49 AM, Maarten Lankhorst
>> wrote:
>>> Op 04-04-18 om 13:37 schreef Rob Clark:
On Wed, Apr 4, 2018 at 6:36 AM,
Hello,
First of all, thank you for the patch. This generates more discussion than I
had anticipated, which is both good and bad. I'll comment through the e-mail,
and try to explain both my initial idea, and also where it could lead us.
On Tuesday, 27 March 2018 16:02:31 EEST jacopo mondi
On Wed, Apr 4, 2018 at 3:24 PM, Rob Clark wrote:
> On Wed, Apr 4, 2018 at 8:16 AM, Daniel Vetter wrote:
>> On Wed, Apr 04, 2018 at 07:40:32AM -0400, Rob Clark wrote:
>>> On Wed, Apr 4, 2018 at 5:56 AM, Daniel Vetter wrote:
>>> > On Wed, Apr
https://bugs.freedesktop.org/show_bug.cgi?id=105880
--- Comment #3 from Harry Wentland ---
Looks like we don't detect a display. Can you capture dmesg with cik_support=1
dc=1 dc_log=1 to get more log info?
--
You are receiving this mail because:
You are the assignee for
On Wed, Apr 04, 2018 at 04:53:51PM +0530, rya...@codeaurora.org wrote:
> On 2018-04-04 15:56, Daniel Vetter wrote:
> > On Wed, Apr 04, 2018 at 02:34:40PM +0530, Rajesh Yadav wrote:
> > > MSM display controller hardware (DPU) has an inbuilt RSC block
> > > which can control power resources and bus
https://bugs.freedesktop.org/show_bug.cgi?id=105837
Michel Dänzer changed:
What|Removed |Added
QA Contact|xorg-t...@lists.x.org
On Wed, Apr 04, 2018 at 07:35:58AM -0400, Rob Clark wrote:
> On Wed, Apr 4, 2018 at 6:21 AM, Daniel Vetter wrote:
> > On Wed, Apr 04, 2018 at 12:03:00PM +0200, Daniel Vetter wrote:
> >> On Tue, Apr 03, 2018 at 06:42:23PM -0400, Rob Clark wrote:
> >> > Add an atomic helper to
Tomi Valkeinen wrote on Wed [2018-Apr-04 14:12:13
+0300]:
> On 26/03/18 19:21, Benoit Parrot wrote:
> > Currently available display mode from a connector are filtered out
> > based only on pixel clock capability. However we also need to filter
> > out wider mode if we
://github.com/0day-ci/linux/commits/Xidong-Wang/drm-i915-Do-not-use-kfree-to-free-kmem_cache_alloc-return-value/20180404-193341
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
On Wed, Apr 4, 2018 at 8:16 AM, Daniel Vetter wrote:
> On Wed, Apr 04, 2018 at 07:40:32AM -0400, Rob Clark wrote:
>> On Wed, Apr 4, 2018 at 5:56 AM, Daniel Vetter wrote:
>> > On Wed, Apr 04, 2018 at 11:10:08AM +0200, Thomas Hellstrom wrote:
>> >> On 04/04/2018
On Wed, Apr 04, 2018 at 12:36:20PM +0200, Michel Dänzer wrote:
> On 2018-04-03 02:03 PM, Daniel Vetter wrote:
> > On Tue, Apr 3, 2018 at 1:52 PM, Daniel Vetter wrote:
> >> On Tue, Apr 3, 2018 at 1:13 PM, Lucas Stach wrote:
> >>> Hi Daniel,
> >>>
> >>> Am
On Wed, Apr 4, 2018 at 8:26 AM, Daniel Vetter wrote:
> On Wed, Apr 4, 2018 at 2:05 PM, Rob Clark wrote:
>> On Wed, Apr 4, 2018 at 7:49 AM, Maarten Lankhorst
>> wrote:
>>> Op 04-04-18 om 13:37 schreef Rob Clark:
On
Am Montag, den 02.04.2018, 21:50 +0300 schrieb Laurent Pinchart:
> The __omap_gem_get_pages() function is a wrapper around
> omap_gem_attach_pages() that returns the omap_obj->pages pointer through
> a function argument. Some callers don't need the pages pointer, and all
> of them can access
-ci/linux/commits/Xidong-Wang/drm-i915-Do-not-use-kfree-to-free-kmem_cache_alloc-return-value/20180404-193341
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x009-201813 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save
https://bugs.freedesktop.org/show_bug.cgi?id=105339
--- Comment #6 from Ben Clapp ---
With a TR 1950X CPU, RX 580 GPU, Debian testing branch (buster), Mesa 18.0, I'm
also able to reproduce this bug. (I also discovered it using Dolphin.)
The issue wasn't present in 17.3.7,
Hi Benoit,
On Wednesday, 4 April 2018 16:15:11 EEST Benoit Parrot wrote:
> Tomi Valkeinen wrote on Wed [2018-Apr-04 14:12:13 +0300]:
> > On 26/03/18 19:21, Benoit Parrot wrote:
> >> Currently available display mode from a connector are filtered out
> >> based only on pixel clock capability.
Hi Benoit,
Thank you for the patch.
On Monday, 26 March 2018 19:21:24 EEST Benoit Parrot wrote:
> Add common DISPC bindings into the top level bindings file.
> Move common bindings here instead of having multiple copies of
> the same information in all of the variant specific files.
>
>
On Wed, Apr 04, 2018 at 11:46:30AM +0100, Emil Velikov wrote:
> On 29 March 2018 at 08:17, Daniel Vetter wrote:
> > On Wed, Mar 28, 2018 at 04:11:39PM +0100, Emil Velikov wrote:
> >> On 28 March 2018 at 15:49, Chris Wilson wrote:
> >> > Quoting Emil
On Wed, Apr 04, 2018 at 07:17:39AM -0700, Laura Abbott wrote:
> On 04/04/2018 03:30 AM, Daniel Vetter wrote:
> > Most of the other cross-driver gfx infrastructure (dma_buf, dma_fence)
> > also gets cross posted to all the relevant gfx/memory lists. Doing the
> > same for ION means people won't
In the 'auto' case, the `with_atomic` check was bypassed.
Signed-off-by: Eric Engestrom
---
meson.build | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/meson.build b/meson.build
index e762dcc44bff5deac4d1..72cdd14a3ba834abde4d 100644
In the 'auto' case, the `with_atomic` check was bypassed.
Signed-off-by: Eric Engestrom
---
meson.build | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/meson.build b/meson.build
index 72cdd14a3ba834abde4d..4bc088bacdd8120c1508 100644
In the 'auto' case, the `with_atomic` check was bypassed.
Signed-off-by: Eric Engestrom
---
meson.build | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/meson.build b/meson.build
index 4bc088bacdd8120c1508..edcc7e8ddc39b1760868 100644
Signed-off-by: Eric Engestrom
---
meson.build | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/meson.build b/meson.build
index f0804fc5a0a1d907313f..72e5836e78bd239584b3 100644
--- a/meson.build
+++ b/meson.build
@@ -77,6 +77,7 @@
Signed-off-by: Eric Engestrom
---
meson.build | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/meson.build b/meson.build
index 55ad207b6de349863be3..ba8072a19515f8d7aaa4 100644
--- a/meson.build
+++ b/meson.build
@@ -161,8 +161,10 @@
In the 'auto' case, the `with_atomic` check was bypassed.
Signed-off-by: Eric Engestrom
---
meson.build | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/meson.build b/meson.build
index 961ee59cff6dc3c2cbb9..e762dcc44bff5deac4d1 100644
In the 'auto' case, the `with_atomic` check was bypassed.
Signed-off-by: Eric Engestrom
---
meson.build | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/meson.build b/meson.build
index edcc7e8ddc39b1760868..55ad207b6de349863be3 100644
Signed-off-by: Eric Engestrom
---
meson.build | 21 +
1 file changed, 21 insertions(+)
diff --git a/meson.build b/meson.build
index 5b6710ee8dc16b02dbed..8efa99b54e6a108b8255 100644
--- a/meson.build
+++ b/meson.build
@@ -69,6 +69,27 @@ endif
Signed-off-by: Eric Engestrom
---
meson.build | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/meson.build b/meson.build
index ba8072a19515f8d7aaa4..5b6710ee8dc16b02dbed 100644
--- a/meson.build
+++ b/meson.build
@@ -171,8 +171,10 @@ endif
#
Signed-off-by: Eric Engestrom
---
meson.build | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/meson.build b/meson.build
index 29f91ee9f6eb96b05f0d..f0804fc5a0a1d907313f 100644
--- a/meson.build
+++ b/meson.build
@@ -76,6 +76,7 @@ foreach d :
Signed-off-by: Eric Engestrom
---
meson.build | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/meson.build b/meson.build
index 8efa99b54e6a108b8255..12cf96157b2789df3a55 100644
--- a/meson.build
+++ b/meson.build
@@ -70,6 +70,7 @@
On Fri, Mar 30, 2018 at 04:26:53PM +0200, Hans de Goede wrote:
> Hi,
>
> On 30-03-18 15:25, Hans de Goede wrote:
> > Hi,
> >
> > On 30-03-18 14:44, Chris Wilson wrote:
> >> Quoting Hans de Goede (2018-03-30 13:37:40)
> >>> Hi,
> >>>
> >>> On 30-03-18 14:30, Chris Wilson wrote:
> Quoting
https://bugs.freedesktop.org/show_bug.cgi?id=105837
--- Comment #3 from Sherif ---
Created attachment 138584
--> https://bugs.freedesktop.org/attachment.cgi?id=138584=edit
Output of $ DRI_PRIME=1 glxinfo.
--
You are receiving this mail because:
You are the assignee
Entrypoint has been listed since the etnaviv support was added, but was
never implemented, and therefore never exported either.
Fixes: 95e2cc6a801d92a0634b "libdrm: add etnaviv drm support"
Cc: Christian Gmeiner
Cc: Lucas Stach
Signed-off-by:
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