https://bugs.freedesktop.org/show_bug.cgi?id=107465
--- Comment #3 from Germano Massullo ---
Just a clarification: title "amdgpu.dc=1" is not meant as having amdgpu.dc=1 as
setted boot parameter, the situation is:
no boot parameter = problem triggered
amdgpu.dc=0 = no problem
--
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On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec wrote:
>
> This series adds support for Display Engine 3.0 and HDMI 2.0a, which
> can be found on H6 SoC.
>
> Display Engine 3.0 in comparison to 2.0 mostly adds features needed for
> displaying and processing 10-bit and AFBC formats, which are not
Hi
Is there an updated series? These no longer apply for me
Thanks
Mike
On Wed, 22 Aug 2018 at 09:42 Huang Rui wrote:
> On Wed, Aug 22, 2018 at 04:24:02PM +0800, Christian König wrote:
> > Please commit patches #1, #2 and #3, doesn't make much sense to send
> > them out even more often.
> >
https://bugs.freedesktop.org/show_bug.cgi?id=107465
Germano Massullo changed:
What|Removed |Added
Summary|System does not recognize |amdgpu.dc=1 triggers
https://bugs.freedesktop.org/show_bug.cgi?id=107154
--- Comment #10 from freedesktop@nentwig.biz ---
So, there's 4.19rc1-amd-next \o/
echo: write error: Device or resource busy
This started to happen with 4.18. dmesg:
[ 171.245467] Freezing of tasks failed after 20.006 seconds (1 tasks
On Fri, Aug 31, 2018 at 11:32 AM Christian König
wrote:
>
> Am 31.08.2018 um 17:27 schrieb Emil Velikov:
> > On 31 August 2018 at 15:38, Michel Dänzer wrote:
> >> [ Adding the amd-gfx list ]
> >>
> >> On 2018-08-31 3:05 p.m., Thomas Hellstrom wrote:
> >>> On 08/31/2018 02:30 PM, Emil Velikov
That one is already committed to amd-staging-drm-next.
But I've fixed a few bugs with that just yesterday, not sure if the public copy
of amd-staging-drm-next is already up to date.
Christian.
Am 02.09.2018 10:12 schrieb Mike Lothian :
Hi
Is there an updated series? These no longer apply for
The driver for S6E63M0 AMOLED LCD panel is not used. It does not
support DeviceTree and respective possible users (S5Pv210 Aquila and
Goni boards) are DeviceTree-only.
Suggested-by: Marek Szyprowski
Cc: Marek Szyprowski
Cc: Inki Dae
Signed-off-by: Krzysztof Kozlowski
Acked-by: Jingoo Han
The driver for LD9040 AMOLED LCD panel was superseded with DRM driver
panel-samsung-ld9040.c. It does not support DeviceTree and respective
possible user (Exynos4210 Universal C210) is DeviceTree-only and uses
DRM version of driver.
Suggested-by: Marek Szyprowski
Cc: Marek Szyprowski
Cc: Inki
https://bugs.freedesktop.org/show_bug.cgi?id=107213
--- Comment #6 from george ---
Created attachment 141418
--> https://bugs.freedesktop.org/attachment.cgi?id=141418=edit
amdgpu crash in dmesg output
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https://bugzilla.kernel.org/show_bug.cgi?id=200531
Aleksandr Mezin (mezin.alexan...@gmail.com) changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Hi Noralf.
Only nitpicks, I have not the background
to review the actual implmentation.
So no tags from me to put on the commit.
Sam
> +/**
> + * drm_gem_shmem_create - Allocate an object with the given size
> + * @dev: DRM device
> + * @size: Size of the object to allocate
> + *
> + *
https://bugs.freedesktop.org/show_bug.cgi?id=107213
--- Comment #5 from george ---
Hello, found this bug via web search. I am experiencing the *exact* same bug.
I'm running Fedora 28 with MATE desktop, so I'm confident this is not a KDE
problem.
My error message:
[39911.150851]
This adds a library for shmem backed GEM objects with the necessary
drm_driver callbacks.
Signed-off-by: Noralf Trønnes
---
Changes since version 1:
- Fix missing argument in docs (kbuild test robot)
- Fix: sparse: expression using sizeof(void) (kbuild test robot)
- Rebasing gave a new
This move makes tinydrm useful for more drivers. tinydrm doesn't need
continuous memory, but at the time it was convenient to use the CMA
library. The spi core can do dma on is_vmalloc() addresses making this
possible.
Cc: David Lechner
Signed-off-by: Noralf Trønnes
---
This patchset adds a library for shmem backed GEM objects and makes use
of it in tinydrm.
When I made tinydrm I used the CMA helper because it was very easy to
use. July last year I learned that this limits which drivers to PRIME
import from, since CMA requires continuous memory. tinydrm drivers
在 2018/8/30 19:32, Christian König 写道:
[SNIP]
+
+struct drm_syncobj_wait_pt {
+ struct drm_syncobj_stub_fence base;
+ u64 value;
+ struct rb_node node;
+};
+struct drm_syncobj_signal_pt {
+ struct drm_syncobj_stub_fence base;
+ struct dma_fence *signal_fence;
+ struct
https://bugs.freedesktop.org/show_bug.cgi?id=107213
--- Comment #7 from Shmerl ---
I'm waiting for kernel 4.19.x to see if it improves anything, since it
apparently had some fix that looks related:
https://lists.freedesktop.org/archives/dri-devel/2018-August/185123.html
> drm/amd/display: Fix
On Fri, Aug 31, 2018 at 10:41:40AM +0200, Daniel Vetter wrote:
> On Fri, Aug 24, 2018 at 02:16:34AM +0300, Haneen Mohammed wrote:
> > crtc_state is accessed by both vblank_handle() and the ordered
> > work_struct handle vkms_crc_work_handle() to retrieve and or update
> > the frame number for
Currently MP clocks don't consider adjusting parent rate even if they
are allowed to do so. Such behaviour considerably lowers amount of
possible rates, which is very inconvenient when such clock is used for
pixel clock, for example.
In order to improve the situation, adjusting parent rate is
H6 has Synopsys DWC HDMI 2.0 TX PHY.
mpll settings were calculated from specifications of similar Synopsys
HDMI PHY found in i.MX6. Other PHY settings were derived from BSP PHY
driver code.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 137 +
Remove duplicated call, while at it.
Signed-off-by: Michał Mirosław
Acked-by: Daniel Vetter
---
drivers/gpu/drm/mgag200/mgag200_drv.c | 21 +
drivers/gpu/drm/mgag200/mgag200_main.c | 9 -
2 files changed, 1 insertion(+), 29 deletions(-)
diff --git
Signed-off-by: Michał Mirosław
Acked-by: Daniel Vetter
---
drivers/gpu/drm/virtio/virtgpu_drm_bus.c | 24 +++-
1 file changed, 3 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_drm_bus.c
b/drivers/gpu/drm/virtio/virtgpu_drm_bus.c
index
From: Icenowy Zheng
The Allwinner H6 SoC uses a v2.12a DesignWare HDMI controller, with
dedicated CEC and HDCP clocks added; the PHY connected is a standard
DesignWare HDMI PHY.
Add binding for it.
Signed-off-by: Icenowy Zheng
[added HDCP clock and reset]
Signed-off-by: Jernej Skrabec
---
It turns out that H6 HDMI BSP kernel driver doesn't change TMDS rate at
all. At this point it is not clear whether it is just not necessary or
it would cause some kind of issues.
Add a quirk for it.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 5 -
Signed-off-by: Michał Mirosław
Acked-by: Alex Deucher
Acked-by: Daniel Vetter
---
drivers/gpu/drm/radeon/radeon_drv.c | 23 +--
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index
This series adds support for Display Engine 3.0 and HDMI 2.0a, which
can be found on H6 SoC.
Display Engine 3.0 in comparison to 2.0 mostly adds features needed for
displaying and processing 10-bit and AFBC formats, which are not yet
supported by this series.
This series is based on linux-next
Since it is not possible to access sun8i-dw-hdmi driver private data
inside mode_valid function, make it configurable. That way different
versions of HDMI controllers can set different function, depending on
it's limitations.
Signed-off-by: Jernej Skrabec
---
It turns out that even new DW HDMI controllers exhibits same mangenta
line issues as older versions.
Enable workaround for v2.12a.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Video PLL factors can be set in a way that final PLL rate is outside
stable range. H6 user manual specifically says that N factor should not
be below 12. While it doesn't says anything about maximum stable rate, it
is clear that PLL doesn't work at 6.096 GHz (254 * 24 MHz).
Set minimum allowed
Mixer 0 has 1 VI and 3 UI planes, scaler on all planes and can output
4K image @60Hz. It also support 10 bit colors.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
Signed-off-by: Michał Mirosław
Acked-by: Daniel Vetter
---
drivers/gpu/drm/bochs/bochs_drv.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/bochs/bochs_drv.c
b/drivers/gpu/drm/bochs/bochs_drv.c
index 7b20318483e4..c61b40c72b62 100644
---
Interpret (otherwise-invalid) NULL apertures argument to mean all-memory
range. This will allow to remove several duplicates of this code
from drivers in following patches.
Signed-off-by: Michał Mirosław
Acked-by: Bartlomiej Zolnierkiewicz
---
v2: added kerneldoc to corresponding DRM helper
Document remove_conflicting_framebuffers() behaviour.
Signed-off-by: Michał Mirosław
---
drivers/video/fbdev/core/fbmem.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c
index 0df148eb4699..2de93b5014e3 100644
Almost all PCI drivers using remove_conflicting_framebuffers() wrap it
with the same code.
---
v2: add kerneldoc for DRM helper
v3: propagate remove_conflicting_framebuffers() return value
+ move kerneldoc to where function is implemented
Signed-off-by: Michał Mirosław
---
Display Engine 3 is an upgrade of DE2 with new features like support for
10 bit color formats and support for AFBC.
Most of DE2 code works with DE3, except some small details.
Add support for it.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_csc.c | 96
Most, if not all, registers found in DE2 still exists in DE3. However,
units are on different base addresses.
To prepare for addition of DE3 support, registers macros are reworked so
they take base address as parameter.
Signed-off-by: Jernej Skrabec
[rebased]
Signed-off-by: Icenowy Zheng
---
This commit adds all entries needed for HDMI to function properly.
Signed-off-by: Jernej Skrabec
[added DE3 bus]
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 201 +++
1 file changed, 201 insertions(+)
diff --git
Signed-off-by: Michał Mirosław
Acked-by: Alex Deucher
Acked-by: Daniel Vetter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 24 +---
1 file changed, 1 insertion(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
From: Icenowy Zheng
The Allwinner H6 SoC's DE3 needs the SRAM C section being claimed in the
system controller to work, like A64 DE2.
As H6 and A64 system controller are quite similar, code is reused now,
and the A64 fallback compatible string is added after the H6 compatible
string.
H6 is first Allwinner SoC which supports 10 bit colors, HDR and AFBC.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index dd19d674055c..e5731d092e1a
From: Icenowy Zheng
Allwinner H6 SoC has a cut down version of TCON TOP.
Add binding documentation for it.
Signed-off-by: Icenowy Zheng
[expanded description]
Signed-off-by: Jernej Skrabec
---
.../bindings/display/sunxi/sun4i-drm.txt | 14 --
1 file changed, 8
Support for mixer0, mixer1, writeback and rotation units is added.
Signed-off-by: Jernej Skrabec
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 65
drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 1 +
2 files changed, 66 insertions(+)
diff --git
On Fri, Aug 31, 2018 at 10:07:42AM +0100, Chris Wilson wrote:
[...]
> Ahah, someone is looking at remove_conflicting_framebuffers(). May I
> interest you in a use-after-free?
> [ 378.423513] stack segment: [#1] PREEMPT SMP PTI
> [ 378.423530] CPU: 1 PID: 4338 Comm: pm_rpm Tainted: G U
This commit adds compatibles used in H6 display pipeline, namely for
display engine, mixer and TV TCON.
H6 display engine is somewhat similar to R40, just less TCONs and
mixer support more features.
Signed-off-by: Jernej Skrabec
---
.../devicetree/bindings/display/sunxi/sun4i-drm.txt
Signed-off-by: Michał Mirosław
Acked-by: Bartlomiej Zolnierkiewicz
Acked-by: Daniel Vetter
---
drivers/video/fbdev/core/fbmem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c
index
From: Icenowy Zheng
Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
Add quirks support for TCON TOP.
Currently the presence of TCON_TV1 and DSI is controlled via the quirks
structure.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 43
H6 has DW HDMI 2.0 controller v2.12a.
It supports 4K at 60 Hz and HDCP 2.2.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
It turns out that TCON TOP registers in H6 SoC have non-zero reset
value. This may cause issues if bits are not changed during
configuration.
To prevent that, initialize registers to 0.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 7 +++
1 file changed, 7
From: Icenowy Zheng
As we have already binding for the H6 system controller, add its node
to the device tree.
Signed-off-by: Icenowy Zheng
[fixed compatible string]
Signed-off-by: Jernej Skrabec
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 23
1 file changed, 23
This commit adds necessary description and dt includes for H6 DE3 clock.
It is very similar to others, but memory region has some additional
registers not found in DE2.
Signed-off-by: Jernej Skrabec
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent
rate is 24MHz, intermediate result when calculating final rate easily
overflows 32 bit variable.
Because of that, introduce function for calculating clock rate which
uses 64 bit variable for intermediate result.
Use remove_conflicting_framebuffers(NULL) instead of open-coding it.
Signed-off-by: Michał Mirosław
Acked-by: Eric Anholt
Acked-by: Daniel Vetter
---
drivers/gpu/drm/vc4/vc4_drv.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git
From: Icenowy Zheng
The Allwinner H6 DE3 bus is similar to the A64 DE2 one.
Add its compatible string with the A64 string as fallback to the
binding.
Some description of the binding is modified to make it more generic.
Signed-off-by: Icenowy Zheng
---
Signed-off-by: Michał Mirosław
Acked-by: Daniel Vetter
---
drivers/gpu/drm/cirrus/cirrus_drv.c | 23 +--
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.c
b/drivers/gpu/drm/cirrus/cirrus_drv.c
index 69c4e352dd78..85ed8657c862
Currently sun8i-hdmi-phy driver supports only custom PHYs connected to
DW HDMI controller. Since newest Allwinner SoCs have unmodified Synopsys
PHY, driver has to be reorganized to support them.
Variant structure is expanded to allow differentiation between custom
and Sysnopsys PHYs and to hold
This series cleans up duplicated code for replacing firmware FB
driver with proper DRI driver and adds handover support to
Tegra driver.
This is a sligtly updated version of a series sent on 24 Nov 2017.
---
v2:
- rebased on current drm-next
- dropped staging/sm750fb changes
- added kernel
From: Icenowy Zheng
The TCON TOP on Allwinner H6 SoC is a cut down version of the R40 TCON
TOP, which dropped TCON_TV1 and DSI (which do not exist on H6).
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 8
1 file changed, 8 insertions(+)
Use remove_conflicting_framebuffers(NULL) instead of duplicating it.
Signed-off-by: Michał Mirosław
Acked-by: Maxime Ripard
Acked-by: Daniel Vetter
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git
Pine H64 board has HDMI type A connector.
Signed-off-by: Jernej Skrabec
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 25 +++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
Kick out firmware fb when loading Tegra driver.
Signed-off-by: Michał Mirosław
Acked-by: Daniel Vetter
---
drivers/gpu/drm/tegra/drm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 7afe2f635f74..b51ec138fed2 100644
---
Currently supported Allwinner SoCs with DW HDMI controller have
scrambled addresses and read lock. However, that is not true in general.
For example, A80 and H6 have normal addresses and normal read access.
Move code for unscrambling addresses and unlocking read access to it's
own function and
https://bugs.freedesktop.org/show_bug.cgi?id=107784
Bug ID: 107784
Summary: [AMD tahiti XT] displayport broken
Product: DRI
Version: DRI git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity:
https://bugs.freedesktop.org/show_bug.cgi?id=107784
--- Comment #1 from Sylvain BERTRAND ---
Created attachment 141416
--> https://bugs.freedesktop.org/attachment.cgi?id=141416=edit
kernel log
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