Actually, setting the registers for routing, use multiple 'if-else' for
different
routes, but this code would be more and more complicated while we
support more and more SoCs. Change that and use a function call per SoC so the
code will be more portable and clear.
Signed-off-by: Yongqiang Niu
Similar to commit ("drm/amdgpu: fix IH overflow on Vega10 v2")
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR doesn't trigger another memory writeback.
So what can happen is that we end up
In preparation for modularizing io-pgtable formats, add support
for reference counting the io-pgtable format modules to ensure
that the modules are not unloaded while they are in use.
Signed-off-by: Isaac J. Manjarres
---
drivers/iommu/io-pgtable-arm-v7s.c | 1 +
drivers/iommu/io-pgtable-arm.c
Hello. This resolution is supported by the Apu and the motherboard specs.
Will try what you suggest and let you know
Il Lun 4 Gen 2021, 12:10 Christian König
ha scritto:
> Hi Davide,
>
> adding a few of our AMD display people.
>
> In general as already suggested by others opening a bug report
Laurent,
Please review the patch, so that we can push the input_format to the
mainline, which completes the overall features handled wrt bridge.
On Thu, Dec 17, 2020 at 10:39 AM Vinay Simha B N wrote:
> Laurent,
>
> Please review the patch, so that we can push the input_format to the
>
> Add support for MT8183's G-57 Bifrost.
G72
signature.asc
Description: PGP signature
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
The goal of the Generic Kernel Image (GKI) effort is to have a common
kernel image that works across multiple Android devices. This involves
generating a kernel image that has core features integrated into it,
while SoC specific functionality can be added to the kernel for the
device as a module.
Add a basic GPU node for mt8192.
Signed-off-by: Nick Fan
---
This patch depends on Mediatek power and regulator support.
Listed as following.
[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
> GPUs with more than a single regulator (e.g. G-57 on MT8183) will
G72
signature.asc
Description: PGP signature
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
This patch add component RDMA4
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
b/include/linux/soc/mediatek/mtk-mmsys.h
index 13546e9..2c11617 100644
Now that everything is in place for modular io-pgtable formats,
allow the ARM LPAE and ARMV7S io-pgtable formats to be built
as modules, and allow the io-pgtable framework to be enabled,
without having to explicitly enable an io-pgtable format.
Signed-off-by: Isaac J. Manjarres
---
The Panfrost DRM driver depends on the availability of the ARM LPAE
io-pgtable format code to work properly. In preparation for having the
io-pgtable formats as modules, add a "pre" dependency with
MODULE_SOFTDEP() to ensure that the io-pgtable-arm format module is loaded
before loading the
The following series are intended to prepare the mtk-mmsys driver to
allow different DDP (Data Display Path) function call per SoC.
base 5.11-rc1
change since v3:
- move register operation into mmsys path select function
Yongqiang Niu (10):
soc: mediatek: mmsys: create mmsys folder
soc:
On Tue, 2021-01-05 at 07:49 +0200, Laurent Pinchart wrote:
> Hi Philipp,
>
> On Mon, Jan 04, 2021 at 04:30:36PM +0100, Philipp Zabel wrote:
> > On Sun, 2020-12-20 at 21:50 +0200, Laurent Pinchart wrote:
> > > Convert the i.MX6 HDMI TX text binding to YAML.
> > >
> > > Signed-off-by: Laurent
Am 05.01.21 um 08:32 schrieb Defang Bo:
Similar to commit ("drm/amdgpu: fix IH overflow on Vega10 v2").
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR doesn't trigger another memory
https://bugzilla.kernel.org/show_bug.cgi?id=211033
Jindrich Makovicka (makov...@gmail.com) changed:
What|Removed |Added
CC|
I use static analysis tool to find these funcs are similar to the
commit<0fa375e6bc90>(drm/rockchip: Fix suspend crash when drm is not bound),so
it's just defensive,
I haven't actually hitted this.
At 2021-01-05 01:00:27, "Alex Deucher" wrote:
>On Sun, Dec 27, 2020 at 3:56 PM Defang Bo
the mmsys will more and more complicated after support
more and more SoCs, add an independent folder will be
more clear
Signed-off-by: Yongqiang Niu
---
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mmsys/Makefile| 2 +
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373
The io-pgtable code constructs an array of init functions for each
page table format at compile time. This is not ideal, as it prevents
io-pgtable formats from being built as kernel modules.
In preparation for modularizing the io-pgtable formats, switch to a
dynamic registration scheme, where
Btw, should the driver switch to the lower supported resolution then?
Il Lun 4 Gen 2021, 13:04 Davide Corrado ha
scritto:
> Hello. This resolution is supported by the Apu and the motherboard specs.
> Will try what you suggest and let you know
>
> Il Lun 4 Gen 2021, 12:10 Christian König
> ha
move register operation into mmsys path select function
Signed-off-by: Yongqiang Niu
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +
1 file changed, 71 insertions(+), 69 deletions(-)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
add mt8192 mmsys support
Signed-off-by: Yongqiang Niu
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++
drivers/soc/mediatek/mmsys/mtk-mmsys.c| 9 ++
include/linux/soc/mediatek/mtk-mmsys.h| 1 +
4
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
b/include/linux/soc/mediatek/mtk-mmsys.h
index 7e2c0fe..ed99122 100644
On Mon, 2020-12-14 at 22:54 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu 於 2020年12月11日 週五 上午8:45寫道：
> >
> > On Thu, 2020-12-10 at 23:50 +0800, Chun-Kuang Hu wrote:
> > > Hi, Yongqiang:
> > >
> > > Yongqiang Niu 於 2020年12月10日 週四 下午5:08寫道：
> > > >
> > > > This patch add RDMA
Similar to commit ("drm/amdgpu: fix IH overflow on Vega10 v2").
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR doesn't trigger another memory writeback.
So what can happen is that we end
Using this code on A5xx (and probably older too) causes a
smmu bug.
Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)")
Signed-off-by: Konrad Dybcio
Tested-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 -
add mt8183 function call for setting the routing registers
Signed-off-by: Yongqiang Niu
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 ++
drivers/soc/mediatek/mmsys/mtk-mmsys.c| 1 +
Similar to commit ("drm/amdgpu: fix IH overflow on Vega10 v2").
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR doesn't trigger another memory writeback.
So what can happen is that we end
The SMMUv3 driver depends on the availability of the ARM LPAE io-pgtable
format code to work properly. In preparation for having the io-pgtable
formats as modules, add a "pre" dependency with MODULE_SOFTDEP() to
ensure that the io-pgtable-arm format module is loaded before loading
the ARM SMMUv3
Apart from the driver data, in order to extend the driver to support more
and more SoCs, we will need to store other configuration data. So, create
a mtk_mmsys struct to encapsulate all that information.
Signed-off-by: CK Hu
Signed-off-by: Enric Balletbo i Serra
Signed-off-by: Yongqiang Niu
The SMMU driver depends on the availability of the ARM LPAE
io-pgtable format code to work properly. In preparation
for having the io-pgtable formats as modules, add a "pre"
dependency with MODULE_SOFTDEP() to ensure that the ARM LPAE
io-pgtable format module is loaded before loading the ARM SMMU
SOLVED
I opened a ticket here:
https://gitlab.freedesktop.org/drm/amd/-/issues/1425
and they suggested, at the end, the same hint (amdgpu.dc=1).
... which, I was sure, I already tried with no results. Maybe I just
misspelled it, and it didn't work.
It's working now, thank you so much for your
This patch add component POSTMASK
Signed-off-by: Yongqiang Niu
---
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
b/include/linux/soc/mediatek/mtk-mmsys.h
index ed99122..13546e9 100644
---
Add devicetree schema for Arm Mali Valhall GPU
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 252 ++
1 file changed, 252 insertions(+)
create mode 100644
Use function call for setting mmsys ovl mout register
Signed-off-by: Yongqiang Niu
---
drivers/soc/mediatek/mmsys/mtk-mmsys.c | 6 ++
include/linux/soc/mediatek/mtk-mmsys.h | 4
2 files changed, 10 insertions(+)
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
The MSM DRM driver depends on the availability of the ARM LPAE io-pgtable
format code to work properly. In preparation for having the io-pgtable
formats as modules, add a "pre" dependency with MODULE_SOFTDEP() to
ensure that the io-pgtable-arm format module is loaded before loading
the MSM DRM
Similar to commit ("drm/amdgpu: fix IH overflow on Vega10 v2")
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR doesn't trigger another memory writeback.
So what can happen is that we end up
It is observed 'use-after-free' on the dmabuf's file->f_inode with the
race between closing the dmabuf file and reading the dmabuf's debug
info.
Consider the below scenario where P1 is closing the dma_buf file
and P2 is reading the dma_buf's debug info in the system:
P1
Hi,
On Tue, Jan 05, 2021 at 12:12:13PM +0800, Huang Rui wrote:
> I am reproducing this issue as well, are you using a Raven board?
I have no clue what Raven is. The workstation I triggered it once on, has:
[7.563968] [drm] radeon kernel modesetting enabled.
[7.581417] [drm] initializing
Hi
Am 05.01.21 um 03:27 schrieb Deepak Rawat:
On Mon, 2021-01-04 at 14:03 +0100, Thomas Zimmermann wrote:
Hi,
I've been looking forward to this patchset. :) The code is really
nice
already.
Thanks Thomas for the review.
+config DRM_HYPERV
+ tristate "DRM Support for hyperv
On Tue, Jan 05, 2021 at 07:08:52PM +0800, Huang Rui wrote:
> Ah, this asic is a bit old and still use radeon driver. So we didn't
> reproduce it on amdgpu driver. I don't have such the old asic in my hand.
> May we know whether this issue can be duplicated after SI which is used
> amdgpu module
Am 04.01.21 um 22:06 schrieb Christian König:
Am 05.01.21 um 00:13 schrieb Lyude Paul:
Recently a regression was introduced which caused TTM's buffer
eviction to
attempt to evict already-pinned BOs, causing issues with buffer eviction
under memory pressure along with suspend/resume:
On Mon, Jan 04, 2021 at 11:27:24AM -0500, Alex Deucher wrote:
> On Tue, Dec 29, 2020 at 8:17 AM Ard Biesheuvel wrote:
> >
> > On Wed, 16 Dec 2020 at 23:26, Ard Biesheuvel wrote:
> > >
> > > On Wed, 16 Dec 2020 at 19:00, Alex Deucher wrote:
> > > >
> > > > On Mon, Dec 14, 2020 at 12:53 PM Ard
On Tue, Jan 05, 2021 at 06:31:38PM +0800, Borislav Petkov wrote:
> Hi,
>
> On Tue, Jan 05, 2021 at 12:12:13PM +0800, Huang Rui wrote:
> > I am reproducing this issue as well, are you using a Raven board?
>
> I have no clue what Raven is. The workstation I triggered it once on, has:
>
> [
From: Lyude Paul
Recently a regression was introduced which caused TTM's buffer eviction to
attempt to evict already-pinned BOs, causing issues with buffer eviction
under memory pressure along with suspend/resume:
nouveau :1f:00.0: DRM: evicting buffers...
nouveau :1f:00.0: DRM:
Hi Philipp,
On Tue, Jan 05, 2021 at 10:32:01AM +0100, Philipp Zabel wrote:
> On Tue, 2021-01-05 at 07:49 +0200, Laurent Pinchart wrote:
> > On Mon, Jan 04, 2021 at 04:30:36PM +0100, Philipp Zabel wrote:
> > > On Sun, 2020-12-20 at 21:50 +0200, Laurent Pinchart wrote:
> > > > Convert the i.MX6
Hi Rob,
On Mon, Jan 04, 2021 at 04:02:53PM -0700, Rob Herring wrote:
> DT properties which can have multiple entries need to specify what the
> entries are and define how many entries there can be. In the case of
> only a single entry, just 'maxItems: 1' is sufficient.
>
> Add the missing entry
Am 05.01.21 um 12:08 schrieb Huang Rui:
On Tue, Jan 05, 2021 at 06:31:38PM +0800, Borislav Petkov wrote:
Hi,
On Tue, Jan 05, 2021 at 12:12:13PM +0800, Huang Rui wrote:
I am reproducing this issue as well, are you using a Raven board?
I have no clue what Raven is. The workstation I triggered
On Mon, Jan 04, 2021 at 04:02:53PM -0700, Rob Herring wrote:
> DT properties which can have multiple entries need to specify what the
> entries are and define how many entries there can be. In the case of
> only a single entry, just 'maxItems: 1' is sufficient.
>
> Add the missing entry
From: Darren Salt
This is to assist driver modules which do BAR resizing.
v2 (chk): Use ilog2 and make the new funtion extra defensive.
Also use the new function on the two existing ocassions.
Signed-off-by: Darren Salt
Signed-off-by: Christian König
---
From: Darren Salt
This allows BAR0 resizing to be done for cards which don't advertise support
for a size large enough to cover the VRAM but which do advertise at least
one size larger than the default. For example, my RX 5600 XT, which
advertises 256MB, 512MB and 1GB.
[v6] (chk) Reduce to only
Otherwise the CPU can't fully access the BAR.
Signed-off-by: Christian König
---
drivers/pci/pci.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 16216186b51c..b66e4703c214 100644
--- a/drivers/pci/pci.c
+++
From: Darren Salt
This is to assist driver modules which do BAR resizing.
Signed-off-by: Darren Salt
---
drivers/pci/pci.c | 1 +
drivers/pci/pci.h | 1 -
include/linux/pci.h | 1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index
Hi Bjorn,
Darren stumbled over an AMD GPU with nonsense in it's resizeable BAR capability
dword.
This is most likely fixable with a VBIOS update, but we already sold quite a
bunch of those boards with the problem.
The driver still loads without this, but the performance isn't the best.
Do
On Thu, Dec 31, 2020 at 10:22:36AM +0800, Xin Ji wrote:
> static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
> {
> return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
> @@ -189,10 +203,64 @@ static int wait_aux_op_finish(struct anx7625_data *ctx)
>
Hi,
> > It's not possible to do page flip with this virtual device. The call to
> > SYNTHVID_VRAM_LOCATION is only honoured once. So unfortunately need to
> > use SHMEM helpers.
>
> I was thinking about using struct video_output_situation.vram_offset; in
> case you want to tinker with that.
Hi
Am 05.01.21 um 12:04 schrieb Gerd Hoffmann:
Hi,
It's not possible to do page flip with this virtual device. The call to
SYNTHVID_VRAM_LOCATION is only honoured once. So unfortunately need to
use SHMEM helpers.
I was thinking about using struct video_output_situation.vram_offset; in
https://bugzilla.kernel.org/show_bug.cgi?id=211043
Bug ID: 211043
Summary: amdgpu: Mouse cursor freeze of external mouse after a
while (after kernel crash?) (KDE Plasma)
Product: Drivers
Version: 2.5
Kernel Version:
BROKEN_GRAPHICS_PROGRAMS is defined when CONFIG_VGA_CONSOLE=y. And
vgacon.c is built exclusively in that case too. So the check for
BROKEN_GRAPHICS_PROGRAMS is pointless in vgacon.c as it is always true.
So remove the test and BROKEN_GRAPHICS_PROGRAMS completely.
This also eliminates the need for
https://bugzilla.kernel.org/show_bug.cgi?id=211033
--- Comment #4 from Oleg Serytsan (oseryt...@gmail.com) ---
Got the same problem with 5.4.86 and AMD RX560.
Reverting the following commit fixed the issue:
https://bugzilla.kernel.org/show_bug.cgi?id=209987
Oleksandr Natalenko (oleksa...@natalenko.name) changed:
What|Removed |Added
CC|
On Tue, Jan 05, 2021 at 07:43:51PM +0800, Borislav Petkov wrote:
> On Tue, Jan 05, 2021 at 07:08:52PM +0800, Huang Rui wrote:
> > Ah, this asic is a bit old and still use radeon driver. So we didn't
> > reproduce it on amdgpu driver. I don't have such the old asic in my hand.
> > May we know
Hi Zhan,
url:
https://github.com/0day-ci/linux/commits/Zhan-Liu/drm-amdgpu-Do-not-change-amdgpu-framebuffer-format-during-page-flip/20201230-051134
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
dea8dcf2a9fa8cc540136a6cd885c3beece16ec3
config:
On Tue, Jan 05, 2021 at 10:40:08AM -0700, Rob Herring wrote:
> On Tue, Jan 05, 2021 at 02:04:14PM +0100, Greg Kroah-Hartman wrote:
> > On Mon, Jan 04, 2021 at 04:02:53PM -0700, Rob Herring wrote:
> > > DT properties which can have multiple entries need to specify what the
> > > entries are and
Going forward the svga device might reuse mmio for general
register accesses, in order to prepare for that we need to
cleanup our naming and handling of fifo specific mmio reads
and writes. As part of this work lets switch to managed
mapping of the fifo mmio to make the error handling cleaner.
Lets try to cleanup the usage of the term FIFO which we used for
both our MMIO based cmd queue processing and for general
command processing which could have been using command buffers
interface. We're going to rename the functions which are processing
commands (and work either via MMIO or command
From: Roland Scheidegger
Reviewed-by: Zack Rusin
Signed-off-by: Roland Scheidegger
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 17b92e6a0f06..f07dec22121c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5739,6 +5739,7 @@ F:
We can't be setting the display_id register to an invalid value
because that makes our device reset the fb which causes nasty
flicker (due to destruction and creation of a new fb).
Also we can't be using the BITS_PER_PIXEL register if the
8BIT_EMULATION is not supported.
Signed-off-by: Zack Rusin
Instead of doing it in multiple spots lets centralize the code
to handle pci resources. This also cleans up the error
handling a bit and will make it a lot easier to add additional
svga versions to the driver.
Signed-off-by: Zack Rusin
Reviewed-by: Martin Krastev
Reviewed-by: Roland Scheidegger
Throttling was used before fencing to implement early vsync
support in the xorg state tracker a long time ago. The xorg
state tracker has been removed years ago and no one else
has ever used throttling. It's time to remove this code,
it hasn't been used or tested in years.
Signed-off-by: Zack
I've been off in December and just now I finally rebased those on top
drm-misc-next. I'd like to move our developlement to drm-misc so
getting commit rights to drm-misc for both me and Roland would be great
("zack" and "sroland" accounts on fdo).
Roland Scheidegger (1):
drm/vmwgfx: add Zack
Before drm got helpers for removing conflicting pci framebuffer devices
we implemented something known as "stealth" mode which allowed vmwgfx
to run even if it couldn't reserve pci resources. We can just switch
to regular drm helpers instead of keeping the stealth mode alive as
it makes our code a
To cleanup some of the error handling and prepare for some
other work lets switch to a managed drm device. It will
let us get a better handle on some of the error paths.
Signed-off-by: Zack Rusin
Reviewed-by: Martin Krastev
Reviewed-by: Roland Scheidegger
---
Hi Christian,
url:
https://github.com/0day-ci/linux/commits/Christian-K-nig/pci-export-pci_rebar_get_possible_sizes/20210105-224446
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-m001-20210105 (attached as .config)
compiler: gcc-9
Drivers are not supposed to use this directly any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_pool.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
index c81e6eb72da1..9089a047cb51 100644
---
Drivers are not supposed to init the page pool directly any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/radeon_ttm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index
Am 05.01.21 um 17:11 schrieb Ilia Mirkin:
On Tue, Jan 5, 2021 at 8:44 AM Christian König
wrote:
Otherwise the CPU can't fully access the BAR.
Signed-off-by: Christian König
---
drivers/pci/pci.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c
https://bugzilla.kernel.org/show_bug.cgi?id=211043
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC|
On Tue, Jan 05, 2021 at 02:04:14PM +0100, Greg Kroah-Hartman wrote:
> On Mon, Jan 04, 2021 at 04:02:53PM -0700, Rob Herring wrote:
> > DT properties which can have multiple entries need to specify what the
> > entries are and define how many entries there can be. In the case of
> > only a single
Reviewed-by: Lyude Paul
Guessing it's fine if I push this with your sob and review added?
On Tue, 2021-01-05 at 12:45 +0100, Christian König wrote:
> From: Lyude Paul
>
> Recently a regression was introduced which caused TTM's buffer eviction to
> attempt to evict already-pinned BOs, causing
-base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Christian-K-nig/pci-export-pci_rebar_get_possible_sizes/20210105-224446
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm64-randconfig-r006-202
Am 05.01.21 um 19:12 schrieb Lyude Paul:
Reviewed-by: Lyude Paul
Guessing it's fine if I push this with your sob and review added?
Works for me, just take care that you pick the right branch.
I always seem to push my stuff into the wrong one.
Christian.
On Tue, 2021-01-05 at 12:45
On Tue, Jan 5, 2021 at 8:44 AM Christian König
wrote:
>
> Otherwise the CPU can't fully access the BAR.
>
> Signed-off-by: Christian König
> ---
> drivers/pci/pci.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index
On Tue, Jan 5, 2021 at 8:05 AM Will Deacon wrote:
>
> On Mon, Jan 04, 2021 at 11:27:24AM -0500, Alex Deucher wrote:
> > On Tue, Dec 29, 2020 at 8:17 AM Ard Biesheuvel wrote:
> > >
> > > On Wed, 16 Dec 2020 at 23:26, Ard Biesheuvel wrote:
> > > >
> > > > On Wed, 16 Dec 2020 at 19:00, Alex
Hi,
On Wed 23 Dec 20, 18:31, Ilia Mirkin wrote:
> FWIW this is something I added, hoping it was going to get used at
> some point, but I never followed up with support in xf86-video-nouveau
> for Xv. At this point, I'm not sure I ever will. I encoded the
> "enabled" part into the value with a
On Mon, Dec 28, 2020 at 06:49:16PM +0300, Dmitry Osipenko wrote:
> Add modularization support to the Tegra124 EMC driver, which now can be
> compiled as a loadable kernel module.
>
> Note that EMC clock must be registered at clk-init time, otherwise PLLM
> will be disabled as unused clock at boot
Am 05.01.21 um 17:06 schrieb Defang Bo:
Similar to commit ("drm/amdgpu: fix IH overflow on Vega10 v2").
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR doesn't trigger another memory
Currently, data for the device instance is held by vkms_device.
Add a separate type, vkms_config to contain configuration details
for the device and various modes to be later used by configfs.
This config data stays constant once the device is created.
Accordingly, add vkms_create and
On Mon, Dec 28, 2020 at 06:49:18PM +0300, Dmitry Osipenko wrote:
> Now Internal and External memory controllers are memory interconnection
> providers. This allows us to use interconnect API for tuning of memory
> configuration. EMC driver now supports OPPs and DVFS.
>
> Tested-by: Nicolas
Am 05.01.21 um 13:20 schrieb Huang Rui:
On Tue, Jan 05, 2021 at 07:43:51PM +0800, Borislav Petkov wrote:
On Tue, Jan 05, 2021 at 07:08:52PM +0800, Huang Rui wrote:
Ah, this asic is a bit old and still use radeon driver. So we didn't
reproduce it on amdgpu driver. I don't have such the old asic
On Thu, Dec 17, 2020 at 09:05:50PM +0300, Dmitry Osipenko wrote:
> Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
> power consumption and heating of the Tegra chips. Tegra SoC has multiple
> hardware units which belong to a core power domain of the SoC and share
> the
On 01/01/2021 16:54, Yangtao Li wrote:
Use devm_pm_opp_* API to simplify code, and remove opp_table
from panfrost_devfreq.
Signed-off-by: Yangtao Li
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 ++---
On Mon, Dec 28, 2020 at 06:49:17PM +0300, Dmitry Osipenko wrote:
> EMC driver will become mandatory after turning it into interconnect
> provider because interconnect users, like display controller driver, will
> fail to probe using newer device-trees that have interconnect properties.
> Thus make
On 11/23/20 3:01 AM, Christian König wrote:
Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky:
On 11/21/20 9:15 AM, Christian König wrote:
Am 21.11.20 um 06:21 schrieb Andrey Grodzovsky:
Will be used to reroute CPU mapped BO's page faults once
device is removed.
Uff, one page for each
https://bugzilla.kernel.org/show_bug.cgi?id=211033
Mike Old (south.of.hea...@gmx.at) changed:
What|Removed |Added
CC|
On Wed, 2020-12-23 at 18:37 +0200, Jani Nikula wrote:
> On Fri, 04 Dec 2020, Lyude Paul wrote:
> > Currently, every different type of backlight hook that i915 supports is
> > pretty straight forward - you have a backlight, probably through PWM
> > (but maybe DPCD), with a single set of
Hi Yangtao,
On Tue, Jan 5, 2021 at 1:13 PM Chanwoo Choi wrote:
>
> On Sun, Jan 3, 2021 at 12:58 PM Yangtao Li wrote:
> >
> > Use devm_pm_opp_* API to simplify code.
> >
> > Signed-off-by: Yangtao Li
> > ---
> > drivers/devfreq/imx8m-ddrc.c | 15 ++-
> > 1 file changed, 2
FDO is out of space, so move to gitlab.
Signed-off-by: Alex Deucher
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index eb18459c1d16..e2877be6b10d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -907,7 +907,7 @@ AMD KFD
M:
https://bugzilla.kernel.org/show_bug.cgi?id=210849
--- Comment #9 from xrootw...@gmail.com ---
'no_console_suspend' in boot options fix problem absolutely in my case. maybe
this is temporally fix, but i hope it will be fixed normally.
--
You may reply to this email to add a comment.
You are
Hi Rob,
On Tue, Jan 5, 2021 at 8:03 AM Rob Herring wrote:
>
> DT properties which can have multiple entries need to specify what the
> entries are and define how many entries there can be. In the case of
> only a single entry, just 'maxItems: 1' is sufficient.
>
> Add the missing entry
1 - 100 of 112 matches
Mail list logo
