This is an initial patch series to move discrete memory management over to
TTM. It will be followed up shortly with adding more functionality.
The buddy allocator is temporarily removed along with its selftests and
It is replaced with the TTM range manager and some selftests are adjusted
to
[AMD Official Use Only]
>-Original Message-
>From: Koenig, Christian
>Sent: Monday, May 31, 2021 7:55 PM
>To: Yu, Lang ; amd-...@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Thomas Hellströ ; Olsak, Marek
>; Huang, Ray ; Deucher,
>Alexander
>Subject: Re: [PATCH v2
On 5/31/21 2:36 PM, Christian König wrote:
Am 31.05.21 um 14:19 schrieb Thomas Hellström:
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() /
On 5/13/2021 10:44 PM, Jonathan Marek wrote:
Add adreno_is_{a660,a650_family} helpers and convert update existing
adreno_is_a650 usage based on downstream driver's logic (changing into
adreno_is_a650_family or adding adreno_is_a660).
And add the remaining changes required for A660, again based
On 5/31/21 2:19 PM, Thomas Hellström wrote:
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we
On Mon, 31 May 2021 at 17:58, Bjorn Andersson
wrote:
>
> On Wed 07 Apr 10:01 CDT 2021, Dmitry Baryshkov wrote:
>
> > Move the bus clock to mdp device node,in order to facilitate bus band
> > width scaling on sm8250 target.
> >
> > The parent device MDSS will not vote for bus bw, instead the vote
ping
在 2021/5/15 17:01, Baokun Li 写道:
From: "libaok...@huawei.com"
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/nouveau/dispnv50/disp.c: In function 'nv50_mstm_cleanup':
drivers/gpu/drm/nouveau/dispnv50/disp.c:1389:6: warning:
variable ‘ret’ set but not used
On Thu, May 27, 2021 at 11:26:46AM -0500, Jason Ekstrand wrote:
> When the APIs were added to manage VMs more directly from userspace, the
> questionable choice was made to allow changing out the VM on a context
> at any time. This is horribly racy and there's absolutely no reason why
> any
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
v2: move the check outside of for loop
Signed-off-by: Lang Yu
---
drivers/gpu/drm/ttm/ttm_bo.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
[AMD Official Use Only]
>-Original Message-
>From: Koenig, Christian
>Sent: Monday, May 31, 2021 8:49 PM
>To: Yu, Lang ; amd-...@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Thomas Hellströ ; Olsak, Marek
>; Huang, Ray ; Deucher,
>Alexander
>Subject: Re: [PATCH v2
On 5/31/21 12:56 PM, Christian König wrote:
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu
Am 31.05.21 um 14:19 schrieb Thomas Hellström:
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts
On 2021-05-20 4:18 p.m., Daniel Vetter wrote:
> On Thu, May 20, 2021 at 10:13:38AM +0200, Michel Dänzer wrote:
>> On 2021-05-20 9:55 a.m., Daniel Vetter wrote:
>>> On Wed, May 19, 2021 at 5:48 PM Michel Dänzer wrote:
On 2021-05-19 5:21 p.m., Jason Ekstrand wrote:
> On Wed, May 19,
On which branch are you working? I have problems applying that one to
amd-staging-drm-next.
Christian.
Am 31.05.21 um 10:22 schrieb Lang Yu:
Currently, we have a limitted GTT memory size and need a bounce buffer
when doing buffer migration between VRAM and SYSTEM domain.
The problem is under
On Wed 07 Apr 10:01 CDT 2021, Dmitry Baryshkov wrote:
> Move the bus clock to mdp device node,in order to facilitate bus band
> width scaling on sm8250 target.
>
> The parent device MDSS will not vote for bus bw, instead the vote will
> be triggered by mdp device node. Since a minimum vote is
Am 31.05.21 um 13:30 schrieb Lang Yu:
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
v2: move the check outside of for loop
Signed-off-by: Lang Yu
In general those patches now have my rb, but let me add some more
documentation to them to better explain
On 5/31/21 2:02 PM, Christian König wrote:
Am 31.05.21 um 13:19 schrieb Thomas Hellström (Intel):
On 5/31/21 12:56 PM, Christian König wrote:
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström
Hi Patrice
On Mon, May 31, 2021 at 9:51 PM Patrice CHOTARD
wrote:
>
>
>
> On 5/31/21 3:38 PM, Dillon Min wrote:
> > Hi Patrice
> >
> > Thanks for your time to test my patch.
> >
> > On Mon, May 31, 2021 at 9:20 PM Patrice CHOTARD
> > wrote:
> >>
> >> Hi Dillon
> >>
> >>
> >>
> >> On 5/14/21
On Fri 28 May 10:33 CDT 2021, Dmitry Baryshkov wrote:
> On 07/04/2021 18:01, Dmitry Baryshkov wrote:
> > Move the bus clock to mdp device node,in order to facilitate bus band
> > width scaling on sdm845 target.
> >
> > The parent device MDSS will not vote for bus bw, instead the vote will
> > be
This is an initial patch series to move discrete memory management over to
TTM. It will be followed up shortly with adding more functionality.
The buddy allocator is temporarily removed along with its selftests and
It is replaced with the TTM range manager and some selftests are adjusted
to
Am 31.05.21 um 14:19 schrieb Thomas Hellström:
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with
Added r-b tag and merged to drm-misc next.
https://cgit.freedesktop.org/drm/drm-misc/log/?h=drm-misc-next
Thanks for the submission, and sorry about making you jump through all
those hoops.
On Mon, 31 May 2021 at 15:47, Yu Kuai wrote:
>
> pm_runtime_get_sync will increment pm usage counter
On Thu, May 27, 2021 at 11:26:50AM -0500, Jason Ekstrand wrote:
> Now that we have the whole engine set and VM at context creation time,
> we can just assign those fields instead of creating first and handling
> the VM and engines later. This lets us avoid creating useless VMs and
> engine sets
On 5/13/2021 10:44 PM, Jonathan Marek wrote:
Accept all SQE firmware versions for A660.
Re-organize the function a bit and print an error message for unexpected
GPU IDs instead of failing silently.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36
On Mon, May 31, 2021 at 9:15 PM Patrice CHOTARD
wrote:
>
> Hi Dillon
>
> When trying to applying this patch using "git am --3 " i got this
> error :
>
> error: cannot convert from y to UTF-8
> fatal: could not parse patch
>
> Whereas i got no similar error with the other patch 2/3 and 4.
>
> I
On Thu, May 27, 2021 at 11:26:47AM -0500, Jason Ekstrand wrote:
> When the APIs were added to manage the engine set on a GEM context
> directly from userspace, the questionable choice was made to allow
> changing the engine set on a context at any time. This is horribly racy
> and there's
On 5/13/2021 10:44 PM, Jonathan Marek wrote:
Add a660 hwcg table, ported over from downstream.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
Am 31.05.21 um 13:19 schrieb Thomas Hellström (Intel):
On 5/31/21 12:56 PM, Christian König wrote:
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu,
Temporarily remove the buddy allocator and related selftests
and hook up the TTM range manager for i915 regions.
Also modify the mock region selftests somewhat to account for a
fragmenting manager.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld #v2
---
v2:
- Fix an error unwind in
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fault().
Instead, implement a method mapping
Since objects can be migrated or evicted when not pinned or locked,
update the checks for lmem residency or future residency so that
the value returned is not immediately stale.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2: Simplify i915_gem_object_migratable() (Reported by
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other drivers as well.
Add an eviction_valuable call
From: Maarten Lankhorst
The platform should exclusively use mmap_offset, one less path to worry
about for discrete.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality like delayed delete and LRU list manipulation.
Initially we support only LMEM and SYSTEM memory, but SYSTEM
(which in this case means evicted LMEM
From: Maarten Lankhorst
This allows drivers to distinguish between different types of vma_node's.
The readonly flag was unused and is thus removed.
This is a temporary solution, until i915 is converted completely to
use ttm for bo's.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we slightly
need to massage the mmap handlers to
Embed a struct ttm_buffer_object into the i915 gem object, making sure
we alias the gem object part. It's a bit unfortunate that the
struct ttm_buffer_ojbect embeds a gem object since we otherwise could
make the TTM part private to the TTM backend, and use the usual
i915 gem object for the other
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts to use a fast prefetching memcpy and
otherwise falls
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König #v4
--
v4:
- Clarify when we try drm_memcpy_from_wc_dbm (Reported by Matthew Auld)
- Be paranoid about when
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulnerable to user-space
triggered kernel BUGs if the
Any sleeping dma_resv lock taken while the vma pages_mutex is held
will cause a lockdep splat.
Move the i915_gem_object_pin_pages() call out of the pages_mutex
critical section.
Signed-off-by: Thomas Hellström
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_vma.c | 29
All users of this function actually want the dma segment sizes, but that's
not what's calculated. Fix that and rename the function to
i915_sg_dma_sizes to reflect what's calculated.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2
We are currently sharing the VM reservation locks across a number of
gem objects with page-table memory. Since TTM will individiualize the
reservation locks when freeing objects, including accessing the shared
locks, make sure that the shared locks are not freed until that is done.
For PPGTT we
Add support for v2.5.0 DSI block in the SC7280 SoC.
Signed-off-by: Rajeev Nandan
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 20
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
Add YAML schema for the device tree bindings for MSM 7nm DSI PHY driver.
Cc: Jonathan Marek
Signed-off-by: Rajeev Nandan
---
.../bindings/display/msm/dsi-phy-7nm.yaml | 68 ++
1 file changed, 68 insertions(+)
create mode 100644
Changes in this series add support for MSM display DSI CTRL & PHY drivers
for the SC7280 SoC, which has DSI controller v2.5.0 and DSI PHY v4.1.
This series also updates the missing bindings (yaml) for the 7nm DSI PHY
driver on "msm-next" branch.
Rajeev Nandan (3):
dt-bindings: msm/dsi: Add
The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver with
different enable|disable regulator loads.
Signed-off-by: Rajeev Nandan
---
drivers/gpu/drm/msm/Kconfig | 6 +++---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
On Fri, May 28, 2021 at 12:32 AM Tom Lendacky wrote:
>
> On 5/27/21 9:41 AM, Tom Lendacky wrote:
> > On 5/27/21 8:02 AM, Christoph Hellwig wrote:
> >> On Wed, May 19, 2021 at 11:50:07AM -0700, Florian Fainelli wrote:
> >>> You convert this call site with swiotlb_init_io_tlb_mem() which did not
>
On Thursday, May 20th, 2021 at 10:17 AM, Pekka Paalanen
wrote:
> I think adding "for all drivers" would make things much more clear,
> like in the other cases you mention "atomic-capable drivers".
Good point, done.
> > @@ -797,6 +802,13 @@ struct drm_get_cap {
> > * If set to 1, the DRM
Am 12.05.21 um 19:59 schrieb Alex Deucher:
> On Wed, May 12, 2021 at 9:04 AM Ville Syrjälä
> wrote:
>> On Wed, May 12, 2021 at 02:06:56PM +0200, Werner Sembach wrote:
>>> Hello,
>>>
>>> In addition to the existing "max bpc", and "Broadcast RGB/output_csc" drm
>>> properties I propose 4 new
On 31/05/2021 17:42, Bjorn Andersson wrote:
On Fri 28 May 10:33 CDT 2021, Dmitry Baryshkov wrote:
On 07/04/2021 18:01, Dmitry Baryshkov wrote:
Move the bus clock to mdp device node,in order to facilitate bus band
width scaling on sdm845 target.
The parent device MDSS will not vote for bus
31.05.2021 17:13, Thierry Reding пишет:
> On Tue, May 11, 2021 at 02:27:08AM +0300, Dmitry Osipenko wrote:
>> Display controller (DC) performs isochronous memory transfers, and thus,
>> has a requirement for a minimum memory bandwidth that shall be fulfilled,
>> otherwise framebuffer data can't be
Hi Patrice
On Mon, May 31, 2021 at 9:39 PM Dillon Min wrote:
>
> On Mon, May 31, 2021 at 9:15 PM Patrice CHOTARD
> wrote:
> >
> > Hi Dillon
> >
> > When trying to applying this patch using "git am --3 " i got this
> > error :
> >
> > error: cannot convert from y to UTF-8
> > fatal: could not
This patch series is for making the GPD Win Max display usable with
Linux.
The GPD Win Max is a small laptop, and its eDP panel does not send an
EDID over DPCD; the EDID is instead available in the intel opregion, in
mailbox #5 [1]
The first patch is based on Jani's patch series [2] adding
The ACPI OpRegion Mailbox #5 ASLE extension may contain an EDID to be
used for the embedded display. Add support for using it via by adding
the EDID to the list of available modes on the connector, and use it for
eDP when available.
If a panel's EDID is broken, there may be an override EDID set
Panel is 800x1280, but mounted on a laptop form factor, sideways.
Reviewed-by: Hans de Goede
Signed-off-by: Anisse Astier
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c
Hi Dillon
When trying to applying this patch using "git am --3 " i got this error
:
error: cannot convert from y to UTF-8
fatal: could not parse patch
Whereas i got no similar error with the other patch 2/3 and 4.
I find a way to apply it anyway.
Patrice
On 5/14/21 1:02 PM,
On 5/31/21 3:38 PM, Dillon Min wrote:
> Hi Patrice
>
> Thanks for your time to test my patch.
>
> On Mon, May 31, 2021 at 9:20 PM Patrice CHOTARD
> wrote:
>>
>> Hi Dillon
>>
>>
>>
>> On 5/14/21 1:02 PM, dillon.min...@gmail.com wrote:
>>> From: Dillon Min
>>>
>>> This seriese fix three
Hi!
Dne petek, 28. maj 2021 ob 22:30:35 CEST je Roman Stratiienko napisal(a):
> Create callback to allow updating engine's registers on mode change.
>
> Signed-off-by: Roman Stratiienko
> Reviewed-by: Jernej Skrabec
> ---
> drivers/gpu/drm/sun4i/sun4i_crtc.c | 3 +++
>
Hi!
General note, you should send Allwinner specific patches to linux-
su...@lists.linux.dev too. It's already in MAINTAINERS, but probably it's not
yet propagated in all trees.
Dne petek, 28. maj 2021 ob 22:30:36 CEST je Roman Stratiienko napisal(a):
> Fixes corrupted display picture when
Hi Dillon
On 5/14/21 1:02 PM, dillon.min...@gmail.com wrote:
> From: Dillon Min
>
> This seriese fix three i2c/clk bug for stm32 f4/f7
> - kernel runing in sdram, i2c driver get data timeout
> - ltdc clk turn off after kernel console active
> - kernel hang in set ltdc clock rate
>
> clk bug
Hi Dillon
On 5/31/21 4:29 PM, Dillon Min wrote:
> Hi Patrice
>
> On Mon, May 31, 2021 at 9:51 PM Patrice CHOTARD
> wrote:
>>
>>
>>
>> On 5/31/21 3:38 PM, Dillon Min wrote:
>>> Hi Patrice
>>>
>>> Thanks for your time to test my patch.
>>>
>>> On Mon, May 31, 2021 at 9:20 PM Patrice CHOTARD
>>>
On Fri, May 28, 2021 at 11:30:35PM +0300, Roman Stratiienko wrote:
> Create callback to allow updating engine's registers on mode change.
>
> Signed-off-by: Roman Stratiienko
> Reviewed-by: Jernej Skrabec
> ---
> drivers/gpu/drm/sun4i/sun4i_crtc.c | 3 +++
>
Dne ponedeljek, 31. maj 2021 ob 19:24:40 CEST je Jernej Škrabec napisal(a):
> Hi!
>
> Dne petek, 28. maj 2021 ob 22:30:35 CEST je Roman Stratiienko napisal(a):
> > Create callback to allow updating engine's registers on mode change.
> >
> > Signed-off-by: Roman Stratiienko
> > Reviewed-by:
Am 19.05.21 um 15:49 schrieb Ville Syrjälä:
> On Wed, May 19, 2021 at 12:34:05PM +0300, Pekka Paalanen wrote:
>> On Wed, 12 May 2021 16:04:16 +0300
>> Ville Syrjälä wrote:
>>
>>> On Wed, May 12, 2021 at 02:06:56PM +0200, Werner Sembach wrote:
Hello,
In addition to the existing "max
Hi all,
After merging the i2c tree, today's linux-next build (x86_64 allmodconfig)
failed like this:
In file included from drivers/gpu/drm/i915/i915_gem.c:1250:
drivers/gpu/drm/i915/selftests/i915_gem.c:97:13: error: conflicting types for
'pm_suspend'
97 | static void pm_suspend(struct
On 31/05/2021 16:33, Rajeev Nandan wrote:
The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver with
different enable|disable regulator loads.
Signed-off-by: Rajeev Nandan
---
drivers/gpu/drm/msm/Kconfig | 6 +++---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
On 31/05/2021 16:33, Rajeev Nandan wrote:
Add support for v2.5.0 DSI block in the SC7280 SoC.
Signed-off-by: Rajeev Nandan
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 20
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 21
On 28/05/2021 15:57, Jonathan Marek wrote:
On 5/3/21 1:11 PM, Rob Herring wrote:
On Fri, Apr 23, 2021 at 01:24:40PM -0400, Jonathan Marek wrote:
Document qcom,dsi-phy-cphy-mode option, which can be used to control
whether DSI will operate in D-PHY (default) or C-PHY mode.
Given this is a
Hi Patrice
On Mon, May 31, 2021 at 10:58 PM Patrice CHOTARD
wrote:
>
> Hi Dillon
>
> On 5/31/21 4:29 PM, Dillon Min wrote:
> > Hi Patrice
> >
> > On Mon, May 31, 2021 at 9:51 PM Patrice CHOTARD
> > wrote:
> >>
> >>
> >>
> >> On 5/31/21 3:38 PM, Dillon Min wrote:
> >>> Hi Patrice
> >>>
> >>>
This series adds memory bandwidth management to the NVIDIA Tegra DRM driver,
which is done using interconnect framework. It fixes display corruption that
happens due to insufficient memory bandwidth.
Changelog:
v18: - Moved total peak bandwidth from CRTC state to plane state and removed
Display controller (DC) performs isochronous memory transfers, and thus,
has a requirement for a minimum memory bandwidth that shall be fulfilled,
otherwise framebuffer data can't be fetched fast enough and this results
in a DC's data-FIFO underflow that follows by a visual corruption.
The Memory
It's useful to know the total number of underflow events and currently
the debug stats are getting reset each time CRTC is being disabled. Let's
account the overall number of events that doesn't get a reset.
Reviewed-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
Hi Patrice
Thanks for your time to test my patch.
On Mon, May 31, 2021 at 9:20 PM Patrice CHOTARD
wrote:
>
> Hi Dillon
>
>
>
> On 5/14/21 1:02 PM, dillon.min...@gmail.com wrote:
> > From: Dillon Min
> >
> > This seriese fix three i2c/clk bug for stm32 f4/f7
> > - kernel runing in sdram, i2c
On 2021/05/31 18:54, Robert Foss wrote:
Hey Yu,
I'm not finding your this patch with the correct tags. I'd expect the subject:
[PATCH v2] drm: bridge: cdns-mhdp8546: Fix PM reference leak in
cdns_mhdp_probe()
Can you please resubmit using this title, just to be sure I merge the
right version
pm_runtime_get_sync will increment pm usage counter even it failed.
Forgetting to putting operation will result in reference leak here.
Fix it by replacing it with pm_runtime_resume_and_get to keep usage
counter balanced.
Reported-by: Hulk Robot
Signed-off-by: Yu Kuai
---
changes in V2:
-
On Tue, May 11, 2021 at 02:27:08AM +0300, Dmitry Osipenko wrote:
> Display controller (DC) performs isochronous memory transfers, and thus,
> has a requirement for a minimum memory bandwidth that shall be fulfilled,
> otherwise framebuffer data can't be fetched fast enough and this results
> in a
Embed a struct ttm_buffer_object into the i915 gem object, making sure
we alias the gem object part. It's a bit unfortunate that the
struct ttm_buffer_ojbect embeds a gem object since we otherwise could
make the TTM part private to the TTM backend, and use the usual
i915 gem object for the other
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König #v4
--
v4:
- Clarify when we try drm_memcpy_from_wc_dbm (Reported by Matthew Auld)
- Be paranoid about when
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fault().
Instead, implement a method mapping
Since objects can be migrated or evicted when not pinned or locked,
update the checks for lmem residency or future residency so that
the value returned is not immediately stale.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2: Simplify i915_gem_object_migratable() (Reported by
From: Maarten Lankhorst
The platform should exclusively use mmap_offset, one less path to worry
about for discrete.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
From: Maarten Lankhorst
This allows drivers to distinguish between different types of vma_node's.
The readonly flag was unused and is thus removed.
This is a temporary solution, until i915 is converted completely to
use ttm for bo's.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we slightly
need to massage the mmap handlers to
All users of this function actually want the dma segment sizes, but that's
not what's calculated. Fix that and rename the function to
i915_sg_dma_sizes to reflect what's calculated.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2
We are currently sharing the VM reservation locks across a number of
gem objects with page-table memory. Since TTM will individiualize the
reservation locks when freeing objects, including accessing the shared
locks, make sure that the shared locks are not freed until that is done.
For PPGTT we
Any sleeping dma_resv lock taken while the vma pages_mutex is held
will cause a lockdep splat.
Move the i915_gem_object_pin_pages() call out of the pages_mutex
critical section.
Signed-off-by: Thomas Hellström
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_vma.c | 29
Temporarily remove the buddy allocator and related selftests
and hook up the TTM range manager for i915 regions.
Also modify the mock region selftests somewhat to account for a
fragmenting manager.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld #v2
---
v2:
- Fix an error unwind in
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality like delayed delete and LRU list manipulation.
Initially we support only LMEM and SYSTEM memory, but SYSTEM
(which in this case means evicted LMEM
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts to use a fast prefetching memcpy and
otherwise falls
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulnerable to user-space
triggered kernel BUGs if the
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other drivers as well.
Add an eviction_valuable call
HEAD~2 punted on merging DRM_DEBUG_KMS_RATELIMITED; clean that up now,
removing the extra macro indirections which support !KMS cases, since
only _KMS_RATELIMITED is used. They can be re-added once needed.
conflict was here:
c5261e93758a drm/print: Fixup DRM_DEBUG_KMS_RATELIMITED()
hi everyone,
this patchset reworks the drm.debug controlled debug categories,
and remaps them to use dynamic_debug_exec_queries().
To do this "smoothly", DRM_UT_* is converted from an enum to a
class-prefix string, which is prepended## to the real format string.
This lets us use:
$> echo
drm's debug system uses distinct categories of debug messages, mapped
to bits in drm.debug. Currently, code does a lot of unlikely bit-mask
checks on drm.debug (in drm_debug_enabled), we can use dynamic debug
instead, and get all that jump_label goodness.
RFC: dynamic debug has no concept of
s/prink/printk/ - no functional changes
Signed-off-by: Jim Cromie
---
include/drm/drm_print.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index a3c58c941bdc..9377a17d74f1 100644
--- a/include/drm/drm_print.h
+++
The gvt component of this driver has ~120 pr_debugs, in 9 "classes".
Following model of drm.debug, add a parameter to map bits to these
classes.
In Makefile, add DYNAMIC_DEBUG_MODULE if CONFIG_DRM_USE_DYNAMIC_DEBUG.
In i915_params.c, add callback to map bits to queries.
TBD: consider moving the
On 5/13/2021 10:43 PM, Jonathan Marek wrote:
SM8250 AOP firmware already sets up PDC registers for us, and it only needs
to be enabled. This path will be used for other newer GPUs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 -
1 file
On 5/13/2021 10:43 PM, Jonathan Marek wrote:
These aren't used by anything anymore.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/msm_gpu.h | 9 -
2 files changed, 12 deletions(-)
diff --git
On 5/13/2021 10:43 PM, Jonathan Marek wrote:
Value was shifted in the wrong direction, resulting in the field always
being zero, which is incorrect for A650.
Fixes: d0bac4e9cd66 ("drm/msm/a6xx: set ubwc config for A640 and A650")
Signed-off-by: Jonathan Marek
---
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