Quoting Dmitry Baryshkov (2021-10-05 23:10:22)
> On Wed, 6 Oct 2021 at 07:26, Stephen Boyd wrote:
> >
> > Quoting Bjorn Andersson (2021-10-05 19:37:52)
> > > On Tue 05 Oct 19:06 PDT 2021, Stephen Boyd wrote:
> > >
> > > > Quoting Bjorn Andersson (2021-10-05 18:43:16)
> > > > > On Tue 05 Oct 17:43
Hi Randy,
On Tue, 5 Oct 2021 22:48:03 -0700 Randy Dunlap wrote:
>
> on i386:
>
> ld: drivers/gpu/drm/msm/hdmi/hdmi_phy.o:(.rodata+0x3f0): undefined reference
> to `msm_hdmi_phy_8996_cfg'
>
>
> Full randconfig fle is attached.
This would be because CONFIG_DRM_MSM is set but CONFIG_COMMON_CLOC
On 10/5/21 20:24, Matthew Auld wrote:
We already do this when mapping the pages.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 -
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 1 -
2 files changed, 2 deletions(-)
Reviewed-by: Thomas Hellström
On 10/5/21 20:24, Matthew Auld wrote:
The comment here is no longer accurate, since the current shrinker code
requires a full ref before touching any objects. Also unset_pages()
should already do the required make_unshrinkable() for us, if needed,
which is also nicely balanced with set_pages().
On 10/5/21 20:24, Matthew Auld wrote:
Attempt to document shrink_pin and the other relevant interfaces that
interact with it, before we start messing with it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_object_types
On 10/5/21 20:24, Matthew Auld wrote:
We currently just evict lmem objects to system memory when under memory
pressure. For this case we might lack the usual object mm.pages, which
effectively hides the pages from the i915-gem shrinker, until we
actually "attach" the TT to the object, or in the
Hi,
On 23/09/2021 09:06, Neil Armstrong wrote:
> This patchset is the follow-up the v4 patchset from Benoit Parrot at [1].
>
> This patch series adds virtual-plane support to omapdrm driver to allow the
> use
> of display wider than 2048 pixels.
>
> In order to do so we introduce the concept of
On 06/10/2021 00:14, Matthew Brost wrote:
On Tue, Oct 05, 2021 at 10:47:11AM -0700, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to th
Good morning, could I get an rb for that patch here as well?
I've pushed the first few with Daniel's and your rbs, but this one here
is blocking all the rest.
Thanks,
Christian.
Am 05.10.21 um 13:37 schrieb Christian König:
A simpler version of the iterator to be used when the dma_resv objec
Hello,
When using Healer to fuzz the latest Linux kernel, the following crash
was triggered.
HEAD commit: 0513e464f900 Merge tag 'perf-tools-fixes-for-v5.15-2021-09-27'
git tree: upstream
console output:
https://drive.google.com/file/d/1xw1nX3KSXOI0GzbKjGw5c0C14We3e0R3/view?usp=sharing
kernel con
On 05/10/2021 12:37, Christian König wrote:
A simpler version of the iterator to be used when the dma_resv object is
locked.
v2: fix index check here as well
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 49 ++
include/linux/dma-resv.h
On 06/10/2021 09:40, Tvrtko Ursulin wrote:
On 05/10/2021 12:37, Christian König wrote:
A simpler version of the iterator to be used when the dma_resv object is
locked.
v2: fix index check here as well
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 49
On 10/6/2021 8:59 AM, Christian König wrote:
Am 06.10.21 um 08:55 schrieb Lazar, Lijo:
On 10/6/2021 12:05 PM, Christian König wrote:
Am 06.10.21 um 08:32 schrieb Lazar, Lijo:
On 10/6/2021 11:49 AM, Christian König wrote:
Am 06.10.21 um 06:51 schrieb Lazar, Lijo:
On 10/5/2021 10:15 PM
Hello,
When using Healer to fuzz the latest Linux kernel, the following crash
was triggered.
HEAD commit: 42d43c92fc57 Merge branch 'for-linus'
git tree: upstream
console output:
https://drive.google.com/file/d/1TXbZJ5Reefwpvr_wk3N1rGVKIMnF6fbP/view?usp=sharing
kernel config:
https://drive.goog
On 05/10/2021 18:47, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to the user, GuC shares this info
with i915 for all engines using sha
From: Thomas Hellström
Break out some shmem backend utils for future reuse by the TTM backend:
shmem_alloc_st(), shmem_free_st() and __shmem_writeback() which we can
use to provide a shmem-backed TTM page pool for cached-only TTM
buffer objects.
Main functional change here is that we now compute
We already do this when mapping the pages.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 -
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt
The comment here is no longer accurate, since the current shrinker code
requires a full ref before touching any objects. Also unset_pages()
should already do the required make_unshrinkable() for us, if needed,
which is also nicely balanced with set_pages().
Signed-off-by: Matthew Auld
Cc: Thomas
For cached objects we can allocate our pages directly in shmem. This
should make it possible(in a later patch) to utilise the existing
i915-gem shrinker code for such objects. For now this is still disabled.
v2(Thomas):
- Add optional try_to_writeback hook for objects. Importantly we need
to
From: Laurent Pinchart
The SN65DSI8x EN signal may be tied to VCC, or otherwise controlled by
means not available to the kernel. Make the GPIO optional.
Signed-off-by: Laurent Pinchart
---
.../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 1 -
1 file changed, 1 deletion(-)
di
Attempt to document shrink_pin and the other relevant interfaces that
interact with it, before we start messing with it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 24 +-
drivers/gpu/drm/i915/ge
We currently just evict lmem objects to system memory when under memory
pressure. For this case we might lack the usual object mm.pages, which
effectively hides the pages from the i915-gem shrinker, until we
actually "attach" the TT to the object, or in the case of lmem-only
objects it just gets mi
This should let us do an accelerated copy directly to the shmem pages
when temporarily moving lmem-only objects, where the i915-gem shrinker
can later kick in to swap out the pages, if needed.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i9
Turn on the shmem tt backend, and enable shrinking.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/driver
On Tue, Oct 05, 2021 at 05:00:40PM +0200, Sebastian Andrzej Siewior wrote:
> From: Mike Galbraith
>
> Commit
>8d7849db3eab7 ("drm/i915: Make sprite updates atomic")
>
> started disabling interrupts across atomic updates. This breaks on PREEMPT_RT
> because within this section the code attemp
Hi Alexander,
Thank you for the patch.
On Wed, Oct 06, 2021 at 09:47:13AM +0200, Alexander Stein wrote:
> The enable signal may not be controllable by the kernel. Make it
> optional.
> This is a similar to commit bbda1704fc15 ("drm/bridge: ti-sn65dsi86: Make
> enable GPIO optional")
>
> Signed-o
On Wed, Oct 06, 2021 at 12:18:02PM +0300, Laurent Pinchart wrote:
> Hi Alexander,
>
> Thank you for the patch.
One more thing, the subject line has a typo, it should read
ti-sn65dsi83.
> On Wed, Oct 06, 2021 at 09:47:13AM +0200, Alexander Stein wrote:
> > The enable signal may not be controllabl
Hi Dave, Daniel,
I've rebased the patches and dropped the vc4 changes. I kept the compiler fix,
as it appeared to be unrelated to the clock changes.
drm-misc-fixes-2021-10-06:
Rebased drm-misc-fixes for v5.15-rc5:
- Dropped vc4 patches.
- Compiler fix for vc4.
- Cursor fix for nouveau.
- Fix ttm
Hello,
When using Healer to fuzz the latest Linux kernel, the following crash
was triggered.
HEAD commit: 42d43c92fc57 Merge branch 'for-linus'
git tree: upstream
console output:
https://drive.google.com/file/d/1fV8jSOKPspCPI-4i7Ee_FJIPIvz24MYu/view?usp=sharing
kernel config:
https://drive.goog
On Tue, Oct 05, 2021 at 05:00:41PM +0200, Sebastian Andrzej Siewior wrote:
> Luca Abeni reported this:
> | BUG: scheduling while atomic: kworker/u8:2/15203/0x0003
> | CPU: 1 PID: 15203 Comm: kworker/u8:2 Not tainted 4.19.1-rt3 #10
> | Call Trace:
> | rt_spin_lock+0x3f/0x50
> | gen6_read32+0x4
Applied to drm-misc-next
On Thu, 23 Sept 2021 at 01:19, Laurent Pinchart
wrote:
>
> Hi Cai,
>
> Thank you for the patch.
>
> On Wed, Sep 22, 2021 at 08:59:08PM +0800, Cai Huoqing wrote:
> > The helper function devm_add_action_or_reset() will internally
> > call devm_add_action(), and if devm_add_
>
On Tue, 7 Sept 2021 at 04:40, Marek Vasut wrote:
>
> Move detach implementation from sn65dsi83_remove() to dedicated
.detach callback. There is no functional change to the code, but
> that detach is now in the correct location.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> Cc: Laurent Pin
On 2021-10-06 12:34:19 [+0300], Ville Syrjälä wrote:
> I think the correct answer is to make uncore.lock a raw_spinlock.
> Without the tracepoints deubgging any of this is stuff pretty much
> impossible. We also take that lock a lot.
Let me check if that works.
Sebastian
On 29-07-21, 23:23, Dmitry Baryshkov wrote:
> On 15/07/2021 09:51, Vinod Koul wrote:
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > index fd2d104f0a91..4da6d72b7996 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > +++ b/drivers/
On 02-08-21, 16:24, abhin...@codeaurora.org wrote:
> On 2021-07-14 23:51, Vinod Koul wrote:
> > @@ -476,6 +498,9 @@ static int _dpu_rm_reserve_intf(
> > }
> >
> > global_state->intf_to_enc_id[idx] = enc_id;
> > +
> > + global_state->dsc_to_enc_id[0] = enc_id;
> > + global_state->dsc_t
Hi Dave, Daniel,
Handling drm-misc-next this week for Maxime.
drm-misc-next-2021-10-06:
drm-misc-next for v5.16:
UAPI Changes:
- Allow empty drm leases for creating separate GEM namespaces.
Cross-subsystem Changes:
- Slightly rework dma_buf_poll.
- Add dma_resv_for_each_fence_unlocked to iterat
On 29-07-21, 23:25, Dmitry Baryshkov wrote:
> On 15/07/2021 09:51, Vinod Koul wrote:
> > This add SDM845 DSC blocks into hw_catalog
> >
> > Signed-off-by: Vinod Koul
> > ---
> > Changes since RFC:
> > - use BIT values from MASK
> >
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 22 +
On 02-08-21, 16:29, abhin...@codeaurora.org wrote:
> On 2021-07-14 23:51, Vinod Koul wrote:
> > This add SDM845 DSC blocks into hw_catalog
> /add --> adds
> >
> > Signed-off-by: Vinod Koul
> > ---
> > Changes since RFC:
> > - use BIT values from MASK
> >
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_ca
Hi Chun-Kuang,
Missatge de Chun-Kuang Hu del dia dv., 1
d’oct. 2021 a les 17:52:
>
> Hi, Enric:
>
> Enric Balletbo Serra 於 2021年9月30日 週四 下午9:48寫道：
> >
> > Hi Chun-Kuang,
> >
> > Missatge de Chun-Kuang Hu del dia dj., 30 de
> > set. 2021 a les 15:11:
> > >
> > > Hi, Enric:
> > >
> > > Enric Ball
Am 06.10.21 um 09:20 schrieb Stephen Rothwell:
Hi Randy,
On Tue, 5 Oct 2021 22:48:03 -0700 Randy Dunlap wrote:
on i386:
ld: drivers/gpu/drm/msm/hdmi/hdmi_phy.o:(.rodata+0x3f0): undefined reference to
`msm_hdmi_phy_8996_cfg'
Full randconfig fle is attached.
This would be because CONFIG_
Hi,
On Wed, 6 Oct 2021 at 10:06, Stephen Boyd wrote:
>
> Quoting Dmitry Baryshkov (2021-10-05 23:10:22)
> > On Wed, 6 Oct 2021 at 07:26, Stephen Boyd wrote:
> > >
> > > Quoting Bjorn Andersson (2021-10-05 19:37:52)
> > > > On Tue 05 Oct 19:06 PDT 2021, Stephen Boyd wrote:
> > > >
> > > > > Quoti
Applied to drm-misc-next
On Fri, 9 Jul 2021 at 01:03, Dmitry Baryshkov
wrote:
>
> - set DRM_CONNECTOR_POLL_HPD as the connector will generate hotplug
> events on its own
>
> - do not call drm_kms_helper_hotplug_event() unless mode_config.funcs
> pointer is not NULL to remove possible kernel o
[AMD Official Use Only]
> -Original Message-
> From: Wentland, Harry
> Sent: October 5, 2021 2:04 PM
> To: Zuo, Jerry ; Doug Anderson
>
> Cc: Ville Syrjälä ; dri-
> de...@lists.freedesktop.org; ge...@linux-m68k.org; oliver.s...@intel.com;
> Daniel Vetter ; David Airlie ; Jani Nikula
> ;
On 30-07-21, 01:15, Dmitry Baryshkov wrote:
> On 15/07/2021 09:51, Vinod Koul wrote:
> > Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> > bits so that DSC would work there as well
> >
> > Signed-off-by: Vinod Koul
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.
On 02-08-21, 17:00, abhin...@codeaurora.org wrote:
> On 2021-07-14 23:51, Vinod Koul wrote:
> > Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> > bits so that DSC would work there as well
> >
> > Signed-off-by: Vinod Koul
> Please correct me if wrong but here you seem t
On 02-08-21, 17:24, abhin...@codeaurora.org wrote:
> On 2021-07-14 23:51, Vinod Koul wrote:
> > We cannot enable mode_3d when we are using the DSC. So pass
> > configuration to detect DSC is enabled and not enable mode_3d
> > when we are using DSC
> >
> > We add a helper dpu_encoder_helper_get_dsc
A simpler version of the iterator to be used when the dma_resv object is
locked.
v2: fix index check here as well
v3: minor coding improvement, some documentation cleanup
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 51 ++
include/linux/dma
Just exercising a very minor subset of the functionality, but already
proven useful.
v2: add missing locking
v3: some more cleanup and consolidation, add unlocked test as well
Signed-off-by: Christian König
---
drivers/dma-buf/Makefile | 3 +-
drivers/dma-buf/selftests.h | 1 +
drive
On Wed, 6 Oct 2021 at 00:19, Dmitry Osipenko wrote:
>
> 05.10.2021 16:10, Ulf Hansson пишет:
> > On Sat, 2 Oct 2021 at 22:44, Dmitry Osipenko wrote:
> >>
> >> 01.10.2021 15:32, Ulf Hansson пишет:
> +static __maybe_unused int tegra_clock_pm_suspend(struct device *dev)
> +{
> +
On 06/10/2021 13:36, Christian König wrote:
A simpler version of the iterator to be used when the dma_resv object is
locked.
v2: fix index check here as well
v3: minor coding improvement, some documentation cleanup
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 51
On 29-07-21, 23:54, Dmitry Baryshkov wrote:
> On 15/07/2021 09:52, Vinod Koul wrote:
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 8d942052db8a..41140b781e66 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >
On Wed, 6 Oct 2021 at 00:43, Dmitry Osipenko wrote:
>
> 06.10.2021 01:19, Dmitry Osipenko пишет:
> ...
> > I reproduced the OFF problem by removing the clk prepare/unprepare from
> > the suspend/resume of the clk driver and making some extra changes to
> > clock tree topology and etc to trigger th
On 02-08-21, 17:57, abhin...@codeaurora.org wrote:
> On 2021-07-14 23:52, Vinod Koul wrote:
> > When DSC is enabled in DT, we need to configure the encoder for DSC
> > configuration, calculate DSC parameters for the given timing.
> >
> > This patch adds that support by adding dpu_encoder_prep_dsc(
Hi Neil,
On 06/10/2021 11:17, Neil Armstrong wrote:
Hi,
On 23/09/2021 09:06, Neil Armstrong wrote:
This patchset is the follow-up the v4 patchset from Benoit Parrot at [1].
This patch series adds virtual-plane support to omapdrm driver to allow the use
of display wider than 2048 pixels.
In o
On 06/10/2021 13:36, Christian König wrote:
Just exercising a very minor subset of the functionality, but already
proven useful.
v2: add missing locking
v3: some more cleanup and consolidation, add unlocked test as well
Signed-off-by: Christian König
---
drivers/dma-buf/Makefile | 3
On Wed, Oct 6, 2021 at 2:47 AM Alexander Stein
wrote:
>
> Add a VCC regulator which needs to be enabled before the EN pin is
> released.
>
> Signed-off-by: Alexander Stein
> ---
> .../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 5 +
> 1 file changed, 5 insertions(+)
>
> diff -
Hi,
On 06/10/2021 08:58, Barry Song wrote:
On Wed, Oct 6, 2021 at 5:15 PM Wanghui (John) wrote:
HI Tvrtko
On 2021/10/4 22:36, Tvrtko Ursulin wrote:
void set_user_nice(struct task_struct *p, long nice)
{
bool queued, running;
- int old_prio;
+ int old_prio, ret;
Hi,
On Tue, 5 Oct 2021, Greg KH wrote:
> On Wed, Sep 22, 2021 at 11:54:32AM +0300, Kai Vehmanen wrote:
> > In current code, the devres group for aggregate master is left open
> > after call to component_master_add_*(). This leads to problems when the
> > master does further managed allocations on
On Tue, 28 Sept 2021 at 14:16, Guido Günther wrote:
>
> media-bus-formats.h has them in hexadecimal as well so matching with
> that file saves one conversion when debugging.
>
> Signed-off-by: Guido Günther
> ---
> drivers/gpu/drm/mxsfb/mxsfb_kms.c | 2 +-
> 1 file changed, 1 insertion(+), 1 del
On Tue, Oct 05, 2021 at 07:34:00PM +0200, Marijn Suijten wrote:
> On 2021-10-05 17:24:53, Daniel Thompson wrote:
> > On Tue, Oct 05, 2021 at 05:23:26PM +0200, Marijn Suijten wrote:
> > > Since there don't seem to be any substantial platforms/PMICs using this
> > > functionality in a working manner,
Hi,
On Tue, Oct 5, 2021 at 7:27 PM Bjorn Andersson
wrote:
>
> > > For reference, this is how I thought one is supposed to tie the Type-C
> > > controller to the display driver:
> > > https://lore.kernel.org/all/20211005022451.2037405-1-bjorn.anders...@linaro.org/
> >
> > OK, so I looked at that a
This new ADDFB2 flag allows callers to mark a framebuffer as
"persistent", and no longer have RMFB semantics when the DRM
file is closed.
[1]: https://lore.kernel.org/dri-devel/YTJypepF1Hpc2YYT@reader/
Signed-off-by: Simon Ser
Cc: Hans de Goede
Cc: Dennis Filder
Cc: Daniel Vetter
Cc: Pekka Pa
On 2021-10-05 19:10, Bjorn Andersson wrote:
On Tue 05 Oct 16:04 PDT 2021, khs...@codeaurora.org wrote:
On 2021-10-05 15:36, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2021-10-05 14:40:38)
> > On Tue 05 Oct 11:45 PDT 2021, Stephen Boyd wrote:
> >
> > > Quoting Bjorn Andersson (2021-10-04 19:
On Wed, Oct 6, 2021 at 5:15 PM Wanghui (John) wrote:
>
> HI Tvrtko
>
> On 2021/10/4 22:36, Tvrtko Ursulin wrote:
> > void set_user_nice(struct task_struct *p, long nice)
> > {
> > bool queued, running;
> > - int old_prio;
> > + int old_prio, ret;
> > struct rq_flags rf;
> >
Convert the Silicon Image SiI8620 MIPI-DSI to LVDS bridge documentation
to YAML.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/display/bridge/sil,sii8620.yaml | 96 +++
.../bindings/display/bridge/sil-sii8620.txt | 33 ---
2 files changed, 96 insertions(+), 3
VCC needs to be enabled before releasing the enable GPIO.
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
in
Convert the Silicon Image SiI9234 HDMI/MHL bridge documentation to YAML.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/display/bridge/sii9234.txt | 49
.../bindings/display/bridge/sil,sii9234.yaml | 110 ++
2 files changed, 110 insertions(+), 49 del
Add a VCC regulator which needs to be enabled before the EN pin is
released.
Signed-off-by: Alexander Stein
---
.../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
Convert the Toshiba TC358767 txt documentation to YAML.
Signed-off-by: AngeloGioacchino Del Regno
---
.../display/bridge/toshiba,tc358767.txt | 54
.../display/bridge/toshiba,tc358767.yaml | 118 ++
2 files changed, 118 insertions(+), 54 deletions(-)
delete
> From: Laurent Pinchart
>
> The SN65DSI8x EN signal may be tied to VCC, or otherwise controlled by
> means not available to the kernel. Make the GPIO optional.
>
> Signed-off-by: Laurent Pinchart
> ---
> .../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 1 -
> 1 file changed,
Convert the Silicon Image SiI8620 HDMI/MHL bridge documentation to YAML.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/display/bridge/sil,sii8620.yaml | 93 +++
.../bindings/display/bridge/sil-sii8620.txt | 33 ---
2 files changed, 93 insertions(+), 33 deleti
On Wed, Oct 6, 2021 at 3:21 PM Rob Herring
wrote:
> On Wed, Oct 6, 2021 at 2:47 AM Alexander Stein
> wrote:
> >
> > Add a VCC regulator which needs to be enabled before the EN pin is
> > released.
> >
> > Signed-off-by: Alexander Stein
> > ---
> > .../devicetree/bindings/display/bridge/ti,sn65
The enable signal may not be controllable by the kernel. Make it
optional.
This is a similar to commit bbda1704fc15 ("drm/bridge: ti-sn65dsi86: Make
enable GPIO optional")
Signed-off-by: Alexander Stein
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
Convert the Toshiba TC358764 txt documentation to YAML.
Signed-off-by: AngeloGioacchino Del Regno
---
.../display/bridge/toshiba,tc358764.txt | 35 ---
.../display/bridge/toshiba,tc358764.yaml | 94 +++
2 files changed, 94 insertions(+), 35 deletions(-)
delete mo
Combo phy support both USB3 and DP simultaneously. USB3 is the
master of combo phy so that USB3 should initialize and power on
its phy before DP initialize its phy. At current implementation,
DP driver initialize its phy happen earlier than USB3 initialize
its phy which cause timeout error at proc
On Wed, Oct 6, 2021 at 4:41 AM Lyude Paul wrote:
>
> Since we don't support hybrid AUX/PWM backlights in nouveau right now,
> let's add some explicit checks so that we don't break nouveau once we
> enable support for these backlights in other drivers.
>
> Signed-off-by: Lyude Paul
> ---
> driver
On 2021-10-06 12:15:21 [+0200], To Ville Syrjälä wrote:
> On 2021-10-06 12:34:19 [+0300], Ville Syrjälä wrote:
> > I think the correct answer is to make uncore.lock a raw_spinlock.
> > Without the tracepoints deubgging any of this is stuff pretty much
> > impossible. We also take that lock a lot.
>
Replace private helper with call to ioctl_wrapper for
DRM_IOCTL_PRIME_HANDLE_TO_FD.
Signed-off-by: Alan Previn
---
tests/i915/gem_pxp.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 79040165..0430f4b8 10
On Tue 05 Oct 21:26 PDT 2021, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2021-10-05 19:37:52)
> > On Tue 05 Oct 19:06 PDT 2021, Stephen Boyd wrote:
> >
> > > Quoting Bjorn Andersson (2021-10-05 18:43:16)
> > > > On Tue 05 Oct 17:43 PDT 2021, Stephen Boyd wrote:
> > > >
> > > > > Quoting Bjorn
>-Original Message-
>From: Teres Alexis, Alan Previn
>Sent: Wednesday, October 6, 2021 12:52 PM
>To: igt-...@lists.freedesktop.org
>Cc: Teres Alexis, Alan Previn ; dri-
>de...@lists.freedesktop.org; Ruhl; Ruhl, Michael J
>; Vivi, Rodrigo
>Subject: [PATCH i-g-t 1/1] tests/i915_pxp: Use ioc
On Wed, Oct 06, 2021 at 09:22:42AM +0100, Tvrtko Ursulin wrote:
>
> On 06/10/2021 00:14, Matthew Brost wrote:
> > On Tue, Oct 05, 2021 at 10:47:11AM -0700, Umesh Nerlige Ramappa wrote:
> > > With GuC handling scheduling, i915 is not aware of the time that a
> > > context is scheduled in and out of
On Mon, Oct 04, 2021 at 03:36:48PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Code added in 71ed60112d5d ("drm/i915: Add kick_backend function to
> i915_sched_engine") and ee242ca704d3 ("drm/i915/guc: Implement GuC
> priority management") introduced some scheduling related vfuncs whi
Quoting Bjorn Andersson (2021-10-06 10:07:17)
> On Tue 05 Oct 21:26 PDT 2021, Stephen Boyd wrote:
>
> > Quoting Bjorn Andersson (2021-10-05 19:37:52)
> > > On Tue 05 Oct 19:06 PDT 2021, Stephen Boyd wrote:
> > >
> > > > Quoting Bjorn Andersson (2021-10-05 18:43:16)
> > > > > On Tue 05 Oct 17:43 PDT
On 06/10/2021 20:07, Bjorn Andersson wrote:
On Tue 05 Oct 21:26 PDT 2021, Stephen Boyd wrote:
Quoting Bjorn Andersson (2021-10-05 19:37:52)
On Tue 05 Oct 19:06 PDT 2021, Stephen Boyd wrote:
Quoting Bjorn Andersson (2021-10-05 18:43:16)
On Tue 05 Oct 17:43 PDT 2021, Stephen Boyd wrote:
Quo
On Mon, Oct 04, 2021 at 03:36:49PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Introduce the concept of context nice value which matches the process
> nice.
>
> We do this by extending the struct i915_sched_attr and add a helper
> (i915_sched_attr_priority) to be used to convert to e
On Mon, Oct 04, 2021 at 03:36:49PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Introduce the concept of context nice value which matches the process
> nice.
>
> We do this by extending the struct i915_sched_attr and add a helper
> (i915_sched_attr_priority) to be used to convert to e
On Wed 06 Oct 08:37 PDT 2021, khs...@codeaurora.org wrote:
> On 2021-10-05 19:10, Bjorn Andersson wrote:
> > On Tue 05 Oct 16:04 PDT 2021, khs...@codeaurora.org wrote:
> >
> > > On 2021-10-05 15:36, Stephen Boyd wrote:
> > > > Quoting Bjorn Andersson (2021-10-05 14:40:38)
> > > > > On Tue 05 Oct
Maxime Ripard 于2021年9月28日周二 下午5:28写道：
>
> On Sun, Sep 26, 2021 at 10:31:53PM +0800, Kevin Tang wrote:
> > Maxime Ripard 于2021年9月17日周五 下午11:40写道：
> > > > +static void sprd_dsi_encoder_mode_set(struct drm_encoder *encoder,
> > > > + struct drm_display_mode *mode,
> > >
On Wed 06 Oct 10:19 PDT 2021, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2021-10-06 10:07:17)
> > On Tue 05 Oct 21:26 PDT 2021, Stephen Boyd wrote:
> >
> > > Quoting Bjorn Andersson (2021-10-05 19:37:52)
> > > > On Tue 05 Oct 19:06 PDT 2021, Stephen Boyd wrote:
> > > >
> > > > > Quoting Bjorn
On 10/6/21 12:24 AM, Christian König wrote:
Am 06.10.21 um 09:20 schrieb Stephen Rothwell:
Hi Randy,
On Tue, 5 Oct 2021 22:48:03 -0700 Randy Dunlap wrote:
on i386:
ld: drivers/gpu/drm/msm/hdmi/hdmi_phy.o:(.rodata+0x3f0): undefined reference to
`msm_hdmi_phy_8996_cfg'
Full randconfig fle
On Thu, Sep 16, 2021 at 06:09:20PM +0300, Mikko Perttunen wrote:
> To get full performance out of these engines, bump their clock rates
> to maximum. In the future we may want something smarter but this
> should be fine for now.
>
> Signed-off-by: Mikko Perttunen
> ---
> drivers/gpu/drm/tegra/nv
On Thu, Sep 16, 2021 at 05:55:17PM +0300, Mikko Perttunen wrote:
> Add support for booting and using NVDEC on Tegra210, Tegra186
> and Tegra194 to the Host1x and TegraDRM drivers. Booting in
> secure mode is not currently supported.
>
> Signed-off-by: Mikko Perttunen
> ---
> v5:
> * Remove num_in
On Thu, Sep 30, 2021 at 01:28:04AM +0300, Dmitry Osipenko wrote:
> Asus TF700T tablet uses TC358768 DPI->DSI bridge that sits between Tegra's
> DPI output and display panel input. Bridge requires to have stable PCLK
> output before RGB encoder is enabled because it uses PCLK by itself to
> clock in
On Thu, Sep 30, 2021 at 01:28:05AM +0300, Dmitry Osipenko wrote:
> Asus Transformer TF700T is a Tegra30 tablet device which uses RGB->DSI
> bridge that requires a precise clock rate in order to operate properly.
> Tegra30 has a dedicated PLL for each display controller, hence the PLL
> rate can be
On Thu, Sep 16, 2021 at 05:55:15PM +0300, Mikko Perttunen wrote:
> Add YAML device tree bindings for NVDEC, now in a more appropriate
> place compared to the old textual Host1x bindings.
>
> Signed-off-by: Mikko Perttunen
> ---
> v6:
> * Elaborated description for nvidia,host1x-class.
> * Added d
On Thu, Sep 16, 2021 at 05:55:16PM +0300, Mikko Perttunen wrote:
> Add a device tree node for NVDEC on Tegra186, and
> device tree nodes for NVDEC and NVDEC1 on Tegra194.
>
> Signed-off-by: Mikko Perttunen
> ---
> v5:
> * Change from nvidia,instance to nvidia,host1x-class
> v4:
> * Add dma-cohere
Sam,
Thanks for your response.
Sam Ravnborg 于2021年9月27日周一 上午12:33写道：
>
> Hi Kevin,
>
> > > > + reg->_0b.bits.out_sel = pll->out_sel;
> > > > + reg->_0b.bits.kint_l = pll->kint & 0xf;
> > > > + reg->_0e.bits.pll_pu_byp = 0;
> > > > + reg->_0e.bits.pll_pu = 0;
> > > > + reg->_0e
06.10.2021 21:13, Thierry Reding пишет:
> On Thu, Sep 30, 2021 at 01:28:05AM +0300, Dmitry Osipenko wrote:
>> Asus Transformer TF700T is a Tegra30 tablet device which uses RGB->DSI
>> bridge that requires a precise clock rate in order to operate properly.
>> Tegra30 has a dedicated PLL for each dis
On Wed 06 Oct 10:19 PDT 2021, Dmitry Baryshkov wrote:
> On 06/10/2021 20:07, Bjorn Andersson wrote:
> > On Tue 05 Oct 21:26 PDT 2021, Stephen Boyd wrote:
> >
> > > Quoting Bjorn Andersson (2021-10-05 19:37:52)
> > > > On Tue 05 Oct 19:06 PDT 2021, Stephen Boyd wrote:
> > > >
> > > > > Quoting Bj
On 06/10/2021 18:24, Matthew Brost wrote:
On Mon, Oct 04, 2021 at 03:36:49PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Introduce the concept of context nice value which matches the process
nice.
We do this by extending the struct i915_sched_attr and add a helper
(i915_sched_attr_pri
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