SPDIF and other SoC components share audio PLL on Tegra, thus only one
component may set the desired base clock rate. This creates problem for
HDMI audio because it uses SPDIF and audio may not work if SPDIF's clock
doesn't exactly match standard audio rate since some receivers may reject
audio in
Enable S/PDIF controller to enable HDMI audio support on Toshiba AC100.
Use nvidia,fixed-parent-rate property that prevents audio rate conflict
between S/PDIF and I2S.
Tested-by: Agneli
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-paz00.dts | 8
1 file changed, 8
Add S/PDIF node to Tegra20 device-tree. It's needed for enabling HDMI
audio support.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index
Add HDMI audio graph to Tegra20 device-tree to enable HDMI audio on
Tegra20 devices.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi
Enable S/PDIF controller to enable HDMI audio support on Acer A500.
Use nvidia,fixed-parent-rate property that prevents audio rate conflict
between S/PDIF and I2S.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 8
1 file changed, 8 insertions(+)
Enable Tegra20 S/PDIF driver. It's a part of HDMI audio subsystem on
Tegra.
Signed-off-by: Dmitry Osipenko
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index
Hi Dave and Daniel,
Here goes drm-intel-fixes-2021-12-02:
- Fixing a regression where the backlight brightness control stopped working.
- Fix the Intel HDR backlight support detection.
- Reverting a w/a to fix a gpu Hang in TGL. The w/a itself was also
for a hang, but in a much rarer scenario.
On Wed, 2021-12-01 at 16:30 -0800, Lucas De Marchi wrote:
> PAT can be disabled on boot with "nopat" in the command line. Replace
> one x86-ism with another, which is slightly more correct to prepare for
> supporting other architectures.
Reviewed-by: José Roberto de Souza
>
> Cc: Matt Roper
>
Replace 'struct master' with 'struct aggregate_device' and then rename
'master' to 'adev' everywhere in the code. While we're here, put a
struct device inside the aggregate device so that we can register it
with a bus_type in the next patch.
The diff is large but that's because this is mostly a
Remove most references to 'master' in the code now that we've decided to
migrate all the users of the ops structure to the aggregate driver.
Cc: Daniel Vetter
Cc: Greg Kroah-Hartman
Cc: Laurent Pinchart
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Cc: Saravana Kannan
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Inki Dae
Cc: Joonyoung Shim
Cc: Seung-Woo Kim
Cc: Kyungmin Park
Cc: Daniel Vetter
Cc:
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Xinliang Liu
Cc: Tian Tao
Cc: John Stultz
Cc: Xinwei Kong
Cc: Chen Feng
Cc: Daniel Vetter
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Chun-Kuang Hu
Cc: Philipp Zabel
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Cc: Saravana Kannan
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Russell King
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Saravana Kannan
The component driver only provides 'bind' and 'unbind' callbacks to tell
the host driver that it is time to assemble the aggregate driver now
that all the components have probed. The component driver model doesn't
attempt to resolve runtime PM or suspend/resume ordering, and explicitly
mentions
Similar to drm_of_component_probe() but using the new API that registers
a driver instead of an ops struct. This allows us to migrate the users
of drm_of_component_probe() to the new way of doing things.
Cc: Laurent Pinchart
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell
The device lists are poorly ordered when the component device code is
used. This is because component_master_add_with_match() returns 0
regardless of component devices calling component_add() first. It can
really only fail if an allocation fails, in which case everything is
going bad and we're out
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: James Qian Wang (Arm Technology China)
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob
We'd like to get more device model features in the component framework
so let's pass the struct aggregate_device pointer instead of the parent
device pointer to the component binding functions. This will allow
drivers to inspect and control things related to the aggregate device in
case they need
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Philipp Zabel
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Cc:
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Cc: Saravana Kannan
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Neil Armstrong
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Tomi Valkeinen
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Liviu Dudau
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Cc:
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
TODO: This can be updated to move the drm helper logic into the
aggregate driver shutdown op.
Cc:
This allows aggregate driver writers to use the device passed to their
probe/remove/shutdown functions properly instead of treating it as an
opaque pointer.
Cc: Daniel Vetter
Cc: Greg Kroah-Hartman
Cc: Laurent Pinchart
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Cc: Saravana
This series is from discussion we had on reordering the device lists for
drm shutdown paths[1]. I've introduced an 'aggregate' bus that we put
the aggregate device onto and then we probe the aggregate device once
all the components are probed and call component_add(). The probe/remove
hooks are
Correct,
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
Coarse power gating for render should not be enabled on some DG2
steppings.
Bspec: 52698
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++
1 file changed, 11
cgroup.h (therefore swap.h, therefore half of the universe)
includes bpf.h which in turn includes module.h and slab.h.
Since we're about to get rid of that dependency we need
to clean things up.
v2: drop the cpu.h include from cacheinfo.h, it's not necessary
and it makes riscv sensitive to
Hi Linus,
Bit of an uptick in patch count this week, though it's all relatively
small overall. I suspect msm has been queuing up a few fixes to skew
it here. Otherwise amdgpu has a scattered bunch of small fixes, and
then some vc4, i915. virtio-gpu changes an rc1 introduced uAPI
mistake, and
Looks correct.
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Tested-by: Jyri Sarha
Cc: Tomi Valkeinen
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Vitaly Lubart
Cc: Tomas Winkler
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Cc: Daniel
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Sandy Huang
Cc: "Heiko Stübner"
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
There aren't any users anymore so drop it.
Cc: Laurent Pinchart
Cc: Daniel Vetter
Cc: Greg Kroah-Hartman
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Cc: Saravana Kannan
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/drm_of.c | 85 +---
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Acked-by: Sebastian Reichel
Cc:
Cc: Daniel Vetter
Cc: Linus Walleij
Cc: "Rafael J. Wysocki"
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Yong Wu
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Cc: Kai Vehmanen
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Tomas Winkler
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Cc: Daniel Vetter
Cc: "Rafael J.
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc:
Cc:
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Cc: Saravana
The struct is unused now so drop it along with the functions that use
it.
Cc: Daniel Vetter
Cc: Greg Kroah-Hartman
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc: Russell King
Cc: Saravana Kannan
Signed-off-by: Stephen Boyd
---
drivers/base/component.c | 148
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Emma Anholt
Cc: Maxime Ripard
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc:
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Acked-by: Mark Brown
Cc: Jaroslav Kysela
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
TODO: Move the helpers to PM in aggregate driver hooks.
Acked-by: Paul Cercueil
Cc: Daniel Vetter
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: Daniel Vetter
Cc: "Rafael J. Wysocki"
Cc: Rob Clark
Cc:
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to all
the component devices that make up the aggregate device.
Cc: Lucas Stach
Cc: Russell King
Cc: Christian Gmeiner
Cc: Daniel Vetter
Cc: "Rafael J.
From: Mark Yacoub
[Why]
drm_handle_vblank_events loops over vblank_event_list to send any event
that is current or has passed.
More than 1 event could be pending with past sequence time that need to
be send. This can be a side effect of drivers without hardware vblank
counter and they depend on
On Wed, Nov 17, 2021 at 09:19:38AM -0600, Rob Herring wrote:
> On Wed, Nov 17, 2021 at 8:34 AM Sascha Hauer wrote:
> >
> > This enabled the VOP2 display controller along with hdmi and the
> > required port routes which is enough to get a picture out of the
> > hdmi port of the board.
> >
> >
PATCH V11 2021-12-02 19:39:52:
- patch 4/8: change devm_regulator_get_optional to devm_regulator_get and
remove NULL check (requested by broo...@kernel.org)
- patch 3/8: make hdmi-5v-supply required (requested by broo...@kernel.org)
PATCH V10 2021-11-30 22:26:41:
- patch 3/8: fix $id
From: Paul Boddie
Add support for the LCD controller present on JZ4780 SoCs.
This SoC uses 8-byte descriptors which extend the current
4-byte descriptors used for other Ingenic SoCs.
Tested on MIPS Creator CI20 board.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by:
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for
JZ4780 HDMI support. This requires a new driver, plus device tree and
configuration modifications.
Here we add Kconfig DRM_INGENIC_DW_HDMI, Makefile and driver code.
Signed-off-by: Paul Boddie
From: Paul Boddie
We need to hook up
* HDMI connector
* HDMI power regulator
* JZ4780_CLK_HDMI @ 27 MHz
* DDC pinmux
* HDMI and LCDC endpoint connections
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/ci20.dts | 72 -
This changes the way the regmap is allocated to prepare for the
later addition of the JZ4780 which has more registers and bits
than the others.
Therefore we make the regmap as big as the reg property in
the device tree tells.
Suggested-by: Paul Cercueil
Signed-off-by: H. Nikolaus Schaller
---
From: Sam Ravnborg
Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC.
Based on .txt binding from Zubair Lutfullah Kakakhel
We also add generic ddc-i2c-bus to synopsys,dw-hdmi.yaml
Signed-off-by: Sam Ravnborg
Signed-off-by: H. Nikolaus Schaller
Cc: Rob Herring
Cc:
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for
JZ4780 HDMI support. This requires a new driver, plus device tree and
configuration modifications.
Here we add jz4780 device tree setup.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
After getting the regmap size from the device tree we should
reduce the ranges to the really available registers. This
allows to read only existing registers from the debug fs
and makes the regmap check out-of-bounds access.
For the jz4780 we have done this already.
Suggested-for: Paul Cercueil
Enable CONFIG options as modules.
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/configs/ci20_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index
Hi Chun-Kuang.
Quoting Chun-Kuang Hu (2021-11-25 16:27:45)
> Hi, Guillaume:
>
> This is a big patch, so I give some comment first.
>
> Guillaume Ranquet 於 2021年11月10日 週三 下午9:06寫道：
> >
> > From: Markus Schneider-Pargmann
> >
> > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC
Introduce how to collect DTN log from debugfs.
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 17 +
1 file changed, 17 insertions(+)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst
b/Documentation/gpu/amdgpu/display/dc-debug.rst
In the DC driver, we have multiple acronyms that are not obvious most of
the time; the same idea is valid for amdgpu. This commit introduces a DC
and amdgpu glossary in order to make it easier to navigate through our
driver.
Changes since V1:
- Yann: Divide glossary based on driver context.
-
This commit describes how DCN works by providing high-level diagrams
with an explanation of each component. In particular, it details the
Global Sync signals.
Signed-off-by: Rodrigo Siqueira
---
.../gpu/amdgpu/display/config_example.svg | 414 ++
Display core documentation is not well organized, and it is hard to find
information due to the lack of sections. This commit reorganizes the
documentation layout, and it is preparation work for future changes.
Changes since V1:
- Christian: Group amdgpu documentation together.
- Daniel: Drop
Display core provides a feature that makes it easy for users to debug
Multiple planes by enabling a visual notification at the bottom of each
plane. This commit introduces how to use such a feature.
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 34
Display core provides a feature that makes it easy for users to debug
Pipe Split. This commit introduces how to use such a debug option.
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 28 +--
1 file changed, 26 insertions(+), 2 deletions(-)
Display Core (DC) is one of the components under amdgpu, and it has
multiple features directly related to the KMS API. Unfortunately, we
don't have enough documentation about DC in the upstream, which makes
the life of some external contributors a little bit more challenging.
For these reasons,
Support new nvidia,fixed-parent-rate device-tree property which instructs
I2S that board wants parent clock rate to stay at a fixed rate. This allows
to play audio over S/PDIF and I2S simultaneously. The root of the problem
is that audio components on Tegra share the same audio PLL, and thus, only
Tegra20 SoC supports only S/PDIF source for HDMI audio. Register ASoC HDMI
S/PDIF CODEC for Tegra20, it will be linked with the S/PDIF CPU DAI.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/Kconfig | 3 +
drivers/gpu/drm/tegra/hdmi.c | 153 +++---
2
Add missing error unwinding to tegra_hdmi_init(), for consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/hdmi.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index
Support system suspend by enforcing runtime PM suspend/resume.
Now there is no doubt that h/w is indeed stopped during suspend
and that h/w state will be properly restored after resume.
Signed-off-by: Dmitry Osipenko
---
sound/soc/tegra/tegra20_spdif.c | 2 ++
1 file changed, 2 insertions(+)
Document new optional sound-dai-cells property of HDMI node. This node will
be used as endpoint of HDMI sound DAI graph.
Acked-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Document new nvidia,fixed-parent-rate property which instructs that this
board wants parent clock to stay at a fixed rate. It allows to prevent
conflicts between audio components that share same parent PLL. For
instance, this property allows to have HDMI audio, speaker and headphones
in the system
Add device-tree binding for Tegra20 S/PDIF controller.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../bindings/sound/nvidia,tegra20-spdif.yaml | 85 +++
1 file changed, 85 insertions(+)
create mode 100644
Convert NVIDIA Tegra20 I2S binding to schema.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../bindings/sound/nvidia,tegra20-i2s.txt | 30
.../bindings/sound/nvidia,tegra20-i2s.yaml| 70 +++
2 files changed, 70 insertions(+), 30 deletions(-)
Tegra20 S/PDIF driver was added in a pre-DT era and was never used since
that time. Revive driver by adding device-tree support.
Signed-off-by: Dmitry Osipenko
---
sound/soc/tegra/tegra20_spdif.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git
- Clean up whitespaces, defines and variables.
- Remove obsolete code.
- Adhere to upstream coding style.
- Don't override returned error code.
- Replace pr_err with dev_err.
No functional changes are made by this patch. This is a minor code's
refactoring that will ease further maintenance of
Reset S/PDIF controller on runtime PM suspend/resume to ensure that we
always have a consistent hardware state.
Signed-off-by: Dmitry Osipenko
---
sound/soc/tegra/tegra20_spdif.c | 32
sound/soc/tegra/tegra20_spdif.h | 1 +
2 files changed, 33 insertions(+)
Use resource-managed helpers to make code cleaner. Driver's remove callback
isn't needed anymore since driver is completely resource-managed now.
Signed-off-by: Dmitry Osipenko
---
sound/soc/tegra/tegra20_spdif.c | 33 +
sound/soc/tegra/tegra_pcm.c | 6
This series revives Tegra20 S/PDIF driver which was upstreamed long time
ago, but never was used. It also turns Tegra DRM HDMI driver into HDMI
audio CODEC provider. Finally, HDMI audio is enabled in device-trees.
For now the audio is enable only for Acer A500 tablet and Toshiba AC100
netbook
From: Arnd Bergmann
The DMA resource is never set up anywhere, and passing this as slave_id
has not been the proper procedure in a long time.
As a preparation for removing all slave_id references from the ALSA code,
remove this one.
According to Dmitry Osipenko, this driver has never been used
FIFO trigger level must be not less than the size of DMA burst, otherwise
audio will be played x4 faster that it should be because part of the DMA
data will be dropped on FIFO input buffer overflow.
Signed-off-by: Dmitry Osipenko
---
sound/soc/tegra/tegra20_spdif.c | 8
1 file changed,
Applied. Thanks!
Alex
On Wed, Dec 1, 2021 at 10:16 AM Christian König
wrote:
>
> Am 01.12.21 um 16:13 schrieb Zhou Qingyang:
> > In radeon_driver_open_kms(), radeon_vm_bo_add() is assigned to
> > vm->ib_bo_va and passes and used in radeon_vm_bo_set_addr(). In
> > radeon_vm_bo_set_addr(), there
Applied. Thanks!
Alex
On Thu, Dec 2, 2021 at 11:17 AM Zhou Qingyang wrote:
>
> In amdgpu_connector_lcd_native_mode(), the return value of
> drm_mode_duplicate() is assigned to mode, and there is a dereference
> of it in amdgpu_connector_lcd_native_mode(), which will lead to a NULL
> pointer
Hi Sascha,
Am Donnerstag, 2. Dezember 2021, 16:34:49 CET schrieb Sascha Hauer:
> On Wed, Nov 17, 2021 at 09:19:38AM -0600, Rob Herring wrote:
> > On Wed, Nov 17, 2021 at 8:34 AM Sascha Hauer wrote:
> > >
> > > This enabled the VOP2 display controller along with hdmi and the
> > > required port
Hi Heiko,
On Thu, Dec 02, 2021 at 04:41:17PM +0100, Heiko Stübner wrote:
> Hi Sascha,
>
> Am Donnerstag, 2. Dezember 2021, 16:34:49 CET schrieb Sascha Hauer:
> > On Wed, Nov 17, 2021 at 09:19:38AM -0600, Rob Herring wrote:
> > > On Wed, Nov 17, 2021 at 8:34 AM Sascha Hauer
> > > wrote:
> > > >
With object clearing/copying we need to be able to modify the PTEs on
the fly via some batch buffer, which means we need to be able to map the
paging structures(or at the very least the PT, but being able to also
map the PD might also be useful at some point) into the GTT. And since
the paging
Ensure we add the engine base only after we calculate the qword offset
into the PTE window.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This is all kinds of awkward since we now have to contend with using 64K
GTT pages when mapping anything in LMEM(including the page-tables
themselves).
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 186 +++-
Ensure we account for any object rounding due to min_page_size
restrictions.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index a804c57b61df..0da27ec808dc 100644
---
No need to insert PTEs for the PTE window itself, also foreach expects a
length not an end offset, which could be gigantic here with a second
engine.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
1 file changed, 1
If this is LMEM then we get a 32 entry PT, with each PTE pointing to
some 64K block of memory, otherwise it's just the usual 512 entry PT.
This very much assumes the caller knows what they are doing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
The scratch page might not be allocated in LMEM(like on DG2), so instead
of using that as the deciding factor for where the paging structures
live, let's just query the pt before mapping it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
Hi Dave, Daniel,
New stuff for 5.17.
The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:
Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-next-5.17-2021-12-02
for you
The pull request you sent on Fri, 3 Dec 2021 07:27:03 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2021-12-03-1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/5f58da2befa58edf3a70b91ed87ed9bf77f1e70e
Thank you!
--
Deet-doot-dot, I am a bot.
On Thu, Dec 02, 2021 at 04:06:23PM -0800, john.c.harri...@intel.com wrote:
From: John Harrison
If the GuC has failed to load for any reason and then the user pokes
the debugfs GuC log interface, a BUG and/or null pointer deref can
occur. Don't let that happen.
Signed-off-by: John Harrison
-Original Message-
From: Kuo-Hsiang Chou
Sent: Thursday, September 30, 2021 3:19 PM
To: Thomas Zimmermann ; dri-devel@lists.freedesktop.org;
linux-ker...@vger.kernel.org
Subject: RE: [PATCH] drm/ast: Atomic CR/SR reg R/W
Hi
-Original Message-
From: Thomas Zimmermann
Hi AngeloGioacchino,
Thanks for your suggestion.
On Wed, 2021-12-01 at 13:09 +0100, AngeloGioacchino Del Regno wrote:
> Il 29/11/21 04:41, Yunfei Dong ha scritto:
> > For lat and core architecture, lat thread will send message to core
> > thread when lat decode done. Core hardware will use the
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Ramalingam C
Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.
v2:
- Move pipe control from xcs indirect context to the rcs indirect
context.
Hi Benjamin,
Thanks for your suggestion.
On Tue, 2021-11-30 at 14:34 +0100, Benjamin Gaignard wrote:
> Le 29/11/2021 à 04:41, Yunfei Dong a écrit :
> > Register each hardware as platform device, need to call pm
> > functions
> > to open/close power and clock from module mtk-vcodec-dec, export
> >
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