From: Harry Wentland
Add documentation for color pipeline API.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
---
v8:
- Fix typo "definint" -> "defining"
v7:
- Add a commit messages
v5:
- Don't require BYPASS to succeed (Sebastian)
- use DATA for 1D and 3D LUT types (Sebastian)
-Wflex-array-member-not-at-end was introduced in GCC-14, and we are
getting ready to enable it, globally.
Use the `DEFINE_RAW_FLEX()` helper for an on-stack definition of
a flexible structure where the size of the flexible-array member
is known at compile-time, and refactor the rest of the code,
a
Hi Daniel,
On 28/03/25 17:06, Daniel Stone wrote:
Hi Vignesh,
On Fri, 28 Mar 2025 at 11:03, Vignesh Raman wrote:
The current s3cp implementation does not work anymore after the
migration, and instead of fixing it and propagating the fix down to us,
it's simpler to directly use curl. Uprev mes
Hi Dmitry,
On 31/03/25 13:25, Dmitry Baryshkov wrote:
On Mon, 31 Mar 2025 at 10:53, Maxime Ripard wrote:
On Sun, Mar 30, 2025 at 08:06:45PM +0300, Dmitry Baryshkov wrote:
On Thu, Mar 27, 2025 at 09:31:11PM +0530, Vignesh Raman wrote:
Add jobs to run dt_binding_check and dtbs_check. If warni
The event FB_EVENT_BLANK sends the new blank state in the event's
data field. Also send the old state. It's an additional field in the
data array; existing receivers won't notice the difference.
The backlight subsystem currently tracks blank state per display per
backlight. That is not optimal as
On Thu, Apr 03, 2025 at 09:39:52AM +0200, Christian König wrote:
> > For the UMA GPU case where there is no device memory or eviction
> > problem, perhaps a configurable option to just say account memory in
> > memcg for all allocations done by this process, and state yes you can
> > work around it
Hi all,
This series picks up the work carried out by the Asahi project for
shmem-backed GEM objects. This initial version is meant to kickstart the
discussion on this topic, as the bindings will be clearly needed by Tyr
and other drivers.
It has been tested on both AGX and Tyr successfully.
I di
Am 03.04.25 um 14:58 schrieb Philipp Stanner:
> On Thu, 2025-04-03 at 14:08 +0200, Christian König wrote:
>> Am 03.04.25 um 12:13 schrieb Philipp Stanner:
>>> Nouveau currently relies on the assumption that dma_fences will
>>> only
>>> ever get signalled through nouveau_fence_signal(), which takes
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/panel/panel-ilitek-ili9806e.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c
b/drivers/gpu/drm
Introduces the new crtc property "SHARPNESS_STRENGTH" that allows
the user to set the intensity so as to get the sharpness effect.
The value of this property can be set from 0-255.
It is useful in scenario when the output is blurry and user
want to sharpen the pixels. User can increase/decrease the
The check protects against division by 0, integer wraparound,
and overflow Start/End window settings.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Signed-off-by: Danila Chernetsov
---
drivers/video/fbdev/kyro/fbdev.c | 7 +++
1 f
Since the query loop is using copy_to_user() to write out a single u64 at
a time it feels more natural (and is a tiny bit more compact) to replace
it with put_user().
Access_ok() check is added to the input checking for an early bailout in
case of a bad buffer passed in.
Signed-off-by: Tvrtko Urs
From: Nancy Lin
BLENDER executes the alpha blending function for overlapping
layers from different sources, which is the primary function
of the overlapping system.
Signed-off-by: Nancy Lin
Signed-off-by: Paul-pl Chen
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/m
DRM clients expose information through usage stats as documented in
Documentation/gpu/drm-usage-stats.rst (available online at
https://docs.kernel.org/gpu/drm-usage-stats.html). Add a tool like
PMU, similar to the hwmon PMU, that exposes DRM information. For
example on a tigerlake laptop:
```
$ per
On Sun, Mar 30, 2025 at 08:06:45PM +0300, Dmitry Baryshkov wrote:
> On Thu, Mar 27, 2025 at 09:31:11PM +0530, Vignesh Raman wrote:
> > Add jobs to run dt_binding_check and dtbs_check. If warnings are seen,
> > exit with a non-zero error code while configuring them as warning in
> > the GitLab CI pi
From: Brendan Tam
[ Upstream commit 51d1b338541dea83fec8e6f95d3e46fa469a73a8 ]
[Why]
There have been instances of some monitors being unable to link train on
their reported link speed using their selected FFE preset. If a different
FFE preset is found that has a higher rate of success during lin
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/panel/panel-raydium-rm692e5.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-raydium-rm692e5.c
b/drivers/gpu/drm
Clean up the function a bit, mainly by doing the mode_valid_check dance
once in the beginning of the function, and grouping the calculations
wrt. sync/event mode a bit better.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 48 --
1 file
Applied. Thanks!
Alex
On Mon, Mar 24, 2025 at 8:08 PM Andres Urian Florez
wrote:
>
> Instead of using the strcpy() deprecated function to populate the
> fw_name, use the strscpy() function
>
> Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#strcpy
>
> Signed-off-by: Andres
Add the register bits related to filter lut values.
These values are golden values and these value has
to be loaded one time while enabling the casf.
v2: update commit message[Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_casf.c | 22 +
Expand the driver's DebugFS GEMS file to display entries for the heap
chunks' GEM objects, both those allocated at heap creation time through an
ioctl(), or in response to a tiler OOM event.
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/panthor/panthor_gem.c | 22 +++---
dri
From: Philip Yang
[ Upstream commit 23b645231eeffdaf44021debac881d2f26824150 ]
SVM migration unmap pages from GPU and then update mapping to GPU to
recover page fault. Currently unmap clears the PDE entry for range
length >= huge page and free PTB bo, update mapping to alloc new PT bo.
There is
From: Hermes Wu
When connect to a DP-to-HDMI device which does not connect
to HDMI sink, it will report DPCD 00200h with SINK_COUNT = "0",
and issue HPD_IRQ when SINK_COUNT change to "1".
IT6505 can not recive HPD_IRQ before training done and driver will
force HW enter training done state when c
On Thu, Mar 20, 2025 at 02:44:46PM +0530, Ling Xu wrote:
> Add "gdsp0" and "gdsp1" as the new supported labels for GPDSPs fastrpc
> domains.
Why? What problem is this solving? What is GPDSP and GDSP? Why they
differ? So many questions, so little explained in commit msg.
Also, bindings are before
On Mon, 31 Mar 2025 11:15:24 -0400, Anusha Srivatsa wrote:
> This series adds the infrastructure needed for the refcounting
> allocations for panels similar to Luca's efforts with bridges.
> Underlying intention and idea is the same - avoid use-after-free
> situations in panels. Get reference to pa
From: Leonid Arapov
[ Upstream commit 3e411827f31db7f938a30a3c7a7599839401ec30 ]
Function dispc_ovl_setup is not intended to work with the value OMAP_DSS_WB
of the enum parameter plane.
The value of this parameter is initialized in dss_init_overlays and in the
current state of the code it canno
From: Andrew Wyatt
[ Upstream commit 529741c331da1fbf54f86c6ec3a4558b9b0b16dc ]
The AYA NEO Flip DS and KB both use a 1080x1920 portrait LCD panel. The
Flip DS additionally uses a 640x960 portrait LCD panel as a second display.
Add DMI matches to correctly rotate these panels.
Signed-off-by:
On Tue, Mar 25, 2025 at 10:05 AM Jocelyn Falempe wrote:
>
> Thanks, it looks good to me.
>
> Reviewed-by: Jocelyn Falempe
>
> You want to take the whole series in the rust tree?
>
> Otherwise I can push the patch 1-2 to drm-misc-next if needed.
Please take them if possible, since others may want
From: Hermes Wu
When connect to device which can only training done by
step training, skip auto training when link training restart,
usually happen when display resolution is changed.
Signed-off-by: Hermes Wu
---
drivers/gpu/drm/bridge/ite-it6505.c | 36 +---
1
Am 01.04.25 um 22:46 schrieb Dmitry Osipenko:
> On 4/1/25 23:40, Rob Clark wrote:
>> On Tue, Apr 1, 2025 at 8:58 AM Rob Clark wrote:
>>> From: Rob Clark
>>>
>>> Add support for exporting a dma_fence fd for a specific point on a
>>> timeline. This is needed for vtest/vpipe[1][2] to implement time
On 24/03/2025 18:57, Ariel D'Alessandro wrote:
> Hi all,
>
> This is a new iteration on Panfrost support for AARCH64_4K page table
> format. The main reason behind this patchset is that MediaTek MT8188 SoC
> (ARM Mali-G57 MC3 GPU) constantly faults due to the actual Panfrost cache
> configuration.
Hi
Am 02.04.25 um 12:44 schrieb Matthew Auld:
Build fails with:
error: multiple unsequenced modifications to 'sbuf32'
[-Werror,-Wunsequenced]
264 | le32_to_cpup(sbuf32++),
|^
265 | le32_to_c
Value of enum parameter 'plane' is initialized in dss_init_overlays and
cannot take the value OMAP_DSS_WB. Function dispc_ovl_setup_common could
be called with this value of parameter only from dispc_wb_setup, which has
never been used and has been removed in commit 4f55bb03801a
("omapfb: Remove un
Expose the drm crtc sharpness strength property which will enable
or disable the sharpness/casf based on user input. With this user
can set/update the strength of the sharpness or casf filter.
v2: Update subject[Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/
On Tue, Mar 25, 2025 at 11:55:46AM +0100, Jens Wiklander wrote:
> Hi Sumit,
>
>
> >
> > > +
> > > +#include "tee_private.h"
> > > +
> > > +struct tee_dma_heap {
> > > + struct dma_heap *heap;
> > > + enum tee_dma_heap_id id;
> > > + struct tee_rstmem_pool *pool;
> > > + struct
On 4/3/25 10:03, Thomas Zimmermann wrote:
> Hi
>
> Am 03.04.25 um 02:37 schrieb Lucas De Marchi:
>> On Sun, Mar 23, 2025 at 12:25:58AM +0300, Dmitry Osipenko wrote:
>>> Hi,
>>>
>>> This a continuation of a year-old series that adds generic DRM-shmem
>>> shrinker [1]. The old series became too big
Switch to the generic header check facility, and sunset the copy-pasted
local version.
Keep the header checks gated on CONFIG_DRM_XE_WERROR as before. To be
unified later.
While at it, fix a header missing header guards that was not caught by
the local version.
Reported-by: Linus Torvalds
Close
The Visionox G2647FB105 is a 6.47 inch 1080x2340 MIPI-DSI CMD mode
AMOLED panel used in:
- Xiaomi Mi Note 10 / CC9 Pro (sm7150-xiaomi-tucana)
- Xiaomi Mi Note 10 Lite (sm7150-xiaomi-toco)
Add a dt-binding for it.
Signed-off-by: Alexander Baransky
---
.../display/panel/visionox,g2647fb105.yaml
The page fault handler should reject write/atomic access to read only
VMAs. Add code to handle this in handle_pagefault after the VMA lookup.
Fixes: 3d420e9fa848 ("drm/xe: Rework GPU page fault handling")
Signed-off-by: Jonathan Cavitt
Suggested-by: Matthew Brost
---
drivers/gpu/drm/xe/xe_gt_p
It is common to build a u64 from its high and low parts obtained from
two 32-bit registers. Conversely, it is also common to split a u64 into
two u32s to write them into registers. Add an extension trait for u64
that implement these methods in a new `num` module.
It is expected that this trait wil
The field pdev is unused. Remove it.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Canillas
---
drivers/gpu/drm/tiny/ofdrm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/tiny/ofdrm.c b/drivers/gpu/drm/tiny/ofdrm.c
index 13491c0e704a6..7469dd2810837 100644
-
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c
b/driv
This patch moves GPU info initialization into panthor_hw.c in
preparation of handling GPU register changes. The GPU register reading
operations to populate gpu_info are separated into an architecture
specific arch_*_gpu_info_init() function and is called via the new
function pointer abstraction und
Goal here is cut over to gpusvm and remove xe_hmm, relying instead on
common code. The core facilities we need are get_pages(), unmap_pages()
and free_pages() for a given useptr range, plus a vm level notifier
lock, which is now provided by gpusvm.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Move the calculation of the bits per pixels for screen_info into a
helper function. This will make it available to other callers besides
the firmware code.
Signed-off-by: Thomas Zimmermann
---
drivers/firmware/sysfb_simplefb.c | 31 +
drivers/video/screen_info_generic.c
Hi Maxime，
At 2025-03-21 17:48:04, "Maxime Ripard" wrote:
>On Fri, Mar 21, 2025 at 04:53:38PM +0800, Andy Yan wrote:
>> From: Andy Yan
>>
>> In some application scenarios, we hope to get the corresponding
>> connector when the bridge's detect hook is invoked.
>>
>> In most cases, we can get t
On Wed, Apr 2, 2025 at 4:36 PM AngeloGioacchino Del Regno
wrote:
>
> When calling component_bind_all(), if a component that is included
> in the list fails, all of those that have been successfully bound
> will be unbound, but this driver has two components lists for two
> actual devices, as in, e
Invoke DYNAMIC_DEBUG_CLASSMAP_PARAM to hook drm.debug (__drm_debug) to the
DRM_UT_* classmap, replacing the ad-hoc wiring previously doing it.
Add DRM_CLASSMAP_* adapter macros to selectively use
DYNAMIC_DEBUG_CLASSMAP_* when DRM_USE_DYNAMIC_DEBUG=y is configured.
Signed-off-by: Jim Cromie
Revie
Add some basic tests for exercising entity priority handling.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
Acked-by: Christian König
---
drivers/gpu/drm/scheduler/tests/tests_basic.c | 95 ++-
1 file changed, 94
When the device is coherent, panthor_gpu_coherency_init() will read
GPU_COHERENCY_FEATURES to make sure the GPU supports the ACE-Lite
coherency protocol, which will fail if the clocks/power-domains are
not enabled when the read is done. Move the
panthor_gpu_coherency_init() call after the device ha
Hi Dave, Simona!
Rodrigo is out this week, but sending a PR for a single fix.
Thanks,
Thomas
drm-xe-fixes-2025-03-20:
Driver Changes:
- Fix for an error if exporting a dma-buf multiple time (Tomasz)
The following changes since commit f5d4e81774c42d9c2ea3980e570f3330ff2ed5d2:
drm/xe: remove re
The gud driver has a number of DRM_UT_* debugs, make them
controllable when CONFIG_DRM_USE_DYNAMIC_DEBUG=y by telling dyndbg
that the module uses them.
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/gud/gud_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/gud/gud_drv.c
From: Sarah Walker
Newer PowerVR GPUs (such as the BXS-4-64 MC1) use a RISC-V firmware
processor instead of the previous MIPS or META.
The current version of this patch depends on a patch[1] which exists in
drm-misc-fixes, but has not yet made it back to drm-misc-next (the
target of this patch).
Add EDID support to sysfb connector helpers. Read the EDID property
from the OF node in ofdrm. Without EDID, this does nothing.
Some systems with OF display, such as 32-bit PPC Macintoshs, provide
the system display's EDID data as node property in their DT. Exporting
this information allows compos
dyndbg's CLASSMAP-v1 api was broken; DECLARE_DYNDBG_CLASSMAP tried to
do too much. Its replaced by DRM_CLASSMAP_DEFINE, which creates &
EXPORTs a classmap (in DRM core), and DRM_CLASSMAP_USE which refers to
the classmap defined elsewhere.
The drivers still use DECLARE_DYNDBG_CLASSMAP for now, so
On 17.03.2025 21:55, Cavitt, Jonathan wrote:
> -Original Message-
> From: Wajdeczko, Michal
> Sent: Saturday, March 15, 2025 7:45 AM
> To: Cavitt, Jonathan ;
> intel...@lists.freedesktop.org
> Cc: Gupta, saurabhg ; Zuo, Alex
> ; joonas.lahti...@linux.intel.com; Brost, Matthew
> ; Zh
On 21/03/25 15:56, Daniel Stone wrote:
Hi Vignesh,
On Fri, 14 Mar 2025 at 08:59, Vignesh Raman wrote:
LAVA was recently patched [1] with a fix on how parameters are parsed in
`lava-test-case`, so we don't need to repeat quotes to send the
arguments properly to it. Uprev mesa to fix this issu
From: Andrew Wyatt
[ Upstream commit a860eb9c6ba6cdbf32e3e01a606556e5a90a2931 ]
Some GPD Win 2 units shipped with the correct DMI strings.
Add a DMI match to correctly rotate the panel on these units.
Signed-off-by: Andrew Wyatt
Signed-off-by: John Edwards
Tested-by: Paco Avelar
Reviewed-by
From: Philip Yang
[ Upstream commit f0b4440cdc1807bb6ec3dce0d6de81170803569b ]
If HW scheduler hangs and mode1 reset is used to recover GPU, KFD signal
user space to abort the processes. After process abort exit, user queues
still use the GPU to access system memory before h/w is reset while KFD
Look at the blank state provided by FB_EVENT_BLANK to determine
whether to enable or disable a backlight. Remove the tracking fields
from struct backlight_device.
Tracking requires three variables, fb_on, prev_fb_on and the
backlight's use_count. If fb_on is true, the display has been
unblanked. T
On 4/1/25 09:34, Krzysztof Kozlowski wrote:
> On 01/04/2025 10:18, Charlotte �leÅkec wrote:
>> From: Max Fierke
>>
>> The CWD686 is a 6.86" IPS LCD panel used as the primary
>> display in the ClockworkPi DevTerm portable (all cores)
>>
>> Co-authored-by: Charlotte DeleÅkec
>> Signed-off-by: C
From: Paul-pl Chen
Add mediatek,blender.yaml to support BLENDER for MT8196.
MediaTek display overlap blender, namely OVL_BLENDER or BLENDER,
executes the alpha blending function for overlapping layers
from different sources.
Signed-off-by: Paul-pl Chen
---
.../display/mediatek/mediatek,blender
On Mon, 31 Mar 2025, Thadeu Lima de Souza Cascardo wrote:
> From: Wayne Lin
>
> [ Upstream commit bc068194f548ef1f230d96c4398046bf59165992 ]
>
> [Why]
> Observe after suspend/resme, we can't light up mst monitors under specific
> mst hub.
This is already at stable backport stage, but it would re
Start using the new helper that does the refcounted
allocations
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/panel/panel-ilitek-ili9805.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9805.c
b/drivers/gpu/drm/panel/p
To enable or disable the sharpness check the
casf_enable flag. While enabling the sharpness
write the programmable coefficients, sharpness
register bits and also enable the scaler.
Load the filter lut value which needs to be done
one time while enabling the sharpness.
v2: Introduce casf_enable her
Currently the job free work item will lock sched->job_list_lock first time
to see if there are any jobs, free a single job, and then lock again to
decide whether to re-queue itself if there are more finished jobs.
Since drm_sched_get_finished_job() already looks at the second job in the
queue we c
Following the dyndbg-api-fix, replace DECLARE_DYNDBG_CLASSMAP with
DRM_CLASSMAP_USE. This refs the defined & exported classmap, rather
than re-declaring it redundantly, and error-prone-ly.
This resolves the appearance of "class:_UNKNOWN_" in the control file
for the driver's drm_dbg()s.
Fixes: f
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/panel/panel-lg-lg4573.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-lg-lg4573.c
b/drivers/gpu/drm/panel/pane
On 3/3/25 1:42 PM, Boris Brezillon wrote:
Hi,
This looks like it has been part of a R50 release of the DDK, which is recent
enough to consider it up-to-date. The issues you're seeing with fast resume are
probably due to some integration issues or other quirks.
Boris has the most recent experie
Add __DYNAMIC_DEBUG_CLASSMAP_CHECK to implement the following
arg-checks at compile-time:
0 <= _base < 63
class_names is not empty
class_names[0] is a string
(class_names.length + _base) < 63
These compile-time checks will prevent several misuses; 4 such
examples a
On Thu, 2025-04-03 at 12:13 +0200, Philipp Stanner wrote:
> Nouveau currently relies on the assumption that dma_fences will only
> ever get signalled through nouveau_fence_signal(), which takes care
> of
> removing a signalled fence from the list nouveau_fence_chan.pending.
>
> This self-imposed r
Fix missing includes and struct declarations. Even if these don't cause
any compile issues at the moment, it's good to have them correct.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/tidss/tidss_dispc.h | 3 +++
drivers/gpu/drm/tidss/tidss_drv.h | 2 ++
drivers/gpu/drm/tidss/t
On 2025-04-02 14:00, Philipp Stanner wrote:
> On Wed, 2025-04-02 at 12:58 +0200, Michel Dänzer wrote:
>> On 2025-04-02 12:46, Philipp Stanner wrote:
>>> On Mon, 2025-03-31 at 21:16 +0100, Tvrtko Ursulin wrote:
Round-robin being the non-default policy and unclear how much it
is
used,
On Mon, 24 Mar 2025, Thomas Zimmermann wrote:
> Hi
>
> Am 21.03.25 um 12:27 schrieb Daniel Thompson:
> > On Fri, Mar 21, 2025 at 10:54:01AM +0100, Thomas Zimmermann wrote:
> > > Remove support for fb events from the lcd subsystem. Provide the
> > > helper lcd_notify_blank_all() instead. In fbdev,
The ->writepage operation is being removed. Since this function
exclusively deals with shmem folios, we can call shmem_writeout()
to write it.
Signed-off-by: Matthew Wilcox (Oracle)
---
drivers/gpu/drm/ttm/ttm_backup.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/
On 01.04.2025 19:24, Michal Wajdeczko wrote:
please use "drm/xe/vf:" in the subject as this patch is still more VF
oriented, then general SRIOV
ok.
On 31.03.2025 15:21, Tomasz Lis wrote:
We have only one GGTT for all IOV functions, with each VF having assigned
a range of addresses for its use
If we are only reading the memory then from the device pov the direction
can be DMA_TO_DEVICE. This aligns with the xe-userptr code. Using the
most restrictive data direction to represent the access is normally a
good idea.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Matthew Brost
Revi
old_bits arg is currently a pointer to the input bits, but this could
allow inadvertent changes to the input by the fn. Disallow this.
And constify new_bits while here.
Signed-off-by: Jim Cromie
Reviewed-by: Louis Chauvet
---
lib/dynamic_debug.c | 21 +++--
1 file changed, 11 i
On Mon, Mar 24, 2025 at 9:24 AM Louis Chauvet wrote:
>
>
>
> Le 20/03/2025 à 19:52, Jim Cromie a écrit :
> > Invoke DRM_CLASSMAP_USE from xe_drm_client.c. When built with
> > CONFIG_DRM_USE_DYNAMIC_DEBUG=y, this tells dydnbg that Xe uses
> > has drm.debug calls.
> >
> > Signed-off-by: Jim Cromie
Reduce the scope of some loop counters as these aren't needed outside
the loops they're used in.
Signed-off-by: Alexandru Dadu
---
Changes in v2:
- Remove a loop counter variable definition
- Link to v1:
https://lore.kernel.org/r/20250401-for-loop-counter-scope-v1-1-5ba75770b...@imgtec.com
---
At the moment the driver just sets the clock rate with clk_set_rate(),
and if the resulting rate is not the same as requested, prints a debug
print, but nothing else.
Add mode_fixup(), in which the clk_round_rate() is used to get the
"rounded" rate, and set that to the adjusted_mode.
In practice,
If the new deadline policy is at least as good as FIFO and we can afford
to remove round-robin, we can simplify the scheduler code by making the
scheduler to run queue relationship always 1:1 and remove some code.
Also, now that the FIFO policy is gone the tree of entities is not a FIFO
tree any m
On Wed, 26 Mar 2025 23:29:19 -0400, Anusha Srivatsa wrote:
> Move away from using deprecated API and use _multi variants
> if available. Use mipi_dsi_msleep() and mipi_dsi_usleep_range()
> instead of msleep() and usleep_range() respectively.
>
> Used Coccinelle to find the _multi variant APIs,repl
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, March 18, 2025 1:09 PM
> To: Borah, Chaitanya Kumar ; dri-
> de...@lists.freedesktop.org; intel-...@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org
> Cc: Kumar, Naveen1
> Subject: RE: [PATCH v8 1/3] drm/plane: Add n
On Wed, Mar 26, 2025 at 05:26:11PM +0200, Alexander Usyskin wrote:
> Add driver for access to Intel discrete graphics card
> internal NVM device.
> Expose device on auxiliary bus by i915 and Xe drivers and
> provide mtd driver to register this device with MTD framework.
>
> This is a rewrite of "d
Add a selftest script for dynamic-debug. The config requires
CONFIG_TEST_DYNAMIC_DEBUG=m and CONFIG_TEST_DYNAMIC_DEBUG_SUBMOD=m,
which tacitly requires either CONFIG_DYNAMIC_DEBUG=y or
CONFIG_DYNAMIC_DEBUG_CORE=y
ATM this has just basic_tests(), which modify pr_debug() flags in the
builtin params
On Mon, 31 Mar 2025 17:54:56 +0300
Laurent Pinchart wrote:
> On Mon, Mar 31, 2025 at 01:53:37PM +0300, Pekka Paalanen wrote:
> > On Mon, 31 Mar 2025 11:21:35 +0300 Laurent Pinchart wrote:
> > > On Mon, Mar 31, 2025 at 10:54:46AM +0300, Pekka Paalanen wrote:
> > > > On Thu, 27 Mar 2025 17:35:3
On Thu, 20 Mar 2025 11:17:39 +
Karunika Choo wrote:
> As the FLUSH_MEM and FLUSH_PT commands are deprecated in GPUs from
> Mali-G720 onwards, this patch adds support for performing cache
> maintenance via the FLUSH_CACHES command in GPU_CONTROL, in place of
> FLUSH_MEM and FLUSH_PT based on P
This lets the UMD flag buffers are alloc-on-fault (AKA lazy allocation,
AKA alloc-on-demand). The ultimate goal is to use this infrastructure
for heap objects, but commit only deals with GEM/VM bits.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/panthor/panthor_drv.c | 20 +-
drivers/gpu/d
The Cadence DSI requires negative syncs from the incoming video signal,
but at the moment that requirement is not expressed in any way. If the
crtc decides to use positive syncs, things break down.
Use the adjusted_mode in atomic_check to set the sync flags to negative
ones.
Signed-off-by: Tomi V
On 31/03/2025 18:39, Christopher Obbard wrote:
Hi Johan,
On Mon, 31 Mar 2025 at 09:50, Johan Hovold wrote:
On Thu, Mar 27, 2025 at 04:56:53PM +, Christopher Obbard wrote:
The eDP panel has an HPD GPIO. Describe it in the device tree
for the generic T14s model, as the HPD GPIO property is
On 3/20/2025 9:27 PM, Ekansh Gupta wrote:
>
> On 3/20/2025 7:45 PM, Dmitry Baryshkov wrote:
>> On Thu, Mar 20, 2025 at 07:19:31PM +0530, Ekansh Gupta wrote:
>>> On 1/29/2025 4:10 PM, Dmitry Baryshkov wrote:
On Wed, Jan 29, 2025 at 11:12:16AM +0530, Ekansh Gupta wrote:
> On 1/29/2025 4:5
On Thu, 20 Mar 2025 16:42:11 +0100, Luca Ceresoli wrote:
> DRM bridges are currently considered as a fixed element of a DRM card, and
> thus their lifetime is assumed to extend for as long as the card
> exists. New use cases, such as hot-pluggable hardware with video bridges,
> require DRM bridges
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/panel/panel-ilitek-ili9341.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9341.c
b/drivers/gpu/drm/pane
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Signed-off-by: Anusha Srivatsa
---
v2: none.
---
drivers/gpu/drm/panel/panel-leadtek-ltk500hd1829.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-leadtek-ltk500hd
Hello,
Now that the freedesktop server migration is almost done, it's time to
turn our attention on the 2025 X.Org Foundation elections, which are
rapidly approaching! We will be forwarding the election schedule and
nominating process to the membership shortly.
Please note that only current membe
Some functions used by the HVS->PV muxing tests can return with EDEADLK,
meaning the entire sequence should be restarted. It's not a fatal error
and we should treat it as a recoverable error, and recover, instead of
failing the test like we currently do.
Fixes: 76ec18dc5afa ("drm/vc4: tests: Add u
From: David Yat Sin
[ Upstream commit e90711946b53590371ecce32e8fcc381a99d6333 ]
If queue size is less than minimum, clamp it to minimum to prevent
underflow when writing queue mqd.
Signed-off-by: David Yat Sin
Reviewed-by: Jay Cornwall
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex
> > > > 4K30(3840x2160 30Hz) timing pixel clock around 297M, for 24bits
> > > > RGB pixel data format, total transport bandwidth need 297M*24(at
> > > > least
> > > > 7.2Gbps) more than anx7625 mipi rx lane bandwidth(maximum 6Gbps,
> > > > 4lanes, each lane 1.5Gbps). Without DSC function, anx7625 c
On 02/04/2025 11:38, Ekansh Gupta wrote:
On 3/21/2025 5:53 PM, Srinivas Kandagatla wrote:
On 20/03/2025 18:43, Dmitry Baryshkov wrote:
On Thu, Mar 20, 2025 at 05:11:20PM +, Srinivas Kandagatla wrote:
On 20/03/2025 09:14, Ling Xu wrote:
The fastrpc driver has support for 5 types of r
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