[PATCH 9/9] drm/doc: Polish docs for drm_property_property_blob

- remove kerneldoc for drm-internal functions - drm_property_replace_global_blob isn't actually atomic, and doesn't need to be. Update docs to match - document all the types and try to link things a bit better - nits all over Signed-off-by: Daniel Vetter --- Documentation/gpu/drm-kms.rst |

[PATCH 8/9] drm: Unify handling of blob and object properties

They work exactly the same now, after the refcounting unification a bit ago. The only reason they're distinct is backwards compat with existing userspace. Cc: Daniel Stone Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_property.c | 23 +-- 1 file changed, 5

[PATCH 7/9] drm: Extract drm_property.[hc]

This just contains the base property classes and all the code to handle blobs. I think for any kind of standardized/shared properties it's better to have separate files - this is fairly big already as-is. v2: resurrect misplaced hunk (Daniel Stone) Cc: Daniel Stone Signed-off-by: Daniel Vetter

[PATCH 6/9] drm: move drm_mode_legacy_fb_format to drm_fourcc.c

It's part of the drm fourcc handling code, mapping the old depth/bpp values to new fourcc codes. Cc: Laurent Pinchart Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 43 --- drivers/gpu/drm/drm_fourcc.c | 43

[PATCH 5/9] drm/doc: Polish docs for drm_mode_object

I figured an overview section here is overkill, and better to just document the 2 structures themselves well enough. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_mode_object.c | 9 +++ include/drm/drm_mode_object.h | 50 --- 2 files changed,

[PATCH 4/9] drm: Remove drm_mode_object->atomic_count

It's only used in drm_mode_object_get_properties, and we can compute it there directly with a bit of code shuffling. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_mode_object.c | 31 --- include/drm/drm_mode_object.h | 2 +- 2 files changed, 13

[PATCH 3/9] drm: Extract drm_mode_object.[hc]

Just for the struct drm_mode_object base class. The header file was already partially extracted to help untangle the include loops. v2: - Also move the generic get/set property ioctls. At first this seemed like a bad idea since it requires making drm_mode_crtc_set_obj_prop non-static. But

[PATCH 2/9] drm/doc: Polish kerneldoc for encoders

- Move missing bits into struct drm_encoder docs. - Explain that encoders are 95% internal and only 5% uapi, and that in general the uapi part is broken. - Remove verbose comments for functions not exposed to drivers. Signed-off-by: Daniel Vetter --- Documentation/gpu/drm-kms.rst | 46

[PATCH 1/9] drm: Extract drm_encoder.[hc]

Same treatment as before. Only hiccup is drm_crtc_mask, which unfortunately can't be resolved until drm_crtc.h is less of a monster. Untangle the header loop with a forward delcaration for that static inline. Signed-off-by: Daniel Vetter --- Documentation/gpu/drm-kms.rst | 9 ++

Use of copy_from_user in msm_gem_submit.c while holding a spin_lock

On Wed, Aug 17, 2016 at 03:24:38PM -0400, Rob Clark wrote: > hmm, looks like, at least on arm (not sure about arm64), > > #define __copy_from_user_inatomic __copy_from_user > > ie. copy_from_user() minus the access_ok() and memset in the > !access_ok() path.. but maybe what I want is just the >

Use of copy_from_user in msm_gem_submit.c while holding a spin_lock

On Wed, Aug 17, 2016 at 02:49:32PM -0400, Rob Clark wrote: > I'm not saying that I shouldn't fix it (although not quite sure how > yet.. taking/dropping the spinlock inside the loop is not a good > option from a performance standpoint). What I am saying is that this > is not something that can

"Fixes" for page flipping under PRIME on AMD & nouveau

Am 17.08.2016 um 18:35 schrieb Mario Kleiner: > On 08/17/2016 06:27 PM, Christian König wrote: >>> AMD uses copy swaps because radeon/amdgpu kms can't switch the >>> scanout mode from tiled to linear on the fly during flips. >> Well I'm not an expert on this, but as far as I know the bigger

[PATCH 2/2] drm/hisilicon: Make it compile again

Hi, On 17 August 2016 at 18:17, Daniel Vetter wrote: > I just broke the build :( > > Note that the cleanup function is a bit confused: ade_data was never > set as drvdata, and calling drm_crtc_cleanup directly is a bug - this Yes, this is a bug. Thanks for pointing out this. > is called

"Fixes" for page flipping under PRIME on AMD & nouveau

On 08/17/2016 06:27 PM, Christian König wrote: >> AMD uses copy swaps because radeon/amdgpu kms can't switch the >> scanout mode from tiled to linear on the fly during flips. > Well I'm not an expert on this, but as far as I know the bigger problem > is that the dedicated AMD hardware generations

"Fixes" for page flipping under PRIME on AMD & nouveau

> AMD uses copy swaps because radeon/amdgpu kms can't switch the > scanout mode from tiled to linear on the fly during flips. Well I'm not an expert on this, but as far as I know the bigger problem is that the dedicated AMD hardware generations you are targeting usually can't reliable scanout

[PATCH 2/2] drm/radeon: Fix pageflipping of PRIME imported scanout bo's.

Scanout bo's which are dmabuf backed in RAM and imported via prime will not update their content with new rendering from the renderoffload gpu once they've been flipped onto the scanout once. The reason is that at preparation of first flip they get pinned into VRAM, then unpinned at some later

[PATCH 1/2] drm/nouveau: Fix pageflipping of PRIME imported scanout bo's.

Scanout bo's which are dmabuf backed in RAM and imported via prime will not update their content with new rendering from the renderoffload gpu once they've been flipped onto the scanout once. The reason is that at preparation of first flip they get pinned into VRAM, then unpinned at some later

"Fixes" for page flipping under PRIME on AMD & nouveau

Hi, i spent some time playing with DRI3/Present + PRIME for testing how well it works for Optimus/Enduro style setups wrt. page flipping on the current kernel/mesa/xorg. I want page flipping, because neuroscience/medical applications need the reliable timing/timestamping and tear free

Use of copy_from_user in msm_gem_submit.c while holding a spin_lock

On Wed, Aug 17, 2016 at 11:08:46AM -0400, Rob Clark wrote: > On Wed, Aug 17, 2016 at 7:40 AM, Vaishali Thakkar > wrote: > > Hello, > > > > I was wondering about the call to copy_from_user in function > > submit_lookup_objects for drive > > /gpu/drm/msm/msm_gem_submit.c It calls

[PATCH] drm/tegra: dsi: Enhance runtime power management

From: Thierry Reding The MIPI DSI output on Tegra SoCs requires some external logic to calibrate the MIPI pads before a video signal can be transmitted. This MIPI calibration logic requires to be powered on while the MIPI pads are being used, which is currently done as part

[PATCH v4 4/4] gpu: ipu-ic: allow multiple handles to ic

The image converter kernel API supports conversion contexts and job queues, so we should allow more than one handle to the IC, so that multiple users can add jobs to the queue. Note however that users that control the IC manually (that do not use the image converter APIs but setup the IC task by

[PATCH v4 3/4] gpu: ipu-ic: Add complete image conversion support with tiling

This patch implements complete image conversion support to ipu-ic, with tiling to support scaling to and from images up to 4096x4096. Image rotation is also supported. The internal API is subsystem agnostic (no V4L2 dependency except for the use of V4L2 fourcc pixel formats). Callers prepare for

[PATCH v4 2/4] gpu: ipu-v3: Add FSU channel linking support

Adds functions to link and unlink source channels to sink channels in the FSU: int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch); int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch); The channels numbers are usually IDMAC channels, but they can also be channels that do

[PATCH v4 1/4] gpu: ipu-v3: Add Video Deinterlacer unit

Adds the Video Deinterlacer (VDIC) unit. Signed-off-by: Steve Longerbeam --- v4: - pruned included headers. v3: - renamed and exported ipu_vdi_set_top_field_man() to ipu_vdi_set_field_order(). Args include std and field to determine correct field order. - exported ipu_vdi_set_motion(). -

[PATCH v4 0/4] IPUv3 prep for i.MX5/6 v4l2 staging drivers, v4

In this version: - rebased against latest drm-next. - cleaned up header includes in ipu-vdi.c. - do away with struct ipu_ic_tile_off in ipu-ic.c, and move tile offsets into struct ipu_ic_tile. This paves the way for possibly allowing for each tile to have different dimensions in the future.

Use of copy_from_user in msm_gem_submit.c while holding a spin_lock

On Wed, Aug 17, 2016 at 3:15 PM, Al Viro wrote: > On Wed, Aug 17, 2016 at 02:49:32PM -0400, Rob Clark wrote: >> If there is a copy_from_user() variant that will return an error >> instead of blocking, I think that is really what I want so I can >> implement a slow-path that drops the spin-lock

Use of copy_from_user in msm_gem_submit.c while holding a spin_lock

Hello, I was wondering about the call to copy_from_user in function submit_lookup_objects for drive /gpu/drm/msm/msm_gem_submit.c It calls copy_from_user[1] in a spin_lock, which is not normally allowed, due to the possibility of a deadlock. Is there some reason that I am overlooking why it

[PATCH v2] drm/imx: Add active plane reconfiguration support

Am Montag, den 15.08.2016, 16:41 +0800 schrieb Liu Ying: > We don't support configuring active plane on-the-fly for imx-drm. > The relevant CRTC should be disabled before the plane configuration. > Of course, the plane itself should be disabled as well. > This patch adds active plane

[Bug 97220] miss detect monitor. dell UP3214Q

for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160817/18206c71/attachment.html>

[Bug 97260] [bisected] R9 290 low performance in Linux 4.7

the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160817/7e9bae41/attachment.html>

[PATCH v12 7/7] drm/i915/skl: Update DDB values atomically with wms/plane attrs

Now that we can hook into update_crtcs and control the order in which we update CRTCs at each modeset, we can finish the final step of fixing Skylake's watermark handling by performing DDB updates at the same time as plane updates and watermark updates. The first major change in this patch is

[PATCH v12 6/7] drm/i915: Move CRTC updating in atomic_commit into it's own hook

Since we have to write ddb allocations at the same time as we do other plane updates, we're going to need to be able to control the order in which we execute modesets on each pipe. The easiest way to do this is to just factor this section of intel_atomic_commit_tail() (intel_atomic_commit() for

[PATCH v12 5/7] drm/i915/skl: Ensure pipes with changed wms get added to the state

If we're enabling a pipe, we'll need to modify the watermarks on all active planes. Since those planes won't be added to the state on their own, we need to add them ourselves. Signed-off-by: Lyude Reviewed-by: Matt Roper Cc: stable at vger.kernel.org Cc: Ville Syrjälä Cc: Daniel Vetter Cc:

[PATCH v12 4/7] drm/i915/skl: Update plane watermarks atomically during plane updates

Thanks to Ville for suggesting this as a potential solution to pipe underruns on Skylake. On Skylake all of the registers for configuring planes, including the registers for configuring their watermarks, are double buffered. New values written to them won't take effect until said registers are

[PATCH v12 3/7] drm/i915/gen9: Only copy WM results for changed pipes to skl_hw

From: Matt Roper When we write watermark values to the hardware, those values are stored in dev_priv->wm.skl_hw. However with recent watermark changes, the results structure we're copying from only contains valid watermark and DDB values for the pipes that are

[PATCH v12 2/7] drm/i915/skl: Add support for the SAGV, fix underrun hangs

Since the watermark calculations for Skylake are still broken, we're apt to hitting underruns very easily under multi-monitor configurations. While it would be lovely if this was fixed, it's not. Another problem that's been coming from this however, is the mysterious issue of underruns causing

[PATCH v12 1/7] drm/i915/gen6+: Interpret mailbox error flags

In order to add proper support for the SAGV, we need to be able to know what the cause of a failure to change the SAGV through the pcode mailbox was. The reasoning for this is that some very early pre-release Skylake machines don't actually allow you to control the SAGV on them, and indicate an

[PATCH v12 0/7] Finally fix watermarks

Patches that actually changed (please re-review: drm/i915/gen6+: Interpret mailbox error flags drm/i915/skl: Add support for the SAGV, fix underrun hangs drm/i915/skl: Update DDB values atomically with wms/plane attrs Everything else is the same. Updated version of

[PATCH v2] drm/rockchip: Don't continue trying to enable crtc on failure

Sean, On 08/16/2016 07:12 AM, Sean Paul wrote: > If vop_enable fails, don't continue on, it causes system hangs. > > Signed-off-by: Sean Paul Also meet this problem on my Rk3399 Kevin board. VOP just failed to get the pm_runtime at resume time, but ｄｒｉｖer still just continue without

Use of copy_from_user in msm_gem_submit.c while holding a spin_lock

On Wed, Aug 17, 2016 at 3:15 PM, Al Viro wrote: > On Wed, Aug 17, 2016 at 02:49:32PM -0400, Rob Clark wrote: > >> I'm not saying that I shouldn't fix it (although not quite sure how >> yet.. taking/dropping the spinlock inside the loop is not a good >> option from a performance standpoint). What

[pull] amdgpu drm-fixes-4.8

Hi Dave, Just one small fix for amdgpu this week for systems with a gart aperture > 4 GB. The following changes since commit 93b1f14553a5f48104b639d28e41c2bb73c0dc37: Merge tag 'mediatek-drm-fixes-2016-08-12' of git://git.pengutronix.de/git/pza/linux into drm-fixes (2016-08-15 16:07:14

[PATCH 1/2] drm/hisilicon: Allow compile-testing on arm

On 17 August 2016 at 11:17, Daniel Vetter wrote: > diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst > index d5ad60d3cf06..6544c74d250a 100644 > --- a/Documentation/gpu/drm-kms.rst > +++ b/Documentation/gpu/drm-kms.rst > @@ -389,6 +389,15 @@ connector and plane objects by

Use of copy_from_user in msm_gem_submit.c while holding a spin_lock

On Wed, Aug 17, 2016 at 2:49 PM, Rob Clark wrote: > On Wed, Aug 17, 2016 at 1:08 PM, Al Viro wrote: >> On Wed, Aug 17, 2016 at 11:08:46AM -0400, Rob Clark wrote: >>> On Wed, Aug 17, 2016 at 7:40 AM, Vaishali Thakkar >>> wrote: >>> > Hello, >>> > >>> > I was wondering about the call to

[PATCH v4 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K

From: Junzhi Zhao Pixel clock should be 297MHz when resolution is 4K. Signed-off-by: Junzhi Zhao Signed-off-by: Bibby Hsieh --- drivers/gpu/drm/mediatek/mtk_dpi.c |9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git

[PATCH v4 2/3] drm/mediatek: enhance the HDMI driving current

From: Junzhi Zhao In order to improve 4K resolution performance, we have to enhance the HDMI driving current when clock rate is greater than 165MHz. Signed-off-by: Junzhi Zhao Signed-off-by: Bibby Hsieh --- drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 42

[PATCH v4 1/3] drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable

From: Junzhi Zhao The mtk_hdmi_send_infoframe have to be run after PLL and PIXEL clock of HDMI enable. Make sure that HDMI inforframes can be sent successfully. Signed-off-by: Junzhi Zhao Signed-off-by: Bibby Hsieh --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 17

[PATCH v4 0/3] MT8173 HDMI 4K support

This is MT8173 HDMI 4K support PATCH v4, based on 4.8-rc1. In order to support HDMI 4K on MT8173, we have to make some modifications. 1) Make sure that mtk_hdmi_send_infoframe is sent successfully. 2) Enhance the HDMI driving current to improve performance. 3) Make sure that pixel clock is 297MHz

Use of copy_from_user in msm_gem_submit.c while holding a spin_lock

On Wed, Aug 17, 2016 at 1:08 PM, Al Viro wrote: > On Wed, Aug 17, 2016 at 11:08:46AM -0400, Rob Clark wrote: >> On Wed, Aug 17, 2016 at 7:40 AM, Vaishali Thakkar >> wrote: >> > Hello, >> > >> > I was wondering about the call to copy_from_user in function >> > submit_lookup_objects for drive >>

[PATCH v5 3/4] drm/bridge: analogix_dp: add the PSR function support

Hello Archit, On 08/17/2016 01:41 PM, Archit Taneja wrote: > Hi, > > On 07/24/2016 12:27 PM, Yakir Yang wrote: >> The full name of PSR is Panel Self Refresh, panel device could refresh >> itself with the hardware framebuffer in panel, this would make lots of >> sense to save the power

[PATCH] drm/rockchip: analogix_dp: drop unnecessary probe deferral "error" print

On Wed, Aug 17, 2016 at 2:10 PM, Brian Norris wrote: > This driver is the only user of of_drm_find_panel() which prints an > error before doing probe deferral, yielding messages like this on boot, > before eventually succeeding: > > [2.234271] [drm:rockchip_dp_probe] *ERROR* failed to find

[PATCH] drm/rockchip: analogix_dp: drop unnecessary probe deferral "error" print

This driver is the only user of of_drm_find_panel() which prints an error before doing probe deferral, yielding messages like this on boot, before eventually succeeding: [2.234271] [drm:rockchip_dp_probe] *ERROR* failed to find panel ... [4.797539] [drm:rockchip_dp_probe] *ERROR* failed

[PATCH v6 6/8] Documentation: bindings: add dt documentation for rk3399 dmc

Hi Lin, On 2016년 08월 17일 07:36, Lin Huang wrote: > This patch adds the documentation for rockchip rk3399 dmc driver. > > Signed-off-by: Lin Huang > --- > Changes in v6: > -Add more detail in Documentation > > Changes in v5: > -None > > Changes in v4: > -None > > Changes in v3: > -None

[PATCH v8 12/12] drm/i915: Check TMDS clock DP to HDMI dongle

Respect max TMDS clock frequency from DPCD for active DP to HDMI adapters. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_drv.h | 3 +++ drivers/gpu/drm/i915/intel_hdmi.c | 27 +++ 2 files changed, 30 insertions(+) diff --git

[PATCH v8 11/12] drm: Add DP branch device info on debugfs

Read DisplayPort branch device info from through debugfs interface. v2: use drm_dp_helper routines to collect data v3: cleanup to match the drm_dp_helper.c patches introduced earlier in this series v4: move DP branch device info to function 'intel_dp_branch_device_info()' v5: initial step to

[PATCH v8 10/12] drm/i915: Update bits per component for display info

DisplayPort branch device may define max supported bits per component. Update display info based on this value if bpc is defined. v2: cleanup to match the drm_dp_helper.c patches introduced earlier in this series v3: Fill bpc for connector's display info in separate drm_dp_helper function

[PATCH v8 09/12] drm/i915: Check pixel rate for DP to VGA dongle

Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and

[PATCH v8 09/12] Check pixel rate for DP to VGA dongle

Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and

[PATCH v8 08/12] drm/i915: Read DP branch device SW revision

SW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x50A. v2: move drm_dp_ds_revision structure to be part of drm_dp_link structure (Daniel) v3: remove dependency to drm_dp_helper but instead parse DPCD and print SW revision info to dmesg

[PATCH v8 07/12] drm/i915: Read DP branch device HW revision

HW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x509. v2: move drm_dp_ds_revision structure to be part of drm_dp_link structure (Daniel) v3: remove dependency to drm_dp_helper but instead parse DPCD and print HW revision info to dmesg

[PATCH v8 06/12] drm/i915: Cleanup DisplayPort AUX channel initialization

Let's remove reference to "struct intel_connector *connector" in intel_dp_aux_init() function as it is no longer required. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c

[PATCH v8 05/12] drm: Read DP branch device id

Read DisplayPort branch device id string. Reviewed-by: Jim Bride Signed-off-by: Mika Kahola --- drivers/gpu/drm/drm_dp_helper.c | 12 include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c

[PATCH v8 04/12] drm: Helper to read max bits per component

Helper routine to read out maximum supported bits per component for DisplayPort legay converters. v2: Return early if detailed port cap info is not available. Replace if-else ladder with switch-case (Ville) Reviewed-by: Jim Bride Signed-off-by: Mika Kahola ---

[PATCH v8 03/12] drm: Helper to read max clock rate

Helper routine to read out maximum supported pixel rate for DisplayPort legay VGA converter or TMDS clock rate for other digital legacy converters. The helper returns clock rate in kHz. v2: Return early if detailed port cap info is not available. Replace if-else ladder with switch-case

[PATCH v8 02/12] drm: Drop VGA from bpc definitions

Drop "VGA" from bits per component definitions as these are also used by other standards such as DVI, HDMI, DP++. Reviewed-by: Jim Bride Signed-off-by: Mika Kahola --- include/drm/drm_dp_helper.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[PATCH v8 01/12] drm: Add missing DP downstream port types

Add missing DisplayPort downstream port types. The introduced new port types are DP++ and Wireless. Reviewed-by: Jim Bride Signed-off-by: Mika Kahola --- include/drm/drm_dp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h

[PATCH v8 00/12] drm/i915: DP branch devices

Prep work for DP branch device handling This series of patches reads DPCD register 0x80h for receiver capabilities for DP branch devices. The branch device types are converters for the following standards - DP to VGA - DP to DVI - DP to HDMI - DP++ dual mode - Wireless WiGig DPCD register

"Fixes" for page flipping under PRIME on AMD & nouveau

On Wed, Aug 17, 2016 at 12:35 PM, Mario Kleiner wrote: > On 08/17/2016 06:27 PM, Christian König wrote: >>> >>> AMD uses copy swaps because radeon/amdgpu kms can't switch the >>> scanout mode from tiled to linear on the fly during flips. >> >> Well I'm not an expert on this, but as far as I know

[PATCH] drm/hisilicon: add back missing } on ade_dc_ops

On Wed, Aug 17, 2016 at 12:09:24PM +0100, Colin King wrote: > From: Colin Ian King > > Fix build error by adding back the closing } on ade_dc_ops which > got accidentally removed from an earlier commit. > > Fixes: d25bcfb8c2e18b9b36 ("Don't set drm_device->platformdev") Yeah that patch was

[PATCH v8 12/12] drm/i915: Check TMDS clock DP to HDMI dongle

Respect max TMDS clock frequency from DPCD for active DP to HDMI adapters. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_drv.h | 3 +++ drivers/gpu/drm/i915/intel_hdmi.c | 27 +++ 2 files changed, 30 insertions(+) diff --git

[PATCH v8 11/12] drm: Add DP branch device info on debugfs

Read DisplayPort branch device info from through debugfs interface. v2: use drm_dp_helper routines to collect data v3: cleanup to match the drm_dp_helper.c patches introduced earlier in this series v4: move DP branch device info to function 'intel_dp_branch_device_info()' v5: initial step to

[PATCH v8 10/12] drm/i915: Update bits per component for display info

DisplayPort branch device may define max supported bits per component. Update display info based on this value if bpc is defined. v2: cleanup to match the drm_dp_helper.c patches introduced earlier in this series v3: Fill bpc for connector's display info in separate drm_dp_helper function

[PATCH v8 09/12] drm/i915: Check pixel rate for DP to VGA dongle

Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and

[PATCH v8 09/12] Check pixel rate for DP to VGA dongle

Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and

[PATCH v8 08/12] drm/i915: Read DP branch device SW revision

SW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x50A. v2: move drm_dp_ds_revision structure to be part of drm_dp_link structure (Daniel) v3: remove dependency to drm_dp_helper but instead parse DPCD and print SW revision info to dmesg

[PATCH v8 07/12] drm/i915: Read DP branch device HW revision

HW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x509. v2: move drm_dp_ds_revision structure to be part of drm_dp_link structure (Daniel) v3: remove dependency to drm_dp_helper but instead parse DPCD and print HW revision info to dmesg

[PATCH v8 06/12] drm/i915: Cleanup DisplayPort AUX channel initialization

Let's remove reference to "struct intel_connector *connector" in intel_dp_aux_init() function as it is no longer required. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c

[PATCH v8 05/12] drm: Read DP branch device id

Read DisplayPort branch device id string. Reviewed-by: Jim Bride Signed-off-by: Mika Kahola --- drivers/gpu/drm/drm_dp_helper.c | 12 include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c

[PATCH v8 04/12] drm: Helper to read max bits per component

Helper routine to read out maximum supported bits per component for DisplayPort legay converters. v2: Return early if detailed port cap info is not available. Replace if-else ladder with switch-case (Ville) Reviewed-by: Jim Bride Signed-off-by: Mika Kahola ---

[PATCH v8 03/12] drm: Helper to read max clock rate

Helper routine to read out maximum supported pixel rate for DisplayPort legay VGA converter or TMDS clock rate for other digital legacy converters. The helper returns clock rate in kHz. v2: Return early if detailed port cap info is not available. Replace if-else ladder with switch-case

[PATCH v8 02/12] drm: Drop VGA from bpc definitions

Drop "VGA" from bits per component definitions as these are also used by other standards such as DVI, HDMI, DP++. Reviewed-by: Jim Bride Signed-off-by: Mika Kahola --- include/drm/drm_dp_helper.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[PATCH v8 01/12] drm: Add missing DP downstream port types

Add missing DisplayPort downstream port types. The introduced new port types are DP++ and Wireless. Reviewed-by: Jim Bride Signed-off-by: Mika Kahola --- include/drm/drm_dp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h

[PATCH v8 00/12] drm/i915: DP branch devices

Prep work for DP branch device handling This series of patches reads DPCD register 0x80h for receiver capabilities for DP branch devices. The branch device types are converters for the following standards - DP to VGA - DP to DVI - DP to HDMI - DP++ dual mode - Wireless WiGig DPCD register

[PATCH 2/2] drm/hisilicon: Make it compile again

On Wed, Aug 17, 2016 at 07:02:01PM +0800, Xinliang Liu wrote: > Hi, > > On 17 August 2016 at 18:17, Daniel Vetter wrote: > > I just broke the build :( > > > > Note that the cleanup function is a bit confused: ade_data was never > > set as drvdata, and calling drm_crtc_cleanup directly is a bug -

drm/bridge: dw_hdmi: Colorspace registers

On Wed, Aug 17, 2016 at 12:37:27PM +0100, Jose Abreu wrote: > Hi Russell, > > > On 17-08-2016 12:21, Russell King - ARM Linux wrote: > > On Wed, Aug 17, 2016 at 10:33:10AM +0100, Jose Abreu wrote: > >> Hi Russell, > >> > >> When using driver dw-hdmi in any other colorspace than RGB the > >> Y1,

[PATCH v3 1/3] drm: add SimpleDRM driver

On Wed, Aug 17, 2016 at 12:19:02PM +0200, Noralf Trønnes wrote: > > Den 17.08.2016 11:30, skrev Daniel Vetter: > > On Tue, Aug 16, 2016 at 9:38 PM, Noralf Trønnes > > wrote: > > > > That's still a lot for what amounts to reimplementing mmap on shmem, but > > > > badly. What I mean with

[Bug 97371] AMDGPU/Iceland amdgpu: failed testing IB on ring 9/10

es/dri-devel/attachments/20160817/cbc53e9a/attachment.html>

drm/bridge: dw_hdmi: Colorspace registers

Hi Russell, On 17-08-2016 12:21, Russell King - ARM Linux wrote: > On Wed, Aug 17, 2016 at 10:33:10AM +0100, Jose Abreu wrote: >> Hi Russell, >> >> When using driver dw-hdmi in any other colorspace than RGB the >> Y1, Y0 and YCC values are not correct. I confirmed in databook >> that these

drm/bridge: dw_hdmi: Colorspace registers

On Wed, Aug 17, 2016 at 10:33:10AM +0100, Jose Abreu wrote: > Hi Russell, > > When using driver dw-hdmi in any other colorspace than RGB the > Y1, Y0 and YCC values are not correct. I confirmed in databook > that these registers are being written to the wrong offset (per > my databook they should

[PATCH v3 1/3] drm: add SimpleDRM driver

Den 17.08.2016 11:30, skrev Daniel Vetter: > On Tue, Aug 16, 2016 at 9:38 PM, Noralf Trønnes > wrote: >>> That's still a lot for what amounts to reimplementing mmap on shmem, but >>> badly. What I mean with redirecting is pointing the entire ->mmap >>> operation to the mmap implementation for

[PATCH 2/2] drm/hisilicon: Make it compile again

I just broke the build :( Note that the cleanup function is a bit confused: ade_data was never set as drvdata, and calling drm_crtc_cleanup directly is a bug - this is called indirectly through drm_mode_config_cleanup, which calls into crtc->destroy, which already has the call to

[PATCH 1/2] drm/hisilicon: Allow compile-testing on arm

I just broke the build :( Cc: Xinliang Liu Cc: Xinwei Kong Cc: Chen Feng Cc: Sean Paul Fixes: d25bcfb8c2e1 ("drm/hisilicon: Don't set drm_device->platformdev") Signed-off-by: Daniel Vetter --- Documentation/gpu/drm-kms.rst | 9 + drivers/gpu/drm/hisilicon/kirin/Kconfig | 3

next-20160817 build: 2 failures 5 warnings (next-20160817)

On Wed, Aug 17, 2016 at 10:26:44AM +0100, Mark Brown wrote: > On Wed, Aug 17, 2016 at 08:28:17AM +0100, Build bot for Mark Brown wrote: > > Today's -next fails to build an arm64 allmodconfig due to: > > > arm64-allmodconfig > > ../drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c:140:18:

[Bug 97371] AMDGPU/Iceland amdgpu: failed testing IB on ring 9/10

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[PATCH] drm/hisilicon: add back missing } on ade_dc_ops

From: Colin Ian King Fix build error by adding back the closing } on ade_dc_ops which got accidentally removed from an earlier commit. Fixes: d25bcfb8c2e18b9b36 ("Don't set drm_device->platformdev") Signed-off-by: Colin Ian King ---

[Bug 97039] The Talos Principle and Serious Sam 3 GPU faults

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[Bug 97371] AMDGPU/Iceland amdgpu: failed testing IB on ring 9/10

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[Bug 97371] AMDGPU/Iceland amdgpu: failed testing IB on ring 9/10

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next-20160817 build: 2 failures 5 warnings (next-20160817)

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[Bug 97039] The Talos Principle and Serious Sam 3 GPU faults

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[PATCH v3 1/3] drm: add SimpleDRM driver

On Tue, Aug 16, 2016 at 9:38 PM, Noralf Trønnes wrote: >> That's still a lot for what amounts to reimplementing mmap on shmem, but >> badly. What I mean with redirecting is pointing the entire ->mmap >> operation to the mmap implementation for the underlying mmap. Roughly: >> >> /*

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