'destroy_workqueue()' already drains the queue before destroying it, so
there is no need to flush it explicitly.
Remove the redundant 'flush_workqueue()' calls.
Signed-off-by: Xu Wang
---
drivers/video/fbdev/omap2/omapfb/omapfb-main.c | 1 -
1 file changed, 1 deletion(-)
diff --git
On Thu, Jan 13, 2022 at 11:40 AM Xin Ji wrote:
>
> Hi Hsin-Yi, thanks for the patch! Please fix the follow comment, then
> add my id.
> Reviewed-by: Xin Ji
>
> On Tue, Jan 11, 2022 at 07:27:00PM +0800, Hsin-Yi Wang wrote:
> > Support reading edid through aux channel if panel is connected to aux
List panel under aux-bus node if it's connected to anx7625's aux bus.
Signed-off-by: Hsin-Yi Wang
Reviewed-by: Xin Ji
---
.../display/bridge/analogix,anx7625.yaml| 17 +
1 file changed, 17 insertions(+)
diff --git
Support reading edid through aux channel if panel is connected to aux
bus. Extend anx7625_aux_dpcd_trans() to implement aux transfer function:
1. panel is populated in devm_of_dp_aux_populate_ep_devices(), so move
anx7625_parse_dt() after.
2. Use pm runtime autosuspend since aux transfer
Use devm_kzalloc instead of kzalloc and drop kfree(). Let the memory
handled by driver detach.
Signed-off-by: Hsin-Yi Wang
Reviewed-by: Xin Ji
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git
On Thu, 13 Jan 2022 at 00:19, Rob Clark wrote:
>
> On Tue, Jan 11, 2022 at 1:31 PM Akhil P Oommen
> wrote:
> >
> > Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace
> > identify the sku.
> >
> > Signed-off-by: Akhil P Oommen
> > ---
> >
> >
Eliminate the follow smatch warnings:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3504 amdgpu_device_init()
warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1716
amdgpu_ras_error_status_query() warn: if statement not indented
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1058
Eliminate the following coccicheck warning:
./drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2725:16-17: Unneeded semicolon
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Realized that the GuC multi-lrc fini breadcrumb emit code is very
delicate as the math this code does relies on functions it calls to emit
a certain number of DWs. Add a few GEM_BUG_ONs to assert the math is
correct.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c
Quoting Yong Wu (2022-01-12 01:09:19)
> On Tue, 2022-01-11 at 16:27 -0800, Stephen Boyd wrote:
> > ---8<---
> > diff --git a/drivers/base/component.c b/drivers/base/component.c
> > index 64ad7478c67a..97f253a41bdf 100644
> > --- a/drivers/base/component.c
> > +++ b/drivers/base/component.c
> > @@
Quoting Kuogee Hsieh (2022-01-12 14:17:54)
>
> On 1/12/2022 12:00 PM, Stephen Boyd wrote:
> > Quoting Kuogee Hsieh (2022-01-11 10:43:23)
> >> Current DP drivers have regulators, clocks, irq and phy are grouped
> >> together within a function and executed not in a symmetric manner.
> >> This
There are only two lines in mtk_vcodec_release_enc_pm, using
pm_runtime_disable and put_device instead directly.
Move pm_runtime_enable outside mtk_vcodec_release_enc_pm to symmetry with
pm_runtime_disable, after that, rename mtk_vcodec_init_enc_pm to *_clk
since it only has clock operations now.
Add work queue to process core hardware information.
First, get lat_buf from message queue, then call core
hardware of each codec(H264/VP9/AV1) to decode, finally
puts lat_buf back to the message.
Signed-off-by: Yunfei Dong
Reviewed-by: Steve Cho
---
There are only two lines in mtk_vcodec_release_dec_pm, using
pm_runtime_disable and put_device instead directly.
Move pm_runtime_enable outside mtk_vcodec_init_dec_pm to symmetry with
pm_runtime_disable, after that, rename mtk_vcodec_init_dec_pm to *_clk
since it only has clock operations now.
There is just one core thread, in order to separate different
hardware, using codec type to separeate it in scp driver.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
.../media/platform/mtk-vcodec/vdec_ipi_msg.h | 12 ---
Generalizes power and clock on/off interfaces to support different
hardware.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 6 +-
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.c | 2 +-
Add core dec and dec end ipi msg:
AP_IPIMSG_DEC_CORE/AP_IPIMSG_DEC_CORE_END.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
.../media/platform/mtk-vcodec/vdec_ipi_msg.h | 4
.../media/platform/mtk-vcodec/vdec_vpu_if.c| 12
For lat and core architecture, lat thread will send message to core
thread when lat decode done. Core hardware will use the message
from lat to decode, then free message to lat thread when decode done.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
Use the dma_set_mask_and_coherent helper to set vdec
DMA bit mask to support 34bits iova space(16GB) that
the mt8192 iommu HW support.
Whole the iova range separate to 0~4G/4G~8G/8G~12G/12G~16G,
regarding which iova range VDEC actually locate, it
depends on the dma-ranges property of vdec dtsi
For add new hardware, not only need to lock lat hardware, also
need to lock core hardware in case of different instance start
to decoder at the same time.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 4 ++--
There are more than two hardwares for decoder: LAT0, LAT1 and CORE. In
order to manage these hardwares, register each hardware as independent
platform device for the larbs are different.
Each hardware module controls its own information which includes
interrupt/power/clocks/registers.
Calling
Separates different architecture for hardware: pure_sin_core
and lat_sin_core. MT8183 is pure single core. Uses .hw_arch to
distinguish.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
.../platform/mtk-vcodec/mtk_vcodec_dec_stateful.c | 1 +
Adds irq interface for multi hardware.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 33 ---
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.c | 2 +-
.../platform/mtk-vcodec/mtk_vcodec_drv.h | 25
Using the needed params for pm init/release function and remove unused
param mtkdev in 'struct mtk_vcodec_pm'.
Signed-off-by: Yunfei Dong
Reviewed-by: Tzung-Bi Shih
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Steve Cho
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 6 ++---
Adds decoder dt-bindings for mt8192.
Signed-off-by: Yunfei Dong
Reviewed-by: Rob Herring
---
.../media/mediatek,vcodec-subdev-decoder.yaml | 265 ++
1 file changed, 265 insertions(+)
create mode 100644
Separate decoder and encoder document for the dts are big difference.
Signed-off-by: Yunfei Dong
Reviewed-by: Rob Herring
---
.../media/mediatek,vcodec-decoder.yaml| 176 +
.../media/mediatek,vcodec-encoder.yaml| 187 ++
Adds MT8192's compatible "mediatek,mt8192-vcodec-dec".
Adds MT8192's device private data mtk_lat_sig_core_pdata.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
.../media/platform/mtk-vcodec/mtk_vcodec_dec.h | 1 +
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c |
Different platforms may have different numbers of register bases. Gets the
numbers of register bases from dts (sizeof(u32) * 4 bytes for each).
Signed-off-by: Yunfei Dong
Reviewed-by: Tzung-Bi Shih
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 37 ++-
1 file changed, 28
When mtk vcodec decoder is build as a module, we need to export
mtk-vcodec-dec pm functions to make them visible by the other components.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Benjamin Gaignard
---
Vdec and venc can use the same function to wake up interrupt event.
Signed-off-by: Yunfei Dong
Reviewed-by: Tzung-Bi Shih
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Steve Cho
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 9 +
This series adds support for multi hardware decode into mtk-vcodec, by first
adding use
of_platform_populate to manage each hardware information: interrupt, clock,
register
bases and power. Secondly add core work queue to deal with core hardware
message,
at the same time, add msg queue for
Thanks for your patch, Yang. Can you pls also fix the original indentation
problem as well?
if (!adev)
- return -EINVAL;;
+ return -EINVAL;
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Yang Li
Sent: Thursday, January 13, 2022 9:22 AM
To: airl...@linux.ie
Move the multi-lrc guc_id from the lower allocation partition (0 to
number of multi-lrc guc_ids) to upper allocation partition (number of
single-lrc to max guc_ids).
This will help when a native driver transitions to a PF after driver
load time. If the perma-pin guc_ids (kernel contexts) are in a
Hi Hsin-Yi, thanks for the patch! Please fix the follow comment, then
add my id.
Reviewed-by: Xin Ji
On Tue, Jan 11, 2022 at 07:27:00PM +0800, Hsin-Yi Wang wrote:
> Support reading edid through aux channel if panel is connected to aux
> bus. Extend anx7625_aux_dpcd_trans() to implement aux
Hi Hsin-Yi, thanks for the patch! It's OK for me!
Reviewed-by: Xin Ji
Thanks,
Xin
On Tue, Jan 11, 2022 at 07:27:01PM +0800, Hsin-Yi Wang wrote:
> List panel under aux-bus node if it's connected to anx7625's aux bus.
>
> Signed-off-by: Hsin-Yi Wang
> ---
>
Hi Hsin-Yi, thanks for the patch!
Reviewed-by: Xin Ji
Thanks,
Xin
On Tue, Jan 11, 2022 at 07:26:59PM +0800, Hsin-Yi Wang wrote:
> Use devm_kzalloc instead of kzalloc and drop kfree(). Let the memory
> handled by driver detach.
>
> Signed-off-by: Hsin-Yi Wang
> ---
>
Hi Dave, Daniel,
Fixes for 5.17.
The following changes since commit cb6846fbb83b574c85c2a80211b402a6347b60b1:
Merge tag 'amd-drm-next-5.17-2021-12-30' of
ssh://gitlab.freedesktop.org/agd5f/linux into drm-next (2021-12-31 10:59:17
+1000)
are available in the Git repository at:
https://bugzilla.kernel.org/show_bug.cgi?id=215445
--- Comment #8 from hock (talktome7...@gmail.com) ---
The bug is due to the use of uninitialized variable, which UBSAN detected.
See the patch https://patchwork.freedesktop.org/patch/468484 for the fix.
--
You may reply to this email to add a
Eliminate the follow smatch warnings:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3504 amdgpu_device_init()
warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1716
amdgpu_ras_error_status_query() warn: if statement not indented
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2724
Eliminate the following coccicheck warning:
./drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2725:16-17: Unneeded semicolon
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Thu, Jan 13, 2022 at 12:21:17AM +0100, Michal Wajdeczko wrote:
>
>
> On 11.01.2022 17:30, Matthew Brost wrote:
> > Move the multi-lrc guc_id from the lower allocation partition (0 to
> > number of multi-lrc guc_ids) to upper allocation partition (number of
> > single-lrc to max guc_ids).
> >
On 11.01.2022 17:30, Matthew Brost wrote:
> Move the multi-lrc guc_id from the lower allocation partition (0 to
> number of multi-lrc guc_ids) to upper allocation partition (number of
> single-lrc to max guc_ids).
>
> Signed-off-by: Matthew Brost
> ---
>
On 1/12/2022 2:20 PM, Andi Shyti wrote:
The GT has its own properties and in sysfs they should be grouped
in the 'gt/' directory.
Create a 'gt/' directory in sysfs which will contain gt0...gtN
directories related to each tile configured in the GPU. Move the
power management files inside those
Hi,
This is the second series that prepares i915 to host multitile
platforms. It introduces the for_each_gt() macro that loops over
the tiles to perform per gt actions.
This patch is a combination of two patches developed originally
by Abdiel, who introduced some refactoring during probe, and
The GT has its own properties and in sysfs they should be grouped
in the 'gt/' directory.
Create a 'gt/' directory in sysfs which will contain gt0...gtN
directories related to each tile configured in the GPU. Move the
power management files inside those directories.
The previous power management
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four gts are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A
On 1/12/2022 12:00 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-01-11 10:43:23)
Current DP drivers have regulators, clocks, irq and phy are grouped
together within a function and executed not in a symmetric manner.
This increase difficulty of code maintenance and limited code
(CC'ing this to dri-devel, since this is basically patch review)
Alright - so first off sorry about the broken debugging patch! I thought I had
tested that but I guess I hadn't tested it well enough, I'll get it fixed
asap, but feel free to try getting to it before I do.
As for this patch…
On Tue, Jan 11, 2022 at 1:31 PM Akhil P Oommen wrote:
>
> Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace
> identify the sku.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +
> 1 file changed, 5 insertions(+), 4
For example, memory-region in .dts as below,
reg = <0x0 0x5000 0x0 0x2000>
We can get below values,
struct resource r;
r.start = 0x5000;
r.end = 0x6fff;
So the size should be:
size = r.end - r.start + 1 = 0x2000
Signed-off-by: Xianting Tian
---
Hi Dmitry, Rob,
Thanks for the review.
>
> On Mon, Jan 10, 2022 at 05:06:03PM +0300, Dmitry Baryshkov wrote:
> > On Mon, 10 Jan 2022 at 15:56, Rajeev Nandan
> wrote:
> > >
> > > In most cases, the default values of DSI PHY tuning registers should
> > > be sufficient as they are fully optimized.
Hi, Robin,
On Fri, Dec 24, 2021 at 12:56:57PM +, Robin Murphy wrote:
> I'd note that panfrost has been working OK - to the extent that Mesa
> supports its older ISA - on the T624 (single core group) in Arm's Juno SoC
> for over a year now since commit 268af50f38b1.
>
> If you have to force
Hi Dmitry,
> >
> > + if (phy->cfg->ops.tuning_cfg_init)
> > + phy->cfg->ops.tuning_cfg_init(phy);
>
> Please rename to parse_dt_properties() or something like that.
Sure. I didn't understand your comment in v1 to use config_dt() hook. I think,
now I understood.
This function
On Wed, 12 Jan 2022 at 20:41, Kuogee Hsieh wrote:
>
>
> On 1/6/2022 6:01 PM, Dmitry Baryshkov wrote:
> > In commit 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display
> > enable and disable") the DP driver received a drm_bridge instance, which
> > is always attached to the encoder as a
https://bugzilla.kernel.org/show_bug.cgi?id=215445
--- Comment #7 from Bogdan (bogdan.pylypenko...@gmail.com) ---
UBSAN <- Undefined Behaviour sanity checker
> Compile-time instrumentation is used to detect various undefined behaviours
> at runtime.
> For more details, see:
Quoting Kuogee Hsieh (2022-01-11 10:43:23)
> Current DP drivers have regulators, clocks, irq and phy are grouped
> together within a function and executed not in a symmetric manner.
> This increase difficulty of code maintenance and limited code scalability.
> This patch divides the driver life
> > Now that we only list features of interest to kernel space, lots of GPUs
> > have the same feature bits. To cut down on the repetition in the file,
> > merge feature lists that are identical between similar GPUs.
> >
> > Note that this leaves some unmerged identical Bifrost feature lists, as
> (although it's a good thing kbase never did this cleanup - it's a useful
> source of public information ;) )
Haha, yes. Actually, kbase did do the clean up recently (Valhall era
kbase, I guess). To be fair, I still don't know what some of these were,
like "T7xx pairing rules"... Presumably
On Wed, Jan 12, 2022 at 06:37:03PM +, Matthew Wilcox wrote:
> On Tue, Jan 11, 2022 at 06:53:06PM -0400, Jason Gunthorpe wrote:
> > IOMMU is not common in those cases, it is slow.
> >
> > So you end up with 16 bytes per entry then another 24 bytes in the
> > entirely redundant scatter list.
Hi Sujaritha,
[...]
> > +static ssize_t act_freq_mhz_show(struct device *dev,
> > +struct device_attribute *attr, char *buff)
> Alignment with the initial (
OK
[...]
> > +static INTEL_GT_RPS_SYSFS_ATTR(RP1_freq_mhz, 0444, rps_rp_mhz_show, NULL);
> > +static
Hi Dale,
thanks for looking into this patch,
> > + /*
> > +* i915->gt[0] == >gt0
> > +*/
> > +#define I915_MAX_GT 4
> > + struct intel_gt *gt[I915_MAX_GT];
> > +
>
>
> It would be nice if I915_MAX_GT was defined in a more basic header file so
> that the definition of I915_MAX_GT
On Tue, Jan 11, 2022 at 06:53:06PM -0400, Jason Gunthorpe wrote:
> IOMMU is not common in those cases, it is slow.
>
> So you end up with 16 bytes per entry then another 24 bytes in the
> entirely redundant scatter list. That is now 40 bytes/page for typical
> HPC case, and I can't see that being
On 12/30/21 17:26, Pavel Skripkin wrote:
Syzbot has reported GPF in sg_alloc_append_table_from_pages(). The
problem was in ubuf->pages == ZERO_PTR.
ubuf->pagecount is calculated from arguments passed from user-space. If
user creates udmabuf with list.size == 0 then ubuf->pagecount will be
also
Hi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on next-20220112]
[cannot apply to v5.16]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base
On Wed, Dec 22, 2021 at 07:58:29AM +, Miaoqian Lin wrote:
> Since i915_gem_create_context() function return error pointers,
> the kernel_context() function does not return null, It returns error
> pointers too. Using IS_ERR() to check the return value to fix this.
>
Just a nit, err is
This driver supports the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.
Signed-off-by: Biju Das
---
drivers/gpu/drm/rcar-du/Kconfig | 7 +
drivers/gpu/drm/rcar-du/Makefile | 1 +
drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c | 676
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das
---
.../bindings/display/bridge/renesas,dsi.yaml | 143 ++
1 file changed, 143 insertions(+)
create mode 100644
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).
It has DPI/DSI interfaces and supports a maximum resolution of 1080p
along with 2 rpf's to support blending of two picture layers and
raster operations (ROPs).
A feature
Extend the Renesas DU display bindings to support the r9a07g044l RZ/G2L.
Signed-off-by: Biju Das
---
.../bindings/display/renesas,du.yaml | 54 +++
1 file changed, 54 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml
RZ/G2L LCDC does not have DU group registers. This patch allows
accessing DU group registers for SoC's with group feature bit is
set.
Signed-off-by: Biju Das
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 34 -
drivers/gpu/drm/rcar-du/rcar_du_group.c | 10 +++-
2
R-Car has supports DU groups in DU HW, where as it is not supported
in RZ/G2L.
Add RCAR_DU_FEATURE_GROUP feature bit to support RZ/G2L.
Signed-off-by: Biju Das
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +
drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 +
2 files changed, 18
RZ/G2L LCDC does not have DU plane registers. This patch
supports DU planes only for the SoC's with plane feature
bit is set.
Signed-off-by: Biju Das
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 +++
drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 3 ++-
2 files changed, 5 insertions(+), 1
DU plane registers are available on R-Car, but it is not present
on RZ/G2L. Add RCAR_DU_FEATURE_PLANE feature bit to support
later SoC.
Signed-off-by: Biju Das
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 51 ++-
drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 +
2 files
There are some differences related to max frame size supported by different
R-Car/RZ-G family of SoC's
Max frame size supported by R-Car Gen1 & R-Car Gen2 is 4095x2047
Max frame size supported by R-Car Gen3 is 8190x8190
Max frame size supported by RZ/G2L is 1920x1080
Add max_width and max_height
Number of RPF's VSP is different on R-Car and RZ/G2L
R-Car Gen3 -> 5 RPF's
R-Car Gen2 -> 4 RPF's
RZ/G2L -> 2 RPF's
Add num_rpf to struct rcar_du_device_info to support later
SoC without any code changes.
Signed-off-by: Biju Das
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17
Increase buff size for compatible variable to avoid stack corruption
with RZ/G2L SoC's(renesas,du-r9a07g044l) which requires a buff size
more than the current allocated size.
Signed-off-by: Biju Das
---
drivers/gpu/drm/rcar-du/rcar_du_of.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
RZ/G2L LCD controller composed of Frame compression Processor(FCPVD),
Video signal processor (VSPD) and Display unit(DU). The output of
LCDC is connected to Display parallel interface and MIPI link video
interface.
This patch series aims to add basic display support on RZ/G2L SMARC
EVK platform.
On 1/6/2022 6:01 PM, Dmitry Baryshkov wrote:
In commit 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display
enable and disable") the DP driver received a drm_bridge instance, which
is always attached to the encoder as a root bridge. However it conflicts
with the panel_bridge support
On Wed, Jan 12, 2022 at 06:09:06PM +0100, Piotr Piórkowski wrote:
> Tvrtko Ursulin wrote on śro [2022-sty-12
> 08:54:19 +]:
> >
> > On 11/01/2022 16:30, Matthew Brost wrote:
> > > Move the multi-lrc guc_id from the lower allocation partition (0 to
> > > number of multi-lrc guc_ids) to upper
On 1/11/2022 4:15 AM, Andi Shyti wrote:
The GT has its own properties and in sysfs they should be grouped
in the 'gt/' directory.
Create a 'gt/' directory in sysfs which will contain gt0...gtN
directories related to each tile configured in the GPU. Move the
power management files inside those
On Wed, 12 Jan 2022 at 19:09, Rajeev Nandan wrote:
>
> Hi Dmitry,
>
> > >
> > > + if (phy->cfg->ops.tuning_cfg_init)
> > > + phy->cfg->ops.tuning_cfg_init(phy);
> >
> > Please rename to parse_dt_properties() or something like that.
> Sure. I didn't understand your comment in
Tvrtko Ursulin wrote on śro [2022-sty-12
08:54:19 +]:
>
> On 11/01/2022 16:30, Matthew Brost wrote:
> > Move the multi-lrc guc_id from the lower allocation partition (0 to
> > number of multi-lrc guc_ids) to upper allocation partition (number of
> > single-lrc to max guc_ids).
>
> Just a
On 10/01/2022 17:42, Alyssa Rosenzweig wrote:
>> Whether it's worth the effort depends on whether anyone really cares
>> about getting the full performance out of this particular GPU.
>>
>> At this stage I think the main UABI change would be to add the opposite
>> flag to kbase, (e.g.
On 09/01/2022 17:09, Alyssa Rosenzweig wrote:
> Now that we only list features of interest to kernel space, lots of GPUs
> have the same feature bits. To cut down on the repetition in the file,
> merge feature lists that are identical between similar GPUs.
>
> Note that this leaves some unmerged
On 09/01/2022 17:09, Alyssa Rosenzweig wrote:
> Early versions of the legacy kernel driver included comprehensive
> feature lists for every GPU, even though most of the enumerated features
> only matter to userspace. For example, HW_FEATURE_INTERPIPE_REG_ALIASING
> was a feature bit indicating
Am 2022-01-12 um 6:16 a.m. schrieb David Hildenbrand:
> On 10.01.22 23:31, Alex Sierra wrote:
>> This patch series introduces MEMORY_DEVICE_COHERENT, a type of memory
>> owned by a device that can be mapped into CPU page tables like
>> MEMORY_DEVICE_GENERIC and can also be migrated like
>>
On 06/01/2022 03:03, Jiasheng Jiang wrote:
> Because of the possible failure of the dma_supported(), the
> dma_set_mask_and_coherent() may return error num.
> Therefore, it should be better to check it and return the error if
> fails.
>
> Fixes: d9b631f0a0c4 ("drm/panfrost: Set DMA masks
On 2022-01-11 15:51, Linus Torvalds wrote:
> On Tue, Jan 11, 2022 at 7:38 AM Harry Wentland wrote:
>>
>> Attached is a v2 of the buggy patch that should get this right.
>> If you have a chance to try it out let us know
>
> I can confirm that I do not see the horribly flickering behavior with
https://bugzilla.kernel.org/show_bug.cgi?id=210263
--- Comment #8 from ninel...@protonmail.com ---
(In reply to Fabian from comment #5)
> As of Kernel 5.15, I don't need fbcon=nodefer anymore. By default the
> backlight works and is set on start. I still get from time to time an
> boot-error by
Hi
Am 04.01.22 um 09:50 schrieb KuoHsiang Chou:
V1:
1. The MCU FW controling ASPEED DP is loaded by BMC boot loader.
2. Driver starts after CR[3:1] == 111b that indicates Tx is ASTDP,
and CRD1[5] has been asserted by BMVC boot loader.
3. EDID is prioritized by DP monitor.
4. DP's EDID has
DP Spec 1.4a 3.3 requires dp detect the hpd with debounce.
Upstream implementations should implement HPD signal de-bouncing on
an external connection. A period of 100ms should be used for
detecting an HPD connect event (i.e., the event, “HPD high,” is
confirmed only after HPD has been
ssed in kbytes/sec.
The state machine will be ICC provider then, although you'll need to
model that machine as a separate device somehow. For example, on Tegra
we needed to specify clocks as separate devices to model GENPD [2][3].
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=b1bc04a2ac5
[3]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/tegra30.dtsi?h=next-20220112#n394
Hi Dmitry,
On Wed, Jan 12, 2022 at 04:28:41PM +0300, Dmitry Osipenko wrote:
> 14.09.2021 12:35, Maxime Ripard пишет:
> > Hi,
> >
> > This is a follow-up of the discussion here:
> > https://lore.kernel.org/linux-clk/20210319150355.xzw7ikwdaga2dwhv@gilmour/
> >
> > This implements a mechanism to
14.09.2021 12:35, Maxime Ripard пишет:
> Hi,
>
> This is a follow-up of the discussion here:
> https://lore.kernel.org/linux-clk/20210319150355.xzw7ikwdaga2dwhv@gilmour/
>
> This implements a mechanism to raise and lower clock rates based on consumer
> workloads, with an example of such an
On Tue, Jan 11, 2022 at 04:55:35PM +0100, Maxime Ripard wrote:
> Hi Ville,
>
> Thanks for your review
>
> On Wed, Dec 15, 2021 at 03:48:39PM +0200, Ville Syrjälä wrote:
> > On Wed, Dec 15, 2021 at 01:43:53PM +0100, Maxime Ripard wrote:
> > > The current code, when parsing the EDID Deep Color
On Tue, Jan 11, 2022 at 10:34:34AM +0200, Jani Nikula wrote:
> On Mon, 10 Jan 2022, Ville Syrjälä wrote:
> > On Fri, Dec 31, 2021 at 03:23:31PM +0200, Jani Nikula wrote:
> >> On Wed, 12 Jul 2017, ville.syrj...@linux.intel.com wrote:
> >> > From: Ville Syrjälä
> >> >
> >> > Make the atomic
Hi Stephen,
Thanks for your answer
On Tue, Jan 11, 2022 at 07:37:15PM -0800, Stephen Boyd wrote:
> Sorry for being super delayed on response here. I'm buried in other
> work. +Jerome for exclusive clk API.
>
> Quoting Maxime Ripard (2021-09-14 02:35:13)
> > It's not unusual to find clocks being
Hello Kris,
On 1/12/22 03:19, Kris Karas (Bug reporting) wrote:
> Hi Javier, Geert, et al,
>
> Javier Martinez Canillas wrote:
>> Changes in v2:
>> - Make the change only for x86 (Geert Uytterhoeven)
>> - Only check the suppported video mode for x86 (Geert Uytterhoeven).
>
> I just updated Bug
On 10.01.22 23:31, Alex Sierra wrote:
> This patch series introduces MEMORY_DEVICE_COHERENT, a type of memory
> owned by a device that can be mapped into CPU page tables like
> MEMORY_DEVICE_GENERIC and can also be migrated like
> MEMORY_DEVICE_PRIVATE.
>
> Christoph, the suggestion to
I have been looking at this in relation to the migration code and noticed we
have the following in try_to_migrate():
if (is_zone_device_page(page) && !is_device_private_page(page))
return;
Which if I'm understanding correctly means that migration of device coherent
pages
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