Remove redundant assignment code for ttm->caching as it's overwritten
just a few lines later.
v2:
- Update the commit message.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/ttm/ttm_tt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
Hi Andi,
On Wed, May 31, 2023 at 6:21 AM Andi Shyti wrote:
>
> Hi Min,
>
> On Fri, May 26, 2023 at 09:01:31PM +0800, Min Li wrote:
> > If it is async, runqueue_node is freed in g2d_runqueue_worker on another
> > worker thread. So in extreme cases, if g2d_runqueue_worker runs first, and
> > then
Use struct_size() instead of hand writing it.
This is less verbose and more informative.
Signed-off-by: Su Hui
---
drivers/gpu/drm/nouveau/nvif/object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nvif/object.c
From: Bjorn Andersson
Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
Tested-by: Steev Klimaszewski
Reviewed-by: Konrad Dybcio
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v2:
- None
Changes since v1:
- Moved a690 to
From: Bjorn Andersson
Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.
Tested-by: Steev Klimaszewski
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v2:
- Added missing opp level (both gpu and gmu)
- Corrected opp-level for highest
From: Bjorn Andersson
Add memory reservation for the zap-shader and enable the Adreno SMMU,
GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
Lenovo ThinkPad X13s.
Tested-by: Steev Klimaszewski
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes
This series introduces support for A690 in the DRM/MSM driver and
enables it for the two SC8280XP laptops.
Bjorn Andersson (3):
drm/msm/adreno: Add Adreno A690 support
arm64: dts: qcom: sc8280xp: Add GPU related nodes
arm64: dts: qcom: sc8280xp: Enable GPU related nodes
On 5/30/2023 7:53 PM, Dmitry Baryshkov wrote:
On Wed, 31 May 2023 at 03:54, Abhinav Kumar wrote:
With [1] dpu core revision was dropped in favor of using the
compatible string from the device tree to select the dpu catalog
being used in the device.
This approach works well however also
On Wed, 31 May 2023 at 03:54, Abhinav Kumar wrote:
>
> With [1] dpu core revision was dropped in favor of using the
> compatible string from the device tree to select the dpu catalog
> being used in the device.
>
> This approach works well however also necessitates adding catalog
> entries for
Hi,
On Tue, May 30, 2023 at 12:42 AM Uwe Kleine-König
wrote:
>
> The .remove() callback for a platform driver returns an int which makes
> many driver authors wrongly assume it's possible to do error handling by
> returning an error code. However the value returned is (mostly) ignored
> and
On 5/30/2023 7:16 PM, Bjorn Andersson wrote:
On Tue, May 30, 2023 at 05:53:55PM -0700, Abhinav Kumar wrote:
With [1] dpu core revision was dropped in favor of using the
compatible string from the device tree to select the dpu catalog
being used in the device.
This approach works well
Hi,
On Fri, May 26, 2023 at 7:43 AM Doug Anderson wrote:
>
> Hi,
>
> On Fri, May 26, 2023 at 2:08 AM Uwe Kleine-König
> wrote:
> >
> > After commit b8a1a4cd5a98 ("i2c: Provide a temporary .probe_new()
> > call-back type"), all drivers being converted to .probe_new() and then
> > 03c835f498b5
The code after the return will not be executed, so remove them.
Eliminate the following warning:
drivers/gpu/drm/i915/display/intel_color.c:1808 intel_color_prepare_commit()
warn: ignoring unreachable code.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5342
On Tue, May 30, 2023 at 05:53:55PM -0700, Abhinav Kumar wrote:
> With [1] dpu core revision was dropped in favor of using the
> compatible string from the device tree to select the dpu catalog
> being used in the device.
>
> This approach works well however also necessitates adding catalog
>
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.c:1036 kgd2kfd_interrupt()
warn: inconsistent indenting
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
From: Fabio Estevam
Use port-base reference for port@0 and port@1.
This fixes the following schema warning:
imx8mm-evk.dtb: dsi@32e1: ports:port@1:endpoint: Unevaluated properties are
not allowed ('data-lanes' was unexpected)
>From schema:
On 5/30/2023 4:59 PM, Christian König wrote:
> Am 29.05.23 um 11:28 schrieb Ma Jun:
>> Remove redundant assignment code for ttm->caching
>
> The explanation is missing why this is redundant, e.g. something like
> "this is overwritten just a few lines later"..
>
Thanks for review. Will
With [1] dpu core revision was dropped in favor of using the
compatible string from the device tree to select the dpu catalog
being used in the device.
This approach works well however also necessitates adding catalog
entries for small register level details as dpu capabilities and/or
features
On Fri, 2023-05-26 at 17:52 -0700, Ceraolo Spurio, Daniele wrote:
> The full authentication via the GSC requires an heci packet submission
> to the GSC FW via the GSC CS. The GSC has new PXP command for this
> (literally called NEW_HUC_AUTH).
> The intel_huc_auth fuction is also updated to handle
On 5/30/2023 5:20 PM, John Harrison wrote:
On 5/30/2023 17:11, Ceraolo Spurio, Daniele wrote:
On 5/30/2023 4:51 PM, John Harrison wrote:
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the
On 5/30/2023 17:14, Ceraolo Spurio, Daniele wrote:
On 5/30/2023 5:01 PM, John Harrison wrote:
On 5/30/2023 08:29, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
On 5/30/2023 17:11, Ceraolo Spurio, Daniele wrote:
On 5/30/2023 4:51 PM, John Harrison wrote:
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the
On 5/30/2023 5:01 PM, John Harrison wrote:
On 5/30/2023 08:29, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with
On 5/30/2023 4:51 PM, John Harrison wrote:
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that
On 5/30/2023 17:06, Ceraolo Spurio, Daniele wrote:
On 5/30/2023 4:30 PM, John Harrison wrote:
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication contain the
legacy-style binary, which we can use for loading the HuC via DMA. To
find out
On 5/30/2023 4:30 PM, John Harrison wrote:
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication contain the
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse
In preparation to adding support for the hdmi_pwr supply, rename dp_pwr
structure field to the generic connector_pwr.
Reviewed-by: Laurent Pinchart
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/display-connector.c | 18 +-
1 file changed, 9 insertions(+), 9
On some devices the +5V Power pin of the HDMI connector and/or the ESD
protection logic is powered on by a separate regulator. Instead of
declaring this regulator as always-on, make hdmi-connector support the
additional hdmi-pwr supply.
Signed-off-by: Dmitry Baryshkov
---
Follow the dp-connector example and add hdmi-pwr supply to drive the 5V
pin of the HDMI connector (together with some simple glue logic possibly
attached to the connector).
Reviewed-by: Laurent Pinchart
Acked-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
On some devices the 5V pin of the HDMI connector and/or the ESD
protection logic is powered on by a separate regulator. The dp-connector
for such usecases provides dp-pwr supply support. Follow this example
and make hdmi-connector support the hdmi-pwr supply.
Changes since v2:
- Changed to use
On 5/30/2023 08:29, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with meu
meu?
binaries being considered fully
On 5/23/2023 12:30 PM, Abhinav Kumar wrote:
On 5/23/2023 12:23 PM, Dmitry Baryshkov wrote:
On Tue, 23 May 2023 at 22:14, Abhinav Kumar
wrote:
On 5/23/2023 7:36 AM, Dmitry Baryshkov wrote:
On 23/05/2023 10:31, Neil Armstrong wrote:
On 23/05/2023 09:20, Dmitry Baryshkov wrote:
On
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication contain the
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the
manifest of the GSC-enabled HuC binary.
On 30/05/2023 21:13, Marijn Suijten wrote:
On 2023-05-30 10:54:17, Abhinav Kumar wrote:
On 30/05/2023 00:07, Marijn Suijten wrote:
On 2023-05-22 15:58:56, Dmitry Baryshkov wrote:
On Mon, 22 May 2023 at 12:04, Neil Armstrong
wrote:
On 22/05/2023 03:16, Dmitry Baryshkov wrote:
On 22/05/2023
On 30/05/2023 23:09, Jessica Zhang wrote:
On 5/18/2023 3:17 PM, Jessica Zhang wrote:
On 5/17/2023 5:19 PM, Dmitry Baryshkov wrote:
On 16/05/2023 23:20, Jessica Zhang wrote:
Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
comes with the Qualcomm HDK8350 display
On Sun, May 28, 2023 at 02:26:37PM -0600, Gustavo A. R. Silva wrote:
> Zero-length and one-element arrays are deprecated, and we are moving
> towards adopting C99 flexible-array members, instead.
>
> Use the DECLARE_FLEX_ARRAY() helper macro to transform zero-length
> arrays in a union into
On 30/05/2023 19:31, Kuogee Hsieh wrote:
Since msm_dsi_bridge_get_dsc_config() was added to retrieve DSI DSC
info through DRM bridge, msm_dsi_get_dsc_config() become redundant
and should be removed.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
On Mon, 22 May 2023 15:53:50 +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remove
On 30/05/2023 19:31, Kuogee Hsieh wrote:
At current implementation, DSI DSC struct is populated at display setup
during system bootup. This mechanism works fine with embedded display.
But will run into problem with plugin/unplug oriented external display,
such as DP, due to DSC struct will
On Mon, 22 May 2023 15:53:06 +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remove
On Mon, 22 May 2023 15:53:31 +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remove
On Mon, 22 May 2023 15:51:49 +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remove
On Mon, 22 May 2023 15:51:24 +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remove
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
Now that each FW has its own reserved area, we can keep them always
pinned and skip the pin/unpin dance on reset. This will make things
easier for the 2-step HuC authentication, which requires the FW to be
pinned in GGTT after the xfer is
Hi Min,
On Fri, May 26, 2023 at 09:01:31PM +0800, Min Li wrote:
> If it is async, runqueue_node is freed in g2d_runqueue_worker on another
> worker thread. So in extreme cases, if g2d_runqueue_worker runs first, and
> then executes the following if statement, there will be use-after-free.
>
>
On 5/26/2023 16:55, john.c.harri...@intel.com wrote:
From: Michal Wajdeczko
For easier debug of any unexpected error responses from GuC that
might be related to non-blocking fast requests, track action code (and
stack if under DEBUG_GUC config) for every H2G request.
Signed-off-by: Michal
On 5/26/2023 16:55, john.c.harri...@intel.com wrote:
From: Michal Wajdeczko
Instead of printing message fence twice, include HXG header of the
unexpected message and its len.
Signed-off-by: Michal Wajdeczko
Signed-off-by: John Harrison
Reviewed-by: John Harrison
---
On 5/26/2023 16:55, john.c.harri...@intel.com wrote:
From: Michal Wajdeczko
In addition to the already defined REQUEST HXG message format,
which is used when sender expects some confirmation or data,
HXG protocol includes definition of the FAST REQUEST message,
that may be used when sender
On Tue, May 30, 2023 at 9:28 PM Marek Vasut wrote:
>
> Add reset GPIO support. The reset GPIO is cleared after supply regulator
> was enabled, and set before supply regulator is disabled.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Andrzej Hajda
> Cc: Conor Dooley
> Cc: Daniel Vetter
> Cc:
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Similar to queue snapshot, return an array of device information using
an entry_size check and return.
Unlike queue snapshots, the debugger needs to pass to correct number of
devices that exist. If it fails to do so, the KFD will return the
number of
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Allow the debugger to set single memory and single ALU operations.
Some exceptions are imprecise (memory violations, address watch) in the
sense that a trap occurs only when the exception interrupt occurs and
not at the non-halting faulty
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Shader read, write and atomic memory operations can be alerted to the
debugger as an address watch exception.
Allow the debugger to pass in a watch point to a particular memory
address per device.
Note that there exists only 4 watch points per
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
In order to inspect waves from the saved context at any point during a
debug session, the debugger must be able to preempt queues to trigger
context save by suspending them.
On queue suspend, the KFD will copy the context save header information
so
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Allow the debugger to set wave behaviour on to either normally operate,
halt at launch, trap on every instruction, terminate immediately or
stall on allocation.
v2: fixup with new kfd_node struct reference for mes check
Signed-off-by: Jonathan Kim
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
This operation allows the debugger to override the enabled HW
exceptions on the device.
On debug devices that only support the debugging of a single process,
the HW exceptions are global and set through the SPI_GDBG_TRAP_MASK
register.
Because they
On Mon, May 29, 2023 at 11:45:04PM +0800, Sui Jingfeng wrote:
> The vga_is_firmware_default() function will work on non-x86 architectures
> as long as the arch has UEFI GOP support, which passes the firmware
> framebuffer base address and size.
>
> This patch makes the vga_is_firmware_default()
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
The debugger must be notified by any debugger subscribed exception
that comes from hardware interrupts.
If a debugger session exits, any exceptions it subscribed to may still
have interrupts in the interrupt ring buffer or KGD/KFD pipeline.
To
On Tue, 30 May 2023 at 20:37, Abhinav Kumar wrote:
>
>
>
> On 5/29/2023 2:36 PM, Marijn Suijten wrote:
> > On 2023-05-24 12:18:09, Abhinav Kumar wrote:
> >>
> >>
> >> On 5/24/2023 2:48 AM, Marijn Suijten wrote:
> >>> On 2023-05-23 13:01:13, Abhinav Kumar wrote:
>
>
> On 5/21/2023
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
The debugger can attach to a process prior to HSA enablement (i.e.
inferior is spawned by the debugger and attached to immediately before
target process has been enabled for HSA dispatches) or it
can attach to a running target that is already HSA
On 5/18/2023 3:17 PM, Jessica Zhang wrote:
On 5/17/2023 5:19 PM, Dmitry Baryshkov wrote:
On 16/05/2023 23:20, Jessica Zhang wrote:
Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
comes with the Qualcomm HDK8350 display expansion pack.
The panel enables display
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Exception events can be generated from interrupts or queue activitity.
The raise event function will save exception status of a queue, device
or process then notify the debugger of the status change by writing to
a debugger polled file descriptor
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
To enable HW debug mode per process, all devices must be debug enabled
successfully. If a failure occures, rewind the enablement of debug mode
on the enabled devices.
A power management scenario that needs to be considered is HW
debug mode setting
[Public]
> -Original Message-
> From: Kuehling, Felix
> Sent: Tuesday, May 30, 2023 3:56 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Huang, JinHuiEric
> Subject: Re: [PATCH 14/33] drm/amdgpu: prepare map process for multi-
> process
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Unlike single process debug devices, multi-process debug devices allow
debug mode setting per-VMID (non-device-global).
Because the HWS manages PASID-VMID mapping, the new MAP_PROCESS API allows
the KFD to forward the required SPI debug register
Hi Evan,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on kvalo-ath/ath-next wireless-next/main wireless/main]
[cannot apply to linus/master v6.4-rc4 next-20230530]
[If your patch is applied to the wrong git tree
Hi Nathan,
On Tue, May 30, 2023 at 11:37:56AM -0700, Nathan Chancellor wrote:
> When building ARCH=i386 allmodconfig, the following warning occurs:
>
> In file included from include/linux/device.h:15,
>from include/linux/node.h:18,
>from
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Older HW only supports debugging on a single process because the
SPI debug mode setting registers are device global.
The HWS has supplied a single pinned VMID (0xf) for MAP_PROCESS
for debug purposes. To pin the VMID, the KFD will remove the VMID
Hi Neil,
On Tue, May 30, 2023 at 5:57 PM Neil Armstrong
wrote:
[...]
> >> The mipi_dsi_pxclk_div is set as RO in order to use the same GP0
> >> for mipi_dsi_pxclk and vclk2_input.
> >
> > I don't think notifiers is the appropriate approach here.
> > Whenever there is clock change the motifiers
This panel is 8 bits per channel DPI panel, add the missing .bpc
specifier otherwise the kernel is complaining about it as follows:
"
panel-simple panel: Expected bpc in {6,8} but got: 0
"
Fixes: d69de69f2be1 ("drm/panel: simple: Add Powertip PH800480T013 panel")
Signed-off-by: Marek Vasut
---
On Tue, May 30, 2023 at 09:28:04PM +0200, Marek Vasut wrote:
> This chip has one reset GPIO input, document it. The reset GPIO
> is optional as it is sometimes not connected on some hardware.
>
> Signed-off-by: Marek Vasut
Acked-by: Conor Dooley
Cheers,
Conor.
signature.asc
Description: PGP
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
|diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c index
faf4772ed317..a0cfd57ea84a 100644 ---
a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c +++
Add reset GPIO support. The reset GPIO is cleared after supply regulator
was enabled, and set before supply regulator is disabled.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jernej Skrabec
Cc: Jonas Karlman
Cc: Krzysztof
This chip has one reset GPIO input, document it. The reset GPIO
is optional as it is sometimes not connected on some hardware.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jernej Skrabec
Cc: Jonas Karlman
Cc: Krzysztof Kozlowski
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Add missing debug trap registers references and initialize all debug
registers on boot by clearing the hardware exception overrides and the
wave allocation ID index.
The debugger requires that TTMPs 6 & 7 save the dispatch ID to map
waves onto
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Expose debug capabilities in the KFD topology node's HSA capabilities and
debug properties flags.
Ensure correct capabilities are exposed based on firmware support.
Flag definitions can be referenced in uapi/linux/kfd_sysfs.h.
v2: rebase topology
Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
Introduce the GPU debug operations interface.
For ROCm-GDB to extend the GNU Debugger's ability to inspect the AMD GPU
instruction set, provide the necessary interface to allow the debugger
to HW debug-mode set and query exceptions per HSA queue,
> Subject: [PATCH 2/2] drm/i915/gt: Fix parameter in
> gmch_ggtt_insert_{entries,page}()
>
> When building with clang's -Wincompatible-function-pointer-types-strict,
> the following warnings occur:
>
> drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c:102:23: error: incompatible
> function pointer
> Subject: [PATCH 1/2] drm/i915/gt: Fix second parameter type of pre-gen8
> pte_encode callbacks
>
> When booting a kernel compiled with CONFIG_CFI_CLANG (kCFI), there is a CFI
> failure in ggtt_probe_common() when trying to call hsw_pte_encode() via an
> indirect call:
>
> [5.030027] CFI
On Wed, May 31, 2023 at 12:06:42AM +0800, Sui Jingfeng wrote:
> This patch adds PCI driver support on top of what already have. Take the
> GC1000 in LS7A1000/LS2K1000 as the first instance of the PCI device driver.
> There is only one GPU core for the GC1000 in the LS7A1000 and LS2K1000.
>
s/usperspace/userspace/ (in subject)
On Wed, May 31, 2023 at 12:06:43AM +0800, Sui Jingfeng wrote:
> cached system RAM is coherent on loongson CPUs, and the GPU and DC allways
> snoop the CPU's cache. write-combine caching property is not suitiable for
> us.
s/allways/always/
Hi Nathan,
On Tue, May 30, 2023 at 11:24:39AM -0700, Nathan Chancellor wrote:
> When building with clang's -Wincompatible-function-pointer-types-strict,
> the following warnings occur:
>
> drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c:102:23: error: incompatible
> function pointer types assigning
Hi Nathan,
On Tue, May 30, 2023 at 11:24:38AM -0700, Nathan Chancellor wrote:
> When booting a kernel compiled with CONFIG_CFI_CLANG (kCFI), there is a
> CFI failure in ggtt_probe_common() when trying to call hsw_pte_encode()
> via an indirect call:
>
> [5.030027] CFI failure at
drm_warn(>drm, "caller with insufficient PXP reply size
%u (%zu)\n",
reply_size, msg_out_size_max);
reply_size = msg_out_size_max;
}
---
base-commit: 08264f85c5c05ecc38d409c84d48cfb00ccd3bc4
change-id: 20230530-i915-pxp-size_t-wformat-1d73ed1f8d23
Best regards,
--
Nathan Chancellor
When building with clang's -Wincompatible-function-pointer-types-strict,
the following warnings occur:
drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c:102:23: error: incompatible
function pointer types assigning to 'void (*)(struct i915_address_space *,
dma_addr_t, u64, unsigned int, u32)' (aka
When booting a kernel compiled with CONFIG_CFI_CLANG (kCFI), there is a
CFI failure in ggtt_probe_common() when trying to call hsw_pte_encode()
via an indirect call:
[5.030027] CFI failure at ggtt_probe_common+0xd1/0x130 [i915] (target:
hsw_pte_encode+0x0/0x30 [i915]; expected type:
Add the nodes that describe the mdss so that display can work on
MSM8226.
Signed-off-by: Luca Weiss
---
arch/arm/boot/dts/qcom-msm8226.dtsi | 127
1 file changed, 127 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi
change-id:
20230530-i915-gt-cache_level-wincompatible-function-pointer-types-strict-32a5c65249a5
Best regards,
--
Nathan Chancellor
Add the config for the v1.0.2 DSI found on MSM8226. We can reuse
existing bits from other revisions that are identical for v1.0.2.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h
Add the required config for the v1.1 MDP5 found on MSM8226.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
1 file changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
Add the compatible for the DSI found on MSM8226.
Acked-by: Conor Dooley
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
Add the compatible for the MDP5 found on MSM8226.
Acked-by: Conor Dooley
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is
based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel.
Worth noting that the msm-3.10 downstream kernel also will try other
sequences in case this one doesn't work, but during testing it has shown
that the _m
This series adds the required configs for MDP5 and DSI blocks that are
needed for MDSS on MSM8226. Finally we can add the new nodes into the
dts.
Tested on apq8026-lg-lenok and msm8926-htc-memul.
Signed-off-by: Luca Weiss
---
Changes in v2:
- In dsi-phy-28nm.yaml fix the order of the
The MSM8226 SoC uses a slightly different 28nm dsi phy. Add a new
compatible for it.
And while we're at it, in the dsi-phy-28nm.yaml move the 8960 compatible
to its correct place so its sorted alphabetically.
Acked-by: Conor Dooley
Signed-off-by: Luca Weiss
---
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 8c33787278ca8db73ad7d23f932c8c39b9f6e543 Add linux-next specific
files for 20230530
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202305070840.x0g3ofjl-...@intel.com
Error
On 2023-05-30 14:11:06, Dmitry Baryshkov wrote:
> On Tue, 30 May 2023 at 11:27, Marijn Suijten
> wrote:
> >
> > On 2023-05-30 01:39:10, Dmitry Baryshkov wrote:
> > > On 30/05/2023 01:37, Marijn Suijten wrote:
> > > > On 2023-05-30 01:18:40, Dmitry Baryshkov wrote:
> > > >
> > > >>> +ret
On 2023-05-30 10:54:17, Abhinav Kumar wrote:
> > On 30/05/2023 00:07, Marijn Suijten wrote:
> >> On 2023-05-22 15:58:56, Dmitry Baryshkov wrote:
> >>> On Mon, 22 May 2023 at 12:04, Neil Armstrong
> >>> wrote:
>
> On 22/05/2023 03:16, Dmitry Baryshkov wrote:
> > On 22/05/2023 00:23,
Am 17.05.23 um 23:01 schrieb Alex Deucher:
On Wed, May 17, 2023 at 11:02 AM Alex Deucher wrote:
+ dri-devel for scheduler
On Tue, May 9, 2023 at 6:23 AM ZhenGuo Yin wrote:
[Why]
drm_sched_entity_add_dependency_cb ignores the scheduled fence and return false.
If entity's dependency is a
On 5/29/2023 3:18 PM, Dmitry Baryshkov wrote:
On 30/05/2023 00:07, Marijn Suijten wrote:
On 2023-05-22 15:58:56, Dmitry Baryshkov wrote:
On Mon, 22 May 2023 at 12:04, Neil Armstrong
wrote:
On 22/05/2023 03:16, Dmitry Baryshkov wrote:
On 22/05/2023 00:23, Marijn Suijten wrote:
Sony
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