[PATCH v17 6/7] drm/rockchip: cdn-dp: retry to check sink count

-power on, and wait for a while until it is ready to DPCD communication. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v17: None drivers/gpu/drm/rockchip/cdn-dp-core.c | 91 +++--- drivers/gpu/drm/rockchip/cdn-dp-core.h | 1 + 2 files chang

[PATCH v17 7/7] drm/rockchip: cdn-dp: don't configure hardware in mode_set

With atomic modesetting the hardware will be powered off when the mode_set function is called. We should configure the hardware in the enable function. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v17: None drivers/gpu/drm/rockchip/cdn-dp-core.

[PATCH v17 3/7] drm/rockchip: cdn-dp: Do not run worker while suspended

..@chromium.org> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v17: None drivers/gpu/drm/rockchip/cdn-dp-core.c | 15 +-- drivers/gpu/drm/rockchip/cdn-dp-core.h | 1 + 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/

[PATCH v17 5/7] drm/rockchip: cdn-dp: Move mutex_init to probe

From: Jeffy Chen <jeffy.c...@rock-chips.com> We're trying to lock mutex when cdn-dp shutdown, so we need to make sure the mutex is inited in cdn-dp's probe. Signed-off-by: Jeffy Chen <jeffy.c...@rock-chips.com> Reviewed-by: Guenter Roeck <gro...@chromium.org> Reviewed-by: Chri

[PATCH v17 1/7] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong <z...@rock-chips.com> [seanpaul fixed up some races between the worker and m

[PATCH v17 0/7] drm/rockchip: Add CDN DP driver

/9442141/ https://patchwork.kernel.org/patch/9442151/ Changes in v17: - Correct the clock check condition - Correct the coding style - change LANE_REF_CYC to 0x8000 Chris Zhong (4): drm/rockchip: cdn-dp: add cdn DP support for rk3399 drm/rockchip: cdn-dp: do not use drm_helper_hpd_irq_event drm

[PATCH v17 4/7] drm/rockchip: cdn-dp: do not use drm_helper_hpd_irq_event

system crash. replace drm_helper_hpd_irq_event with drm_kms_helper_hotplug_event, only update cdn-dp status. Signed-off-by: Chris Zhong <z...@rock-chips.com> Tested-by: Guenter Roeck <gro...@chromium.org> Reviewed-by: Guenter Roeck <gro...@chromium.org> --- Changes in v17: None

[PATCH v17 2/7] drm/rockchip: cdn-dp: Load firmware if no monitor connected

y: Sean Paul <seanp...@chromium.org> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v17: None drivers/gpu/drm/rockchip/cdn-dp-core.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rock

[PATCH v5 2/6] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> Sign

[PATCH v5 3/6] drm/rockchip/dsi: dw-mipi: correct the coding style

correct the coding style, according the checkpatch scripts Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/dw-mip

[PATCH v5 6/6] drm/rockchip/dsi: add dw-mipi power domain support

Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16

[PATCH v5 4/6] drm/rockchip/dsi: remove mode_valid function

The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/d

[PATCH v5 1/6] dt-bindings: add rk3399 support for dw-mipi-rockchip

The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v5: None Changes in v4: None Changes in v3: None .../devicetree/bindings/disp

[PATCH v5 5/6] dt-bindings: add power domain node for dw-mipi-rockchip

Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v5: None Changes in v4: None Changes in v3: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/D

[PATCH v5 0/6] Rockchip dw-mipi-dsi driver

/patch/9340251 [25/26] https://patchwork.kernel.org/patch/9340127 [26/26] https://patchwork.kernel.org/patch/9340139 Changes in v5: - check the error of phy_cfg_clk in dw_mipi_dsi_bind Changes in v4: - remove the unrelated change Changes in v3: - base on John Keeping's patch series Chris Zhong

Re: [PATCH v3 3/5] drm/rockchip/dsi: remove mode_valid function

On 02/02/2017 02:12 AM, Sean Paul wrote: On Tue, Jan 24, 2017 at 10:27:27AM +0800, Chris Zhong wrote: Hi Sean On 01/24/2017 01:48 AM, Sean Paul wrote: On Fri, Jan 20, 2017 at 06:10:49PM +0800, Chris Zhong wrote: The MIPI DSI do not need check the validity of resolution, the max resolution

[PATCH v6 0/6] Rockchip dw-mipi-dsi driver

://patchwork.kernel.org/patch/9544109 Changes in v6: - no need check phy_cfg_clk before enable/disable Changes in v5: - check the error of phy_cfg_clk in dw_mipi_dsi_bind Changes in v4: - remove the unrelated change Changes in v3: - base on John Keeping's patch series Chris Zhong (6): dt-bindings: add rk3399

[PATCH v6 1/6] dt-bindings: add rk3399 support for dw-mipi-rockchip

The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None ..

[PATCH v6 4/6] drm/rockchip/dsi: remove mode_valid function

The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None drivers/g

[PATCH v6 5/6] dt-bindings: add power domain node for dw-mipi-rockchip

Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++ 1 file changed, 3 inserti

[PATCH v6 3/6] drm/rockchip/dsi: dw-mipi: correct the coding style

correct the coding style, according the checkpatch scripts Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/dw-mip

[PATCH v6 2/6] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> Sign

[PATCH v6 6/6] drm/rockchip/dsi: add dw-mipi power domain support

Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/dw-mip

Re: [PATCH v2 20/26] drm/rockchip: dw-mipi-dsi: use specific poll helper

Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: As the documentation for readx_poll_timeout says, we want to use the specialized macro for readl rather than using the generic version directly. Signed-off-by: John Keeping <j...@met

Re: [PATCH v2 19/26] drm/rockchip: dw-mipi-dsi: improve PLL configuration

Hi John On 01/22/2017 12:31 AM, John Keeping wrote: The multiplication ratio for the PLL is required to be even due to the use of a "by 2 pre-scaler". Currently we are likely to end up with an odd multiplier even though there is an equivalent set of parameters with an even multiplier. For

Re: [PATCH v2 24/26] drm/rockchip: dw-mipi-dsi: support non-burst modes

Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Signed-off-by: John Keeping <j...@metanate.com> --- Unchanged in v2 --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-)

Re: [PATCH v2 25/26] drm/rockchip: dw-mipi-dsi: add reset control

Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: In order to fully reset the state of the MIPI controller we must assert this reset. This is slightly more complicated than it could be in order to maintain compatibility with device trees t

Re: [PATCH v3 3/5] drm/rockchip/dsi: remove mode_valid function

Hi Sean On 01/24/2017 01:48 AM, Sean Paul wrote: On Fri, Jan 20, 2017 at 06:10:49PM +0800, Chris Zhong wrote: The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Does vop actually enforce this, though

Re: [PATCH v2 19/26] drm/rockchip: dw-mipi-dsi: improve PLL configuration

On 01/23/2017 08:49 PM, John Keeping wrote: Hi Chris, On Mon, 23 Jan 2017 09:38:54 +0800, Chris Zhong wrote: On 01/22/2017 12:31 AM, John Keeping wrote: The multiplication ratio for the PLL is required to be even due to the use of a "by 2 pre-scaler". Currently we are likely

[PATCH v4 4/6] drm/rockchip/dsi: remove mode_valid function

The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/dw-mipi-dsi.

[PATCH v4 6/6] drm/rockchip/dsi: add dw-mipi power domain support

Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16 1 file

[PATCH v4 5/6] dt-bindings: add power domain node for dw-mipi-rockchip

Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v4: None Changes in v3: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicet

[PATCH v4 1/6] dt-bindings: add rk3399 support for dw-mipi-rockchip

The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v4: None Changes in v3: None .../devicetree/bindings/disp

[PATCH v4 2/6] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> Sign

[PATCH v4 3/6] drm/rockchip/dsi: dw-mipi: correct the coding style

correct the coding style, according the checkpatch scripts Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 33 - 1 file changed, 16 insertions(+), 17 deletions(-) diff

[PATCH v4 0/6] Rockchip dw-mipi-dsi driver

/patch/9340251 [25/26] https://patchwork.kernel.org/patch/9340127 [26/26] https://patchwork.kernel.org/patch/9340139 Changes in v4: - remove the unrelated change Changes in v3: - base on John Keeping's patch series Chris Zhong (6): dt-bindings: add rk3399 support for dw-mipi-rockchip drm

Re: [PATCH v2 03/26] drm/rockchip: dw-mipi-dsi: pass mode in where needed

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: This shows that we only use the mode from the enable function and prepares us to remove the "mode" field and the mode_set hook in the next commit. Signed-off-by: John Keeping &l

Re: [PATCH v2 04/26] drm/rockchip: dw-mipi-dsi: remove mode_set hook

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: This is not needed since we can access the mode via the CRTC from the enable hook. Also remove the "mode" field that is no longer used. Signed-off-by: John Keeping <j...@me

Re: [PATCH v2 06/26] drm/rockchip: dw-mipi-dsi: fix generic packet status check

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: We want to check that both the GEN_CMD_EMPTY and GEN_PLD_W_EMPTY bits are set so we can't just check "val & mask" because that will be true if either bit is set. Acco

Re: [PATCH v2 08/26] drm/rockchip: dw-mipi-dsi: include bad value in error message

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: As an aid to debugging. Signed-off-by: John Keeping <j...@metanate.com> --- Unchanged in v2 --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++- 1 file changed, 2 insertions(+)

Re: [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure PHY timing

On 01/22/2017 12:31 AM, John Keeping wrote: These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive

Re: [PATCH v2 07/26] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_buf

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: As a side-effect of this, encode the endianness explicitly rather than casting a u16. Signed-off-by: John Keeping <j...@metanate.com> --- Unchanged in v2 --- drivers/gpu/drm/rock

Re: [PATCH v2 26/26] drm/rockchip: dw-mipi-dsi: support read commands

Hi John On 01/22/2017 12:31 AM, John Keeping wrote: I haven't found any method for getting the length of a response, so this just uses the requested rx_len Signed-off-by: John Keeping --- Unchanged in v2 --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 54

Re: [PATCH v2 09/26] drm/rockchip: dw-mipi-dsi: respect message flags

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Instead of always sending commands in LP mode, respect the MIPI_DSI_MSG_USE_LPM flag to decide how to send each message. Also request acks if MIPI_DSI_MSG_REQ_ACK is set. Signed-off-by

Re: [PATCH v2 01/26] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI

Hi John On 01/22/2017 12:31 AM, John Keeping wrote: With atomic modesetting the hardware will be powered off when the mode_set function is called. We should configure the hardware in the commit function (or even the enable function, but switching from commit to enable is left for a future

Re: [PATCH v2 10/26] drm/rockchip: dw-mipi-dsi: only request HS clock when required

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Requesting the HS clock from the PHY before we initialize it causes an invalid signal to be sent out since the input clock is not yet configured. The PHY databook suggests only ass

Re: [PATCH v2 11/26] drm/rockchip: dw-mipi-dsi: don't assume buffer is aligned

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: By dereferencing the MIPI command buffer as a u32* we rely on it being correctly aligned on ARM, but this may not be the case. Copy it into a stack variable that will be correctly a

Re: [PATCH v2 12/26] drm/rockchip: dw-mipi-dsi: prepare panel after phy init

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Some panels need to be configured with commands sent over the MIPI link, which they will do in the prepare hook. Call this after the PHY has been initialized so that we are able to send co

Re: [PATCH v2 13/26] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable

l be driven -* normally when the display is enabled again later. -*/ - msleep(120); - - dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE); This workaround is from[0], I also think it should be deleted. [0] http://www.spinics.net/lists/dri-devel/msg77192.html Revi

Re: [PATCH v2 14/26] drm/rockchip: dw-mipi-dsi: fix escape clock rate

Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Use the same calculation as the vendor kernel to derive the escape clock speed. Signed-off-by: John Keeping <j...@metanate.com> --- Unchanged in v2 --- drivers/gpu/drm/rockchip/dw-mi

Re: [PATCH v2 15/26] drm/rockchip: dw-mipi-dsi: ensure PHY is reset

Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Also don't power up the DSI host at this point since this is not necessary in order to configure the PHY and we do so later when selecting video or command mode. Signed-off-by: John Keep

Re: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured

Hi John This patch do the similar thing with https://patchwork.kernel.org/patch/9530405/ They are changing the phy configuration order, my suggestion is to merge them. On 01/22/2017 12:31 AM, John Keeping wrote: Signed-off-by: John Keeping --- Unchanged in v2 ---

Re: [PATCH v3 22/24] drm/rockchip: dw-mipi-dsi: support non-burst modes

Hi John On 02/01/2017 03:22 AM, Sean Paul wrote: On Sun, Jan 29, 2017 at 01:24:42PM +, John Keeping wrote: Reviewed-by: Sean Paul <seanp...@chromium.org> Signed-off-by: John Keeping <j...@metanate.com> Reviewed-by: Chris Zhong <z...@rock-chips.com> --- v3: - A

Re: [PATCH 1/4] Documentation: bindings: add uphy-dp-sel for Rockchip USB Type-C PHY

Hi Rob On 02/16/2017 10:20 AM, Rob Herring wrote: On Fri, Feb 10, 2017 at 03:44:11PM +0800, Chris Zhong wrote: rockchip,uphy-dp-sel is the register of type-c phy enable DP function. "dt-bindings: phy:" is the preferred subject prefix. OK, I will change the header next version. d

Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver

Hi Sean On 02/21/2017 11:39 PM, Sean Paul wrote: On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote: Hi all [Resend this v7 version series, since there are 5 mails have gone missing, last week] This version does not change the existing v6 patches, just to add the "bandwidt

Re: [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver

n Paul wrote: On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote: Hi all [Resend this v7 version series, since there are 5 mails have gone missing, last week] This version does not change the existing v6 patches, just to add the "bandwidth fix" patch back, since we reall

[RESEND PATCH v7 7/7] drm/rockchip/dsi: add dw-mipi power domain support

Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/dw-mip

[RESEND PATCH v7 4/7] drm/rockchip/dsi: remove mode_valid function

The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None drivers/g

[RESEND PATCH v7 2/7] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> Sign

[RESEND PATCH v7 1/7] dt-bindings: add rk3399 support for dw-mipi-rockchip

The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None ..

[RESEND PATCH v7 5/7] dt-bindings: add power domain node for dw-mipi-rockchip

Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++ 1 file changed, 3 inserti

[RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel

Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough for some panel, it will cause the screen display is not normal, so increases the badnwidth to 1 / 0.8. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v6: None Changes in v5: None Changes in v4: None C

[RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver

le/disable Changes in v5: - check the error of phy_cfg_clk in dw_mipi_dsi_bind Changes in v4: - remove the unrelated change Changes in v3: - base on John Keeping's patch series Chris Zhong (7): dt-bindings: add rk3399 support for dw-mipi-rockchip drm/rockchip/dsi: dw-mipi: support RK3399 mipi

[RESEND PATCH v7 3/7] drm/rockchip/dsi: dw-mipi: correct the coding style

correct the coding style, according the checkpatch scripts Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/dw-mip

Re: [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control

-by: John Keeping <j...@metanate.com> Reviewed-by: Chris Zhong <z...@rock-chips.com> --- v3: - Add Chris' Reviewed-by Unchanged in v2 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-m

Re: [PATCH v2 11/11] drm/rockchip/dsi: fix insufficient bandwidth of some panel

Hi John On 01/17/2017 06:54 PM, John Keeping wrote: On Tue, 17 Jan 2017 17:31:53 +0800, Chris Zhong wrote: On 01/16/2017 08:44 PM, John Keeping wrote: On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote: Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough for some

[PATCH v7 1/7] dt-bindings: add rk3399 support for dw-mipi-rockchip

The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None ..

[PATCH v7 0/7] Rockchip dw-mipi-dsi driver

nges in v4: - remove the unrelated change Changes in v3: - base on John Keeping's patch series Chris Zhong (7): dt-bindings: add rk3399 support for dw-mipi-rockchip drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi drm/rockchip/dsi: dw-mipi: correct the coding style drm/rockchip/dsi: remove

[PATCH v7 2/7] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> Sign

[PATCH 3/4] phy: rockchip-typec: support DP phy switch

-by: Chris Zhong <z...@rock-chips.com> --- drivers/phy/phy-rockchip-typec.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/phy/phy-rockchip-typec.c b/drivers/phy/phy-rockchip-typec.c index 7cfb0f8..1604aaa 100644 --- a/drivers/phy/phy-rockchip-typec.c +++ b/drivers/phy/phy-ro

[PATCH 4/4] drm/rockchip: cdn-dp: remove the DP phy switch

driver can distinguish between PHY 0 and PHY 1, and then write the correct register bit. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/cdn-dp-core.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/g

[PATCH 1/4] Documentation: bindings: add uphy-dp-sel for Rockchip USB Type-C PHY

rockchip,uphy-dp-sel is the register of type-c phy enable DP function. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-ro

[PATCH 2/4] arm64: dts: rockchip: add rockchip, uphy-dp-sel for Type-C phy

rockchip,uphy-dp-sel is the register of type-c phy enable DP function. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/ro

[PATCH 0/4] Move DP phy switch to PHY driver

driver can distinguish between PHY 0 and PHY 1, and then write the correct register bit. Chris Zhong (4): Documentation: bindings: add uphy-dp-sel for Rockchip USB Type-C PHY arm64: dts: rockchip: add rockchip,uphy-dp-sel for Type-C phy phy: rockchip-typec: support DP phy switch drm

Re: [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control

Hi John On 02/15/2017 08:39 PM, John Keeping wrote: On Wed, 15 Feb 2017 11:38:45 +0800, Chris Zhong wrote: On 01/29/2017 09:24 PM, John Keeping wrote: In order to fully reset the state of the MIPI controller we must assert this reset. This is slightly more complicated than it could

[PATCH v2 02/11] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> Sign

[PATCH v2 03/11] drm/rockchip/dsi: remove mode_valid function

The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39 -- 1 file chang

[PATCH v2 06/11] drm/rockchip/dsi: return probe defer if attach panel failed

From: Mark Yao <mark@rock-chips.com> Return -EINVAL would cause mipi dsi bad behavior, probe defer to ensure mipi find the correct mode, Signed-off-by: Mark Yao <mark@rock-chips.com> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/

[PATCH v2 04/11] dt-bindings: add power domain node for dw-mipi-rockchip

Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_

[PATCH v2 05/11] drm/rockchip/dsi: add dw-mipi power domain support

Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/ro

[PATCH v2 01/11] dt-bindings: add rk3399 support for dw-mipi-rockchip

The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff

[PATCH v2 09/11] drm/rockchip/dsi: decrease the value of Ths-prepare

From: xubilv <x...@rock-chips.com> Signed-off-by: xubilv <x...@rock-chips.com> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-ds

[PATCH v2 07/11] drm/rockchip/dsi: fix mipi display can't found at init time

<mark@rock-chips.com> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 57 +++--- 1 file changed, 39 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/d

[PATCH v2 10/11] drm/rockchip/dsi: fix phy clk lane stop state timeout

Before phy init, the detection of phy state should be controlled manually. After that, we can switch the detection to hardward, it is automatic. Hence move PHY_TXREQUESTCLKHS setting to the end of phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/d

[PATCH v2 08/11] drm/rockchip/dsi: fix the issue can not send commands

chips.com> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 26 +- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 4ec82

[PATCH v2 11/11] drm/rockchip/dsi: fix insufficient bandwidth of some panel

Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough for some panel, it will cause the screen display is not normal, so increases the badnwidth to 1 / 0.8. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file chan

[v14.2 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v14.2: - Modify some

[PATCH 0/2] Add DP dai-links to the rk3399-gru machine driver

/8887261/ https://patchwork.kernel.org/patch/8887251/ Chris Zhong (2): drm/rockchip: cdn-dp: support audio hot-plug ASoC: rockchip: Add DP dai-links to the rk3399-gru machine driver .../bindings/sound/rockchip,rk3399-gru-sound.txt | 13 +++--- drivers/gpu/drm/rockchip/cdn-dp-core.c

[PATCH 1/2] drm/rockchip: cdn-dp: support audio hot-plug

Issue hot-plug detection, EDID update, and ELD update notifications from DP drivers. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/cdn-dp-core.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c

[PATCH v15 3/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Signed-off-by: Sean Paul Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes

[PATCH v15 4/5] drm/rockchip: cdn-dp: support audio hot-plug

Issue hot-plug detection, EDID update, and ELD update notifications from DP drivers. Signed-off-by: Chris Zhong --- Changes in v15: None Changes in v14: None Changes in v13: None Changes in v12: None Changes in v11: None Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7

[PATCH v15.1 3/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Signed-off-by: Sean Paul Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes

[PATCH v15 0/5] Rockchip Type-C DisplayPort driver

() - correct the commit message Changes in v1: - add extcon node description - add #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to

[PATCH v15.1 3/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

Hi Mark OK, thanks. I will send the whole series next time, hope it will not bother anyone On 09/12/2016 05:13 PM, Mark Brown wrote: > On Fri, Sep 09, 2016 at 09:16:06PM -0700, Chris Zhong wrote: >> Add support for cdn DP controller which is embedded in the rk3399 >> SoCs. The

Re: [PATCH v2 11/11] drm/rockchip/dsi: fix insufficient bandwidth of some panel

Hi John On 01/16/2017 08:44 PM, John Keeping wrote: On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote: Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough for some panel, it will cause the screen display is not normal, so increases the badnwidth to 1 / 0.8. Signed-off

Re: [05/26] drm/rockchip: dw-mipi-dsi: fix command header writes

same as https://patchwork.kernel.org/patch/9518417/ Tested-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Chris Zhong <z...@rock-chips.com> On 09/20/2016 01:17 AM, John Keeping wrote: In a couple of places here we use "val" for the value that is about to be

Re: [01/26] drm/rockchip: dw-mipi-dsi: use mode from display state

On 09/20/2016 01:17 AM, John Keeping wrote: There is no need to keep a pointer to the mode around since we know it will be present in the connector state. Signed-off-by: John Keeping --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 31 --- 1 file

[PATCH v3 3/5] drm/rockchip/dsi: remove mode_valid function

The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v3: None drivers/gpu/drm/rockchip/dw-mipi-dsi.

[PATCH v3 5/5] drm/rockchip/dsi: add dw-mipi power domain support

Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v3: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-ds

[PATCH v3 4/5] dt-bindings: add power domain node for dw-mipi-rockchip

Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v3: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/disp

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