tead of drm_err. [Uma]
> - Cosmetic changes. [Uma]
> v3:
> - 's/port_data/hdcp_port_data' [Ram]
> - skip redundant link check. [Ram]
> v4:
> - use pipe instead of port to access HDCP2_STREAM_STATUS
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
>
t RepeaterAuthStreamManage msg and m' validation
> whenever required.
>
> v2:
> - Init the hdcp port data k for HDMI/DP SST stream.
> v3:
> - Cosmetic changes. [Uma]
> v4:
> - 's/port_auth/hdcp_port_auth'. [Ram]
> - Commit log improvement.
> v5:
> - Comment and comm
the stream encryptions status for 2.2 another one for
enabling the HDCP2.2 MST support.
Ram
> v2:
> - Add connector details in drm_err. [Ram]
> - 's/port_auth/hdcp_auth_status'. [Ram]
> - Added a debug print for stream enc.
> v3:
> - uniformity for connector detail in DMESG.
tead of drm_err. [Uma]
> - Cosmetic changes. [Uma]
> v3:
> - 's/port_data/hdcp_port_data' [Ram]
> - skip redundant link check. [Ram]
> v4:
> - use pipe instead of port to access HDCP2_STREAM_STATUS
How this missed the functional test till now?
Always true because port's stream status was refe
in DMESG. [Ram]
> - comments improvement. [Ram]
>
Patch LGTM.
Reviewed-by: Ramalingam C
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 38 +++
&g
On 2020-12-10 at 11:56:31 +0530, Anshuman Gupta wrote:
> Enable HDCP 1.4 over DP MST for Gen12.
>
> v2:
> - Enable HDCP for <= Gen12 platforms. [Ram]
>
> Cc: Ramalingam C
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/dr
ses to prevent any crash.
LGTM..
Reviewed-by: Ramalingam C
>
> Cc: Ramalingam C
> Cc: Juston Li
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git
disable HDCP on another MST
> stream on same DP MST topology.
>
> v2:
> Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
> v3:
> Commit log improvement. [Uma]
> Added a comment before scheduling prop_work. [Uma]
>
> Fixes: 33f9a623bfc6 (&
against disappearing
> connectors")
> Cc: Sean Paul
> Cc: Ramalingam C
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers
On 2020-11-05 at 18:48:02 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> > When crtc state need_modeset is true it is not necessary
> > it is going to be a real modeset, it can turns to be a
> > fastset instead of modeset.
> > Th
On 2020-11-05 at 18:51:57 +0530, Ramalingam C wrote:
> On 2020-11-05 at 18:48:02 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> > > When crtc state need_modeset is true it is not necessary
> > > it is going to be a
ream transcoder for stream encryption
> separately.
>
> This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
> on Gen12.
Reviewed-by: Ramalingam C
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/displa
tream status too,
> it requires to move the macro to a header.
> It will be used by both HDCP{1.x,2.x} stream status timeout.
Reviewed-by: Ramalingam C
>
> Related: 'commit 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
> status change")'
> Cc: Ramalingam C
hdcp_cmd_header size annotation nitpick. [Tomas]
>
> Cc: Tomas Winkler
> Cc: Ramalingam C
> Acked-by: Tomas Winkler
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshuman Gupta
> ---
> drivers/misc/mei/hdcp/mei_hdcp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 dele
On 2020-10-27 at 22:12:05 +0530, Anshuman Gupta wrote:
> This requires for HDCP 2.2 MST check link.
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
> driv
; v3:
> Cosmetic changes. [Uma]
>
> Cc: Ramalingam C
> Signed-off-by: Anshuman Gupta
> ---
> .../drm/i915/display/intel_display_types.h| 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++---
> 2 files changed, 92 insertions(+), 15 del
On 2020-10-27 at 22:12:06 +0530, Anshuman Gupta wrote:
> Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
> and HDCP2_AUTH_STREAM register in i915_reg header.
Reviewed-by: Ramalingam C
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshuman Gupta
> ---
&g
g print for stream encryption.
> - Disable the hdcp on port after disabling last stream
> encryption.
> v3:
> - Cosmetic change, removed the value less comment. [Uma]
>
> Cc: Ramalingam C
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst
On 2020-10-27 at 22:12:03 +0530, Anshuman Gupta wrote:
> Let's define Maximum MST content streams up to four
> generically which can be supported by modern display
> controllers.
>
> Cc: Sean Paul
> Cc: Ramalingam C
> Acked-by: Maarten Lankhorst
> Reviewed-by: U
name, error msg print and
> stream typo fixes. [Uma]
>
> Cc: Ramalingam C
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> .../drm/i915/display/intel_display_types.h
On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> Pass dig_port as an argument to intel_hdcp_init()
> and intel_hdcp2_init().
> This will be required for HDCP 2.2 stream encryption.
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshuman Gupta
>
On 2020-11-06 at 10:20:35 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 22:09:12 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> > > Pass dig_port as an argument to intel_hdcp_init()
> > > and intel_hdcp2_init().
> > >
On 2020-11-06 at 10:52:03 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 21:04:03 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> > > Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> > > in TRANS_DDI_FUNC_CTL
On 2020-11-06 at 12:05:14 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 22:04:15 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> > > Add support for multiple mst stream in hdcp port data
> > > which will be used by R
On 2020-10-27 at 22:12:01 +0530, Anshuman Gupta wrote:
> hdcp_port_data is specific to a port on which HDCP
> encryption is getting enabled, so encapsulate it to
> intel_digital_port.
> This will be required to enable HDCP 2.2 stream encryption.
>
> Cc: Ramalingam C
> Rev
on on this port.
>
> Similarly disable the stream encryption for each encrypted
> stream, once all encrypted stream encryption is disabled,
> disable the port HDCP encryption and deauthenticate the port.
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshum
On 2020-10-27 at 22:11:55 +0530, Anshuman Gupta wrote:
> Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
> It requires to call intel_hdcp_handle_cp_irq() in case
> of CP_IRQ is triggered by a sink in DP-MST topology.
>
> Cc: "Ville Syrjälä"
> Cc: Ramalingam C
(Thomas)
- s/TTM_PL_PRIV/I915_PL_LMEM0 (Thomas)
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 88 +
1 file changed, 75 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers
On 2021-06-15 at 13:36:00 +0200, Thomas Hellström wrote:
> To help avoid evicting already resident buffers from the batch we're
> processing, perform locking as a separate step.
>
Looks reasonable to me.
Reviewed-by: Ramalingam C
> Signed-off-by: Thomas Hellström
> ---
> ..
On 2021-07-05 at 14:53:07 +0100, Matthew Auld wrote:
> Convert all the drm_i915_gem_caching bits to proper kernel doc.
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Matthew Auld
LGTM.
Reviewed-by: Ramalingam C
> Cc: Thomas Hellström
> Cc: Maarten Lankhorst
> Cc:
On 2021-07-05 at 14:53:09 +0100, Matthew Auld wrote:
> Convert all the drm_i915_gem_set_domain bits to proper kernel doc.
LGTM.
Reviewed-by: Ramalingam C
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Maarten Lankhorst
> Cc:
he new rules for discrete.
>
> Suggested-by: Thomas Hellström
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Maarten Lankhorst
> Cc: Daniel Vetter
> Cc: Ramalingam C
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 34 ++
> drive
m_create_ext extension.
>
> v2: add some kernel doc for the discrete changes, and document the
> implicit rules
LGTM
Reviewed-by: Ramalingam C
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Maarten Lankhorst
> Cc: Tv
ing a whole new flag is likely overkill.
>
> v2: add some more kernel doc, also add the implicit rules with caching
LGTM
Reviewed-by: Ramalingam C
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Maarten Lankhorst
> Cc: Tvrtko U
> - if (block) {
> - pr_err("bad block, dump:\n");
> - igt_dump_block(mm, block);
> - }
> + pr_err("bad block, dump:\n");
> + igt_dump_block(mm, block);
LGTM.
Reviewed-by: Ramalingam C
>
> return err;
> }
> --
> 2.26.3
>
> @@ -224,9 +224,10 @@ static int igt_mock_reserve(void *arg)
> }
>
> out_close:
> - kfree(order);
> close_objects(mem, );
> intel_memory_region_put(mem);
> +out_free_order:
> + kfree(order);
LGTM.
Reviewed-by: Ramalingam C
> return err;
> }
>
> --
> 2.26.3
>
> that as well.
>
> Changes since v2:
> - Remove no longer used variables in _intel_hdcp2_enable()
LGTM.
Reviewed-by: Ramalingam C
>
> Signed-off-by: Juston Li
> ---
> .../drm/i915/display/intel_display_types.h| 2 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp
for a new
> CP_IRQ.
LGTM.
Reviewed-by: Ramalingam C
>
> Signed-off-by: Juston Li
> Acked-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/dr
in v2:
> - remove unnecessary moving of drm_i915_private from patch 1
Looks good to me
Reviewed-by: Ramalingam C
>
> Signed-off-by: Juston Li
> Acked-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 30 ++--
> include/drm/drm_dp_helpe
compression states.
Cc: Joonas Lahtinen
Cc: Matthew Auld
Signed-off-by: CQ Tang
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 4 insertions(+)
diff
of CCS buffer associated main BO is automatically calculated
by device itself. KMD/UMD can only access this buffer indirectly using
XY_CTRL_SURF_COPY_BLT cmd via the address of device memory buffer.
Cc: CQ Tang
Signed-off-by: Ayaz A Siddiqui
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
.
Cc: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 22 +++--
drivers/gpu/drm/i915
-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 16 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 6
drivers/gpu/drm/i915/i915_gem_evict.c | 17 ++
drivers/gpu/drm/i915
Details of the new features getting added as part of DG2 enabling and their
implicit impact on the uAPI.
Signed-off-by: Ramalingam C
cc: Daniel Vetter
cc: Matthew Auld
---
Documentation/gpu/rfc/i915_dg2.rst | 47 ++
Documentation/gpu/rfc/index.rst| 3 ++
2
From: Matthew Auld
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/sel
supported by the HW.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 61 ++
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 106 +-
drivers/gpu
From: Bommu Krishnaiah
Replace the hard coded 4K alignment value with vm->min_alignment.
Cc: Wilson Chris P
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Ramalingam C
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 ---
drivers/gpu/drm/i915/gt/intel_gt
From: Stuart Summers
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915
age size for scratch
drm/i915/gtt/xehpsdv: move scratch page to system memory
drm/i915/xehpsdv: support 64K GTT pages
drm/i915/selftests: account for min_alignment in GTT selftests
drm/i915/xehpsdv: implement memory coloring
drm/i915/uapi: document behaviour for DG2 64K support
Ramalingam C
the HW expects the correct physical alignment and
size for every PTE, if we mark the page-table as 64K GTT mode.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt
rk for all configurations.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 ++
drivers/gpu/drm/i915/gt/intel_gtt.c
From: Matthew Auld
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm
From: Matthew Auld
For local-memory objects we need to align the GTT addresses to 64K, both
for the ppgtt and ggtt.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_vma.c | 9
rk for all configurations.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 ++
drivers/gpu/drm/i915/gt/intel_gtt.c
supported by the HW.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 61 ++
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 106 +-
drivers/gpu
From: Bommu Krishnaiah
Replace the hard coded 4K alignment value with vm->min_alignment.
Cc: Wilson Chris P
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Ramalingam C
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 ---
drivers/gpu/drm/i915/gt/intel_gt
From: Matthew Auld
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/sel
-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 16 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 6
drivers/gpu/drm/i915/i915_gem_evict.c | 17 ++
drivers/gpu/drm/i915
From: Matthew Auld
For local-memory objects we need to align the GTT addresses to 64K, both
for the ppgtt and ggtt.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_vma.c | 9
the HW expects the correct physical alignment and
size for every PTE, if we mark the page-table as 64K GTT mode.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt
: implement memory coloring
drm/i915/uapi: document behaviour for DG2 64K support
Ramalingam C (2):
drm/i915/Flat-CCS: Document on Flat-CCS memory compression
Doc/gpu/rfc/i915: i915 DG2 uAPI
Stanislav Lisovskiy (1):
drm/i915/dg2: Tile 4 plane format support
Stuart Summers (1):
drm/i915: Add
From: Matthew Auld
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm
From: Stuart Summers
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915
-by: Matthew Auld
Signed-off-by: Ramalingam C
cc: Simon Ser
cc: Pekka Paalanen
---
include/uapi/drm/i915_drm.h | 67 ++---
1 file changed, 62 insertions(+), 5 deletions(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 914ebd9290e5
From: Stanislav Lisovskiy
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Fixed wrong case condition(Jani Nikula)
- Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
v3: -
-off-by: Matt Roper
Signed-off-by: Mika Kahola (v2)
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
cc: Simon Ser
Cc: Pekka Paalanen
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++
.../drm/i915/display/intel_display_types.h| 10 +++-
drivers/gpu/drm/i915/display
.
Cc: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 22 +++--
drivers/gpu/drm/i915
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 14 +++
drivers/gpu/drm/i915/gt/intel_migrate.c | 120 ++-
2 files changed, 131 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt
Details of the new features getting added as part of DG2 enabling and their
implicit impact on the uAPI.
v2: improvised the Flat-CCS documentation [Danvet & CQ]
Signed-off-by: Ramalingam C
cc: Daniel Vetter
cc: Matthew Auld
cc: Simon Ser
cc: Pekka Paalanen
---
Documentation/gpu
Documents the Flat-CCS feature and kernel handling required along with
modifiers used.
Signed-off-by: Ramalingam C
cc: Simon Ser
cc: Pekka Paalanen
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 47 +
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915
compression states.
Cc: Joonas Lahtinen
Cc: Matthew Auld
Signed-off-by: CQ Tang
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 4 insertions(+)
diff
thew Auld
> Cc: Thomas Hellström
> Cc: Ramalingam C
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 ++--
> 1 file changed, 48 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i9
On 2021-12-03 at 12:24:22 +, Matthew Auld wrote:
> Ensure we add the engine base only after we calculate the qword offset
> into the PTE window.
So we didn't hit this issue because we were always using the
engine->instance 0!?
Looks good to me
Reviewed-by: Ramalingam C
>
On 2021-12-03 at 17:31:11 +, Matthew Auld wrote:
> On 03/12/2021 16:59, Ramalingam C wrote:
> > On 2021-12-03 at 12:24:20 +, Matthew Auld wrote:
> > > If this is LMEM then we get a 32 entry PT, with each PTE pointing to
> > > some 64K block of memory, otherw
On 2021-12-03 at 12:24:19 +, Matthew Auld wrote:
> The scratch page might not be allocated in LMEM(like on DG2), so instead
> of using that as the deciding factor for where the paging structures
> live, let's just query the pt before mapping it.
>
Looks good to me.
Reviewed-by:
w Auld
> Cc: Thomas Hellström
> Cc: Ramalingam C
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c| 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c
On 2021-12-03 at 12:24:23 +, Matthew Auld wrote:
> No need to insert PTEs for the PTE window itself, also foreach expects a
> length not an end offset, which could be gigantic here with a second
> engine.
>
Looks good to me
Reviewed-by: Ramalingam C
> Signed-off-by: Mat
On 2021-12-03 at 12:24:24 +, Matthew Auld wrote:
> Ensure we account for any object rounding due to min_page_size
> restrictions.
>
> Signed-off-by: Matthew Auld
Reviewed-by: Ramalingam C
> Cc: Thomas Hellström
> Cc: Ramalingam C
> ---
> drivers/gpu/drm/i915/g
e !CONFIG_DRM_I915_CAPTURE_ERROR case
> (kernel test robot)
> v6:
> - Use #if IS_ENABLED() instead of #ifdef to match driver style.
> - Move yet another change of allocation mode to the separate patch.
> - Commit message rework due to patch reordering.
>
> Signed-off-by: Thomas
the list link, as the page owner is
> allowed to do that.
>
> Signed-off-by: Thomas Hellström
Looks good to me
Reviewed-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 50 +++
> drivers/gpu/drm/i915/i915_gpu_error.h | 4 +--
>
08: R09:
> 7ffd14d79ab0
> [ 234.843119] R10: ffff R11: 0246 R12:
> 0014
> [ 234.843121] R13: R14: 7ffd14d79b60 R15:
> 0005
>
> v5:
> - Use __GFP_KSWAPD_RECLAIM rather than __GFP_NOW
From: Anshuman Gupta
Handles the plane programing for flat ccs and clear color modifiers for
DG2
Signed-off-by: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 3 +-
drivers/gpu/drm/i915/display
-by: Matthew Auld
Signed-off-by: Ramalingam C
cc: Simon Ser
cc: Pekka Paalanen
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: mesa-...@lists.freedesktop.org
Cc: Tony Ye
Cc: Slawomir Milczarek
---
include/uapi/drm/i915_drm.h | 67 ++---
1 file changed, 62 insertions(+), 5
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fb.c | 11 ++
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../drm/i915/display/intel_plane_initial.c| 1 +
: Rebased on new format modifier check [Ram]
Signed-off-by: Matt Roper
Signed-off-by: Mika Kahola (v2)
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
cc: Simon Ser
Cc: Pekka Paalanen
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: mesa-...@lists.freedesktop.org
Cc: Tony Ye
Cc: Slawomir
Documents the Flat-CCS feature and kernel handling required along with
modifiers used.
Signed-off-by: Ramalingam C
cc: Simon Ser
cc: Pekka Paalanen
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: mesa-...@lists.freedesktop.org
Cc: Tony Ye
Cc: Slawomir Milczarek
---
drivers/gpu/drm/i915/gt
Details of the new features getting added as part of DG2 enabling and their
implicit impact on the uAPI.
v2: improvised the Flat-CCS documentation [Danvet & CQ]
Signed-off-by: Ramalingam C
cc: Daniel Vetter
cc: Matthew Auld
cc: Simon Ser
cc: Pekka Paalanen
Cc: Jordan Justen
Cc: Ken
ccount.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 +++--
drivers/gpu/drm/i915/gt/intel_gtt.c | 9 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 9 ++
drivers/gpu/dr
/i915/uapi: document behaviour for DG2 64K support
Ramalingam C (3):
drm/i915/dg2: Prune the Y Tiling modifiers
drm/i915/Flat-CCS: Document on Flat-CCS memory compression
Doc/gpu/rfc/i915: i915 DG2 uAPI
Stanislav Lisovskiy (1):
drm/i915/dg2: Tile 4 plane format support
Stuart Summers (1
From: Stuart Summers
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c
From: Matthew Auld
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Reviewed-by: Lucas De
rk for all configurations.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 ++
drivers/gpu/drm/i915/gt/intel_gtt.c
supported by the HW.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 61 ++
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 106 +-
drivers/gpu
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 14 +++
drivers/gpu/drm/i915/gt/intel_migrate.c | 120 ++-
2 files changed, 131 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt
Remove the Y Tiling modifiers for DG2.
Signed-off-by: Ramalingam C
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_fb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index
compression states.
Cc: Joonas Lahtinen
Cc: Matthew Auld
Signed-off-by: CQ Tang
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 4 insertions(+)
diff
.
Cc: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 22 +++--
drivers/gpu/drm/i915
-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 16 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 6
drivers/gpu/drm/i915/i915_gem_evict.c | 17 ++
drivers/gpu/drm/i915
the HW expects the correct physical alignment and
size for every PTE, if we mark the page-table as 64K GTT mode.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt
901 - 1000 of 1382 matches
Mail list logo
