the clk API function for enable/disable the clock. Those functions
are already checking for NULL clk and returning 0 if that's the case.
Signed-off-by: Robert Chiras
Acked-by: Leonard Crestez
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8
drivers/gpu/drm/mxsfb
This IP requires full stop and re-start when changing display timings,
but we can change the pixel format while running.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff
Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF
is enabled, since it comes up with default value of 1 (this behaviour
has been seen on some imx8 platforms).
In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting
its value.
Signed-off-by: Robert Chiras
a better representation (guido)
- Included a patch submitted by Guido, while he was testing my patch-set
Guido Günther (1):
drm/mxsfb: Read bus flags from bridge if present
Mirela Rabulea (1):
drm/mxsfb: Signal mode changed when bpp changed
Robert Chiras (12):
drm/mxsfb: Update mxsfb to sup
The eLCDIF controller has control pin for the external LCD reset pin.
Add support for it and assert this pin in enable and de-assert it in
disable.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 14 ++
drivers/gpu/drm/mxsfb
Hi Leonard,
On Lu, 2019-08-26 at 19:19 +, Leonard Crestez wrote:
> On 26.08.2019 17:35, Stefan Agner wrote:
> >
> > On 2019-08-26 14:05, Guido Günther wrote:
> > >
> > > Hi,
> > > On Wed, Aug 21, 2019 at 01:15:40PM +0300, Robert Chiras wrote:
> &
e.g. the i.MX8QXP.
>
> It has been tested on the Librem 5 devkit using mxsfb.
>
> Signed-off-by: Guido Günther
> Co-developed-by: Robert Chiras
> ---
> drivers/gpu/drm/bridge/Kconfig | 2 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/dr
it will allow this driver to dinamically set the
video_pll clock for any kind of mode.
So, for the whole patch-set, you can add:
Tested-by: Robert Chiras
Signed-off-by: Robert Chiras
Best regards,
Robert
On Jo, 2019-08-22 at 12:44 +0200, Guido Günther wrote:
> This adds initial support for the
based on input from the user and panel
capabilities.
Save the bus format in crtc->mode.private_flags, so the bridge can
use it.
Signed-off-by: Robert Chiras
Signed-off-by: Mirela Rabulea
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c |
in
order to do horizontal crop on the frame buffer processed by the eLCDIF
block.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 79 --
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 1 +
drivers/gpu/drm/mxsfb
.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 17 +++---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 46 +-
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 4 +++-
drivers/gpu/drm/mxsfb/mxsfb_out.c | 26
From: Guido Günther
The bridge might have special requirmentes on the input bus. This
is e.g. used by the imx-nwl bridge.
Signed-off-by: Guido Günther
Reviewed-by: Stefan Agner
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Because of stability issues, we may want to limit the maximum bandwidth
required by the MXSFB (eLCDIF) driver.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 48 +++
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 2 ++
2
From: Mirela Rabulea
Add mxsfb_atomic_helper_check to signal mode changed when bpp changed.
This will trigger the execution of disable/enable on
a modeset with different bpp than the current one.
Signed-off-by: Mirela Rabulea
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers
Some of the existing registers in this controller are not defined, but
also not used. Add them to the register definitions, so that they can be
easily used in future improvements or fixes.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 15
Add new optional property 'max-memory-bandwidth', to limit the maximum
bandwidth used by the MXSFB_DRM driver.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/mxsfb.txt | 5 +
1 file changed, 5 insertions
Use BIT(x) and GEN_MASK(h, l) for better representation the inside of
various registers.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 151 ++---
1 file changed, 89 insertions(+), 62 deletions(-)
diff --git
Some of the registers, like LCDC_CTRL, CTRL2_OUTSTANDING_REQS and
CTRL1_RECOVERY_ON_UNDERFLOW needs to be properly cleared/initialized
for a better start and stop routine.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12
1 file
On Thu, Aug 22, 2019 at 01:18:21PM +, Robert Chiras wrote:
> >
> > Hi Guido,
> >
> > I added my signed-off, plus some comments inline.
> >
> > On Jo, 2019-08-22 at 12:44 +0200, Guido Günther wrote:
> > >
> > > This adds initial support
changed when bpp changed
Robert Chiras (13):
drm/mxsfb: Update mxsfb to support a bridge
drm/mxsfb: Add defines for the rest of registers
drm/mxsfb: Reset vital registers for a proper initialization
drm/mxsfb: Update register definitions using bit manipulation defines
drm/mxsfb: Update mxsfb
Some of the registers, like LCDC_CTRL, CTRL2_OUTSTANDING_REQS and
CTRL1_RECOVERY_ON_UNDERFLOW needs to be properly cleared/initialized
for a better start and stop routine.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12
1 file changed, 12 insertions
Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF
is enabled, since it comes up with default value of 1 (this behaviour
has been seen on some imx8 platforms).
In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting
its value.
Signed-off-by: Robert Chiras
This IP requires full stop and re-start when changing display timings,
but we can change the pixel format while running.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mxsfb
Use BIT(x) and GEN_MASK(h, l) for better representation the inside of
various registers.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 151 ++---
1 file changed, 89 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb
Some of the existing registers in this controller are not defined, but
also not used. Add them to the register definitions, so that they can be
easily used in future improvements or fixes.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 15 +++
1 file changed
the clk API function for enable/disable the clock. Those functions
are already checking for NULL clk and returning 0 if that's the case.
Signed-off-by: Robert Chiras
Acked-by: Leonard Crestez
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 32
The eLCDIF controller has control pin for the external LCD reset pin.
Add support for it and assert this pin in enable and de-assert it in
disable.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 14 ++
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 2 ++
2 files
Add new optional property 'max-memory-bandwidth', to limit the maximum
bandwidth used by the MXSFB_DRM driver.
Signed-off-by: Robert Chiras
---
Documentation/devicetree/bindings/display/mxsfb.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/display
From: Mirela Rabulea
Add mxsfb_atomic_helper_check to signal mode changed when bpp changed.
This will trigger the execution of disable/enable on
a modeset with different bpp than the current one.
Signed-off-by: Mirela Rabulea
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c
Because of stability issues, we may want to limit the maximum bandwidth
required by the MXSFB (eLCDIF) driver.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 48 +++
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 2 ++
2 files changed, 50
in
order to do horizontal crop on the frame buffer processed by the eLCDIF
block.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 79 --
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 1 +
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 16
3 files
From: Guido Günther
The bridge might have special requirmentes on the input bus. This
is e.g. used by the imx-nwl bridge.
Signed-off-by: Guido Günther
Reviewed-by: Stefan Agner
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
.
Signed-off-by: Robert Chiras
Tested-by: Guido Günther
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 17 +++---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 46 +-
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 4 +++-
drivers/gpu/drm/mxsfb/mxsfb_out.c | 26
with the '-v' parameter will result
in an astronomical refresh rate (1+ Hz), because of that.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
b/drivers/gpu/drm/mxsfb
Add new optional property 'max-res', to limit the maximum supported
resolution by the MXSFB_DRM driver.
Signed-off-by: Robert Chiras
---
Documentation/devicetree/bindings/display/mxsfb.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display
From: Mirela Rabulea
Add mxsfb_atomic_helper_check to signal mode changed when bpp changed.
This will trigger the execution of disable/enable on
a modeset with different bpp than the current one.
Signed-off-by: Mirela Rabulea
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c
Because of stability issues, we may want to limit the maximum resolution
supported by the MXSFB (eLCDIF) driver.
This patch add support for a new property which we can use to impose such
limitation.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 12 ++--
1 file
On Vi, 2019-06-14 at 10:39 -0300, Fabio Estevam wrote:
> Caution: EXT Email
>
> On Fri, Jun 14, 2019 at 10:29 AM Robert Chiras > wrote:
>
> >
> > The GPIO is active high, and the above sequence was received from
> > the
> > panel vendor in the foll
ontroller found
> on
> i.MX8 SoCs.
>
> It adds support for the i.MX8MQ but the same IP can be found on
> e.g. the i.MX8QXP.
>
> It has been tested on the Librem 5 devkit using mxsfb.
>
> Signed-off-by: Guido Günther
> Co-developed-by: Robert Chiras
> Signed-off-by:
On Mi, 2019-12-04 at 13:06 +0100, Guido Günther wrote:
> Hi Robert,
> On Tue, Dec 03, 2019 at 09:50:03AM +, Robert Chiras wrote:
> >
> > Hi Guido,
> >
> > Since your last revision sent, I've done more tests here and found
> > a
> > few more impro
From: Robert Chiras
The clock-drop-level is needed in order to add more blanking space needed
by DSI panels when sending DSI commands. One level is the equivalent of
phy_ref rate from the PLL rate. Since the PLL rate is targeted as highest
possible, each level should not get the crtc_clock too
From: Robert Chiras
This patch adds support for a new clock 'video_pll' in order to better
set the video_pll clock to a clock-rate that satisfies a mode's clock.
The video PLL, on i.MX8MQ, can drive both DC pixel-clock and DSI phy_ref
clock. When used with a bridge that can drive multiple modes
From: Robert Chiras
The flag MIPI_DSI_CLOCK_NON_CONTINUOUS was wrong used in the DSI driver,
so it was added to this panel, but not necessary.
So, remove this flag since it is not needed.
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/panel/panel-raydium-rm67191.c | 3 +--
1 file changed, 1
From: Robert Chiras
Add documentation for a new clock 'video_pll'.
Signed-off-by: Robert Chiras
---
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
b
From: Robert Chiras
This patch-set adds the new following features to the nwl-dsi bridge driver:
1. Control Video PLL from nwl-dsi driver
Add support for the Video PLL into the nwl-dsi driver, in order
to better control it's rate, depending on the requested video mode.
Controlling the Video
From: Laurentiu Palcu
DCSS needs active low VSYNC and HSYNC. Also, move the input selection in
the probe function, as this will not change at runtime.
Signed-off-by: Laurentiu Palcu
Signed-off-by: Robert Chiras
---
drivers/gpu/drm/bridge/nwl-dsi.c | 24
1 file
From: Robert Chiras
Add documentation for a new property: 'fsl,clock-drop-level'.
Signed-off-by: Robert Chiras
---
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/nwl
101 - 147 of 147 matches
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