Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/dg2: extend Wa_1409120013 to DG2

Reviewed-by: Clint Taylor -Clint On 11/16/21 9:48 AM, Matt Roper wrote: From: Matt Atwood Extend existing workaround 1409120013 to DG2. Cc: José Roberto de Souza Signed-off-by: Matt Atwood Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2

Re: [Intel-gfx] [PATCH v3 4/5] drm/i915/dg2: Add Wa_16013000631

Reviewed-by: Clint Taylor -Clint On 11/16/21 9:48 AM, Matt Roper wrote: From: Ramalingam C Invalidate IC cache through pipe control command as part of the ctx restore flow through indirect ctx pointer. v2: - Move pipe control from xcs indirect context to the rcs indirect context

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/dg2: Add Wa_16011777198

Correct, Reviewed-by: Clint Taylor -Clint On 11/16/21 9:48 AM, Matt Roper wrote: Coarse power gating for render should not be enabled on some DG2 steppings. Bspec: 52698 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++ 1 file changed, 11

Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/dg2: Add Wa_14010547955

Looks correct. Reviewed-by: Clint Taylor -Clint On 11/16/21 9:48 AM, Matt Roper wrote: This workaround is documented a bit strangely in the bspec; it's listed as an A0 workaround, but the description clarifies that the workaround is implicitly handled by the hardware and what the driver

Re: [PATCH 3/3] drm/i915/dg2: Program recommended HW settings

Reviewed-by: Clint Taylor -Clint On 11/2/21 3:25 PM, Matt Roper wrote: The bspec's performance guide suggests programming specific values into a few registers for optimal performance. Although these aren't workarounds, it's easiest to handle them inside the GT workaround functions (which

Re: [PATCH 1/2] drm/i915/xehpsdv: Define MOCS table for XeHP SDV

Appears to match latest BSPEC Reviewed-by: Clint Taylor -Clint On 9/3/21 5:35 PM, Matt Roper wrote: From: Lucas De Marchi Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to memory for L3 des

Re: [PATCH v3 0/3] add LG panel to dpcd quirk database

for specific sink/branch device that would cover similar issue. Cc: Jani Nikula Cc: Cooper Chiou Cc: Matt Atwood Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Cc: Clint Taylor Lee, Shawn C (3): drm: Add support for device_id based detection. drm: Change limited M/N quirk to constant N quirk

Re: [PATCH] drm/i915: Fix LSPCON TMDS output buffer enabling from low-power state

irmware loaded. Customer was concerned about the fix being in DRM instead of i915. However, there are no other SOCs that use this DRM function. Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com> Tested-by: Clint Taylor <clinton.a.tay...@intel.com> -Clint ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for

Re: [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy

Re: [RFC PATCH 6/7] drm: add support for DisplayPort CEC-Tunneling-over-AUX

On 05/26/2017 12:18 AM, Daniel Vetter wrote: On Thu, May 25, 2017 at 05:06:25PM +0200, Hans Verkuil wrote: From: Hans Verkuil This adds support for the DisplayPort CEC-Tunneling-over-AUX feature that is part of the DisplayPort 1.3 standard. Unfortunately, not all

Re: [RFC PATCH 7/7] drm/i915: add DisplayPort CEC-Tunneling-over-AUX support

On 05/30/2017 02:29 PM, Hans Verkuil wrote: On 05/30/2017 10:32 PM, Clint Taylor wrote: On 05/30/2017 09:54 AM, Hans Verkuil wrote: On 05/30/2017 06:49 PM, Hans Verkuil wrote: On 05/30/2017 04:19 PM, Clint Taylor wrote: On 05/30/2017 12:11 AM, Jani Nikula wrote: On Tue, 30 May 2017

Re: [RFC PATCH 7/7] drm/i915: add DisplayPort CEC-Tunneling-over-AUX support

On 05/30/2017 09:54 AM, Hans Verkuil wrote: On 05/30/2017 06:49 PM, Hans Verkuil wrote: On 05/30/2017 04:19 PM, Clint Taylor wrote: On 05/30/2017 12:11 AM, Jani Nikula wrote: On Tue, 30 May 2017, Hans Verkuil <hverk...@xs4all.nl> wrote: On 05/29/2017 09:00 PM, Daniel Vetter

Re: [RFC PATCH 7/7] drm/i915: add DisplayPort CEC-Tunneling-over-AUX support

On 05/30/2017 09:49 AM, Hans Verkuil wrote: On 05/30/2017 04:19 PM, Clint Taylor wrote: On 05/30/2017 12:11 AM, Jani Nikula wrote: On Tue, 30 May 2017, Hans Verkuil <hverk...@xs4all.nl> wrote: On 05/29/2017 09:00 PM, Daniel Vetter wrote: On Fri, May 26, 2017 at 12:20:48PM +0200

Re: [ANN] HDMI CEC Status Update

On 05/29/2017 11:53 PM, Hans Verkuil wrote: For those who are interested in HDMI CEC support I made a little status document that I intend to keep up to date: https://hverkuil.home.xs4all.nl/cec-status.txt My goal is to get CEC supported for any mainlined HDMI driver where the hardware

Re: [PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database

On 05/29/2017 04:06 AM, Jani Nikula wrote: On Thu, 18 May 2017, Clint Taylor <clinton.a.tay...@intel.com> wrote: On 05/18/2017 04:10 AM, Jani Nikula wrote: Face the fact, there are Display Port sink and branch devices out there in the wild that don't follow the Display Port specific

Re: [RFC PATCH 7/7] drm/i915: add DisplayPort CEC-Tunneling-over-AUX support

On 05/30/2017 12:11 AM, Jani Nikula wrote: On Tue, 30 May 2017, Hans Verkuil wrote: On 05/29/2017 09:00 PM, Daniel Vetter wrote: On Fri, May 26, 2017 at 12:20:48PM +0200, Hans Verkuil wrote: On 05/26/2017 09:15 AM, Daniel Vetter wrote: Did you look into also wiring

Re: [PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database

ille Syrjälä <ville.syrj...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Clint Taylor <clinton.a.tay...@intel.com> Cc: Adam Jackson <a...@redhat.com> Cc: Harry Wentland <harry.wentl...@amd.com> Signed-off-by: Jani Nikula <jani.nik...@int

Re: [PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database

devices ended up in regressions for other devices. So here we are. v2: Rebase on DRM DP desc read helpers Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Clint Taylor <clinton.a.tay...@intel.com> Cc: Adam Jackson &l

Re: [PATCH 2/2] drm/i915: Detect USB-C specific dongles before reducing M and N

On 05/11/2017 02:57 AM, Jani Nikula wrote: From: Clint Taylor <clinton.a.tay...@intel.com> The Analogix 7737 DP to HDMI converter requires reduced M and N values when to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9 via the DPCD quirk list. v2 by Jani: R

Re: [PATCH 1/2] drm/dp: start a DPCD based DP sink/branch device quirk database

properly. Naturally, the workaround of reducing main link attributes for all devices ended up in regressions for other devices. So here we are. Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Clint Taylor <clinton.a.tay..

Re: [PATCH v6 1/3] drm_fourcc: Add new P010, P016 video format

lines as the Y plane." The LSW contains U and the MSW contains V, hence the Cr:Cb in the comments of the V6 patch. -Clint Ander Cc: Daniel Stone <dan...@fooishbar.org> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-by: Randy Li <ay...@soulik.info>

Re: [PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format

On 02/28/2017 02:58 AM, ayaka wrote: On 02/28/2017 06:57 AM, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per channel video format. Rockchip's vop support this video format(little endia

Re: [PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format

On 02/28/2017 03:56 AM, Ville Syrjälä wrote: On Mon, Feb 27, 2017 at 02:57:58PM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per channel video format. Rockchip's vop support this

Re: [PATCH v4 1/2] drm_fourcc: Add new P010, P016 video format

On 02/27/2017 09:41 AM, Ville Syrjälä wrote: On Mon, Feb 27, 2017 at 09:21:09AM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per channel video format. Rockchip's vop support this

Re: [PATCH v2 1/2] drm_fourcc: Add new P010, P016 video format

On 01/04/2017 06:00 PM, Ayaka wrote: 從我的 iPad 傳送 Daniel Stone 於 2017年1月5日 上午1:02 寫道： Hi Randy, On 4 January 2017 at 16:29, Randy Li wrote: index 90d2cc8..23c8e99 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@

[PATCH] drm/edid: Reduce horizontal timings for pixel replicated modes

On 08/25/2014 06:02 AM, Daniel Vetter wrote: > On Mon, Aug 18, 2014 at 02:02:14PM -0700, clinton.a.taylor at intel.com wrote: >> From: Clint Taylor >> >> Pixel replicated modes should be 720 horizontal pixel and pixel >> replicated by the HW across the HDMI cable

[Intel-gfx] [PATCH] drm: HDMI pixel replication modes now hactive of 720 for pixel replication

On 08/12/2014 04:07 AM, Ville Syrj?l? wrote: > On Tue, Jul 29, 2014 at 02:58:23PM -0700, clinton.a.taylor at intel.com wrote: >> From: Clint Taylor >> >> CEA SD interlaced modes use a horizontal 720 pixels that are pixel >> replicated to 1440. The current driver r