Re: [PATCH] drm/imx/dcss: fix resource size calculation

[Laurentiu Palcu]

Hi Dan,

On Tue, Feb 13, 2024 at 09:05:01PM +0300, Dan Carpenter wrote:
> The resource is inclusive of the ->start and ->end addresses so this
> calculation is not correct.  It should be "res->end - res->start + 1".
> Use the resource_size() to do the calculation.
> 
> Fixes: 90393c9b5408 ("drm/imx/dcss: request memory region")
> Signed-off-by: Dan Carpenter 

Reviewed-by: Laurentiu Palcu 

And pushed to drm-misc-next-fixes.

Thanks,
Laurentiu

> ---
> From static analysis.  Not tested.
> 
>  drivers/gpu/drm/imx/dcss/dcss-dev.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
> b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> index 597e9b7bd4bf..7fd0c4c14205 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> @@ -167,7 +167,6 @@ struct dcss_dev *dcss_dev_create(struct device *dev, bool 
> hdmi_output)
>   struct resource *res;
>   struct dcss_dev *dcss;
>   const struct dcss_type_data *devtype;
> - resource_size_t res_len;
>  
>   devtype = of_device_get_match_data(dev);
>   if (!devtype) {
> @@ -181,8 +180,7 @@ struct dcss_dev *dcss_dev_create(struct device *dev, bool 
> hdmi_output)
>   return ERR_PTR(-EINVAL);
>   }
>  
> - res_len = res->end - res->start;
> - if (!devm_request_mem_region(dev, res->start, res_len, "dcss")) {
> + if (!devm_request_mem_region(dev, res->start, resource_size(res), 
> "dcss")) {
>   dev_err(dev, "cannot request memory region\n");
>   return ERR_PTR(-EBUSY);
>   }
> -- 
> 2.43.0
> 

Re: [PATCH v4 0/2] drm/imx/dcss: implement region request and devres

[Laurentiu Palcu]

Hi Philipp,

Applied series to drm-misc-next.

Thanks,
Laurentiu

On Wed, Jan 24, 2024 at 12:19:03PM +0100, Philipp Stanner wrote:
> @Laurentiu:
> Thank you very much for the review. I was indeed on an older branch. As
> Linus's master is currently broken for ARM64 [1], unfortunately, I built
> it instead against:
> 60096f0a77600ac2cc92b82fee279d1905576950
> 
> Hope that's fine.
> 
> 
> Changes in v4:
> - Add Laurentiu's Reviewed-by to patch #1
> - Remove unnecsseray struct device pointers from all touched files
> - Rebase against newer kernel due to changes in dcss_drv_platform_remove()
> 
> Changes in v3:
> - Fix build errors (missing variable, forgotten remove to call of deleted
>   function)
> 
> Changes in v2:
> - Add the region-request to this patch-series. That was previously a
>   separate patch.
> 
> dcss currently does not request its memory resource. This series adds
> that request with devres. As we're at it, it also ports all the ioremaps
> and associated allocations to devres.
> 
> I can build this, but I don't have the hardware available to test it. So
> you might want to have a closer look.
> 
> P.
> 
> [1] 
> https://lore.kernel.org/lkml/45ad1d0f-a10f-483e-848a-76a30252edbe@paulmck-laptop/
> 
> 
> Philipp Stanner (2):
>   drm/imx/dcss: request memory region
>   drm/imx/dcss: have all init functions use devres
> 
>  drivers/gpu/drm/imx/dcss/dcss-blkctl.c | 13 ++---
>  drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 14 +++---
>  drivers/gpu/drm/imx/dcss/dcss-dev.c| 19 +--
>  drivers/gpu/drm/imx/dcss/dcss-dev.h|  1 -
>  drivers/gpu/drm/imx/dcss/dcss-dpr.c| 21 +++--
>  drivers/gpu/drm/imx/dcss/dcss-drv.c| 12 +++-
>  drivers/gpu/drm/imx/dcss/dcss-dtg.c| 26 +-
>  drivers/gpu/drm/imx/dcss/dcss-scaler.c | 21 +++--
>  drivers/gpu/drm/imx/dcss/dcss-ss.c | 12 +++-
>  9 files changed, 31 insertions(+), 108 deletions(-)
> 
> -- 
> 2.43.0
> 

Re: [PATCH v4 2/2] drm/imx/dcss: have all init functions use devres

[Laurentiu Palcu]

Hi Philipp,

On Wed, Jan 24, 2024 at 12:19:05PM +0100, Philipp Stanner wrote:
> dcss currently allocates and ioremaps quite a few resources in its probe
> function's call graph. Devres now provides convenient functions which
> perform the same task but do the cleanup automatically.
> 
> Port all memory allocations and ioremap() calls to the devres
> counterparts.
> 
> Signed-off-by: Philipp Stanner 

Reviewed-by: Laurentiu Palcu 

Thanks,
Laurentiu
> ---
>  drivers/gpu/drm/imx/dcss/dcss-blkctl.c | 13 ++---
>  drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 14 +++---
>  drivers/gpu/drm/imx/dcss/dcss-dev.c| 12 ++--
>  drivers/gpu/drm/imx/dcss/dcss-dev.h|  1 -
>  drivers/gpu/drm/imx/dcss/dcss-dpr.c| 21 +++--
>  drivers/gpu/drm/imx/dcss/dcss-drv.c| 12 +++-
>  drivers/gpu/drm/imx/dcss/dcss-dtg.c| 26 +-
>  drivers/gpu/drm/imx/dcss/dcss-scaler.c | 21 +++--
>  drivers/gpu/drm/imx/dcss/dcss-ss.c | 12 +++-
>  9 files changed, 24 insertions(+), 108 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c 
> b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
> index c9b54bb2692d..803e3fcdb50f 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
> @@ -42,14 +42,13 @@ int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long 
> blkctl_base)
>  {
>   struct dcss_blkctl *blkctl;
>  
> - blkctl = kzalloc(sizeof(*blkctl), GFP_KERNEL);
> + blkctl = devm_kzalloc(dcss->dev, sizeof(*blkctl), GFP_KERNEL);
>   if (!blkctl)
>   return -ENOMEM;
>  
> - blkctl->base_reg = ioremap(blkctl_base, SZ_4K);
> + blkctl->base_reg = devm_ioremap(dcss->dev, blkctl_base, SZ_4K);
>   if (!blkctl->base_reg) {
>   dev_err(dcss->dev, "unable to remap BLK CTRL base\n");
> - kfree(blkctl);
>   return -ENOMEM;
>   }
>  
> @@ -60,11 +59,3 @@ int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long 
> blkctl_base)
>  
>   return 0;
>  }
> -
> -void dcss_blkctl_exit(struct dcss_blkctl *blkctl)
> -{
> - if (blkctl->base_reg)
> - iounmap(blkctl->base_reg);
> -
> - kfree(blkctl);
> -}
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-ctxld.c 
> b/drivers/gpu/drm/imx/dcss/dcss-ctxld.c
> index 3a84cb3209c4..e41d5c2a3ea4 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-ctxld.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-ctxld.c
> @@ -202,7 +202,7 @@ int dcss_ctxld_init(struct dcss_dev *dcss, unsigned long 
> ctxld_base)
>   struct dcss_ctxld *ctxld;
>   int ret;
>  
> - ctxld = kzalloc(sizeof(*ctxld), GFP_KERNEL);
> + ctxld = devm_kzalloc(dcss->dev, sizeof(*ctxld), GFP_KERNEL);
>   if (!ctxld)
>   return -ENOMEM;
>  
> @@ -217,7 +217,7 @@ int dcss_ctxld_init(struct dcss_dev *dcss, unsigned long 
> ctxld_base)
>   goto err;
>   }
>  
> - ctxld->ctxld_reg = ioremap(ctxld_base, SZ_4K);
> + ctxld->ctxld_reg = devm_ioremap(dcss->dev, ctxld_base, SZ_4K);
>   if (!ctxld->ctxld_reg) {
>   dev_err(dcss->dev, "ctxld: unable to remap ctxld base\n");
>   ret = -ENOMEM;
> @@ -226,18 +226,14 @@ int dcss_ctxld_init(struct dcss_dev *dcss, unsigned 
> long ctxld_base)
>  
>   ret = dcss_ctxld_irq_config(ctxld, to_platform_device(dcss->dev));
>   if (ret)
> - goto err_irq;
> + goto err;
>  
>   dcss_ctxld_hw_cfg(ctxld);
>  
>   return 0;
>  
> -err_irq:
> - iounmap(ctxld->ctxld_reg);
> -
>  err:
>   dcss_ctxld_free_ctx(ctxld);
> - kfree(ctxld);
>  
>   return ret;
>  }
> @@ -246,11 +242,7 @@ void dcss_ctxld_exit(struct dcss_ctxld *ctxld)
>  {
>   free_irq(ctxld->irq, ctxld);
>  
> - if (ctxld->ctxld_reg)
> - iounmap(ctxld->ctxld_reg);
> -
>   dcss_ctxld_free_ctx(ctxld);
> - kfree(ctxld);
>  }
>  
>  static int dcss_ctxld_enable_locked(struct dcss_ctxld *ctxld)
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
> b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> index d448bf1c205e..597e9b7bd4bf 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> @@ -109,8 +109,6 @@ static int dcss_submodules_init(struct dcss_dev *dcss)
>   dcss_ctxld_exit(dcss->ctxld);
>  
>  ctxld_err:
> - dcss_blkctl_exit(dcss->blkctl);
> -
>   dcss_clocks_disable(dcss);
>  
>   return ret;
> @@ -124,7 +122,6 @@ static void dcss_submodules_stop(struct dcss_dev *dcs

Re: [PATCH v3 2/2] drm/imx/dcss: have all init functions use devres

[Laurentiu Palcu]

Hi Philipp,

Several minor comments below.

On Thu, Jan 11, 2024 at 11:13:47AM +0100, Philipp Stanner wrote:
> dcss currently allocates and ioremaps quite a few resources in its probe
> function's call graph. Devres now provides convenient functions which
> perform the same task but do the cleanup automatically.
> 
> Port all memory allocations and ioremap() calls to the devres
> counterparts.
> 
> Signed-off-by: Philipp Stanner 
> ---
>  drivers/gpu/drm/imx/dcss/dcss-blkctl.c | 14 +++---
>  drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 15 ---
>  drivers/gpu/drm/imx/dcss/dcss-dev.c| 12 ++--
>  drivers/gpu/drm/imx/dcss/dcss-dev.h|  1 -
>  drivers/gpu/drm/imx/dcss/dcss-dpr.c| 25 ++---
>  drivers/gpu/drm/imx/dcss/dcss-drv.c| 12 +++-
>  drivers/gpu/drm/imx/dcss/dcss-dtg.c| 23 ---
>  drivers/gpu/drm/imx/dcss/dcss-scaler.c | 24 +---
>  drivers/gpu/drm/imx/dcss/dcss-ss.c | 11 +++
>  9 files changed, 30 insertions(+), 107 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c 
> b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
> index c9b54bb2692d..58e12ec65f80 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
> @@ -41,15 +41,15 @@ void dcss_blkctl_cfg(struct dcss_blkctl *blkctl)
>  int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long blkctl_base)
>  {
>   struct dcss_blkctl *blkctl;
> + struct device *dev = dcss->dev;
>  
> - blkctl = kzalloc(sizeof(*blkctl), GFP_KERNEL);
> + blkctl = devm_kzalloc(dev, sizeof(*blkctl), GFP_KERNEL);
>   if (!blkctl)
>   return -ENOMEM;
>  
> - blkctl->base_reg = ioremap(blkctl_base, SZ_4K);
> + blkctl->base_reg = devm_ioremap(dev, blkctl_base, SZ_4K);
>   if (!blkctl->base_reg) {
>   dev_err(dcss->dev, "unable to remap BLK CTRL base\n");
> - kfree(blkctl);
>   return -ENOMEM;
>   }
>  
> @@ -60,11 +60,3 @@ int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long 
> blkctl_base)
>  
>   return 0;
>  }
> -
> -void dcss_blkctl_exit(struct dcss_blkctl *blkctl)
> -{
> - if (blkctl->base_reg)
> - iounmap(blkctl->base_reg);
> -
> - kfree(blkctl);
> -}
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-ctxld.c 
> b/drivers/gpu/drm/imx/dcss/dcss-ctxld.c
> index 3a84cb3209c4..444511d0f382 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-ctxld.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-ctxld.c
> @@ -199,10 +199,11 @@ static int dcss_ctxld_alloc_ctx(struct dcss_ctxld 
> *ctxld)
>  
>  int dcss_ctxld_init(struct dcss_dev *dcss, unsigned long ctxld_base)
>  {
> + struct device *dev = dcss->dev;
>   struct dcss_ctxld *ctxld;
>   int ret;
>  
> - ctxld = kzalloc(sizeof(*ctxld), GFP_KERNEL);
> + ctxld = devm_kzalloc(dev, sizeof(*ctxld), GFP_KERNEL);
>   if (!ctxld)
>   return -ENOMEM;
>  
> @@ -217,7 +218,7 @@ int dcss_ctxld_init(struct dcss_dev *dcss, unsigned long 
> ctxld_base)
>   goto err;
>   }
>  
> - ctxld->ctxld_reg = ioremap(ctxld_base, SZ_4K);
> + ctxld->ctxld_reg = devm_ioremap(dev, ctxld_base, SZ_4K);
>   if (!ctxld->ctxld_reg) {
>   dev_err(dcss->dev, "ctxld: unable to remap ctxld base\n");
>   ret = -ENOMEM;
> @@ -226,18 +227,14 @@ int dcss_ctxld_init(struct dcss_dev *dcss, unsigned 
> long ctxld_base)
>  
>   ret = dcss_ctxld_irq_config(ctxld, to_platform_device(dcss->dev));
>   if (ret)
> - goto err_irq;
> + goto err;
>  
>   dcss_ctxld_hw_cfg(ctxld);
>  
>   return 0;
>  
> -err_irq:
> - iounmap(ctxld->ctxld_reg);
> -
>  err:
>   dcss_ctxld_free_ctx(ctxld);
> - kfree(ctxld);
>  
>   return ret;
>  }
> @@ -246,11 +243,7 @@ void dcss_ctxld_exit(struct dcss_ctxld *ctxld)
>  {
>   free_irq(ctxld->irq, ctxld);
>  
> - if (ctxld->ctxld_reg)
> - iounmap(ctxld->ctxld_reg);
> -
>   dcss_ctxld_free_ctx(ctxld);
> - kfree(ctxld);
>  }
>  
>  static int dcss_ctxld_enable_locked(struct dcss_ctxld *ctxld)
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
> b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> index d448bf1c205e..597e9b7bd4bf 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> @@ -109,8 +109,6 @@ static int dcss_submodules_init(struct dcss_dev *dcss)
>   dcss_ctxld_exit(dcss->ctxld);
>  
>  ctxld_err:
> - dcss_blkctl_exit(dcss->blkctl);
> -
>   dcss_clocks_disable(dcss);
>  
>   return ret;
> @@ -124,7 +122,6 @@ static void dcss_submodules_stop(struct dcss_dev *dcss)
>   dcss_ss_exit(dcss->ss);
>   dcss_dtg_exit(dcss->dtg);
>   dcss_ctxld_exit(dcss->ctxld);
> - dcss_blkctl_exit(dcss->blkctl);
>   dcss_clocks_disable(dcss);
>  }
>  
> @@ -190,7 +187,7 @@ struct dcss_dev *dcss_dev_create(struct device *dev, bool 
> hdmi_output)
>   return ERR_PTR(-EBUSY);

Re: [PATCH v3 1/2] drm/imx/dcss: request memory region

[Laurentiu Palcu]

Hi Philipp,

On Thu, Jan 11, 2024 at 11:13:46AM +0100, Philipp Stanner wrote:
> The driver's memory regions are currently just ioremap()ed, but not
> reserved through a request. That's not a bug, but having the request is
> a little more robust.
> 
> Implement the region-request through the corresponding managed
> devres-function.
> 
> Signed-off-by: Philipp Stanner 

Reviewed-by: Laurentiu Palcu 

Thanks,
Laurentiu

> ---
>  drivers/gpu/drm/imx/dcss/dcss-dev.c | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
> b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> index 4f3af0dfb344..d448bf1c205e 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> @@ -170,6 +170,7 @@ struct dcss_dev *dcss_dev_create(struct device *dev, bool 
> hdmi_output)
>   struct resource *res;
>   struct dcss_dev *dcss;
>   const struct dcss_type_data *devtype;
> + resource_size_t res_len;
>  
>   devtype = of_device_get_match_data(dev);
>   if (!devtype) {
> @@ -183,6 +184,12 @@ struct dcss_dev *dcss_dev_create(struct device *dev, 
> bool hdmi_output)
>   return ERR_PTR(-EINVAL);
>   }
>  
> + res_len = res->end - res->start;
> + if (!devm_request_mem_region(dev, res->start, res_len, "dcss")) {
> + dev_err(dev, "cannot request memory region\n");
> + return ERR_PTR(-EBUSY);
> + }
> +
>   dcss = kzalloc(sizeof(*dcss), GFP_KERNEL);
>   if (!dcss)
>   return ERR_PTR(-ENOMEM);
> -- 
> 2.43.0
> 

Re: [PATCH] MAINTAINERS: Document that the NXP i.MX 8MQ DCSS driver goes thru drm-misc

[Laurentiu Palcu]

On Mon, Sep 25, 2023 at 03:49:29PM -0700, Douglas Anderson wrote:
> As per the discussion on the lists [1], changes to this driver
> generally flow through drm-misc. Add a tag in MAINTAINERS to document
> this
> 
> [1] 
> https://lore.kernel.org/r/20230925054710.r3guqn5jzdl4g...@fsr-ub1664-121.ea.freescale.net
> 
> Signed-off-by: Douglas Anderson 

Acked-by: Laurentiu Palcu 

Thanks,
Laurentiu

> ---
> 
>  MAINTAINERS | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d72d3af551fb..d20a375ecd7d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -15225,6 +15225,7 @@ M:Laurentiu Palcu 
>  R:   Lucas Stach 
>  L:   dri-devel@lists.freedesktop.org
>  S:   Maintained
> +T:   git git://anongit.freedesktop.org/drm/drm-misc
>  F:   Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
>  F:   drivers/gpu/drm/imx/dcss/
>  
> -- 
> 2.42.0.515.g380fc7ccd1-goog
> 

Re: [RFT PATCH v2 01/12] drm/imx/dcss: Call drm_atomic_helper_shutdown() at shutdown time

[Laurentiu Palcu]

Hi Doug,

On Fri, Sep 22, 2023 at 08:44:16AM -0700, Doug Anderson wrote:
> Hi,
> 
> On Fri, Sep 22, 2023 at 12:56 AM Laurentiu Palcu
>  wrote:
> >
> > Hi,
> >
> > On Thu, Sep 21, 2023 at 12:26:44PM -0700, Douglas Anderson wrote:
> > > Based on grepping through the source code this driver appears to be
> > > missing a call to drm_atomic_helper_shutdown() at system shutdown
> > > time. Among other things, this means that if a panel is in use that it
> > > won't be cleanly powered off at system shutdown time.
> > >
> > > The fact that we should call drm_atomic_helper_shutdown() in the case
> > > of OS shutdown/restart comes straight out of the kernel doc "driver
> > > instance overview" in drm_drv.c.
> > >
> > > Suggested-by: Maxime Ripard 
> > > Reviewed-by: Maxime Ripard 
> > > Signed-off-by: Douglas Anderson 
> >
> > No issues found on i.MX8MQ.
> >
> > Tested-by: Laurentiu Palcu 
> > Reviewed-by: Laurentiu Palcu 
> 
> Thanks! Would you expect this patch to land through drm-misc? If so,
> I'm happy to commit it there with your tags.

Yes, please do. The i.MX8MQ DCSS patches go through drm-misc.

> If patches to this driver normally flow through drm-misc, I'm also
> happy to post a patch to MAINTAINERS (or review a patch you post)
> adding this to the entry for "NXP i.MX 8MQ DCSS DRIVER":
> 
> T: git git://anongit.freedesktop.org/drm/drm-misc
> 
> ...which would make it obvious in the future that things should land
> through drm-misc.

Thanks, that sounds good.

Laurentiu

Re: [RFT PATCH v2 01/12] drm/imx/dcss: Call drm_atomic_helper_shutdown() at shutdown time

[Laurentiu Palcu]

Hi,

On Thu, Sep 21, 2023 at 12:26:44PM -0700, Douglas Anderson wrote:
> Based on grepping through the source code this driver appears to be
> missing a call to drm_atomic_helper_shutdown() at system shutdown
> time. Among other things, this means that if a panel is in use that it
> won't be cleanly powered off at system shutdown time.
> 
> The fact that we should call drm_atomic_helper_shutdown() in the case
> of OS shutdown/restart comes straight out of the kernel doc "driver
> instance overview" in drm_drv.c.
> 
> Suggested-by: Maxime Ripard 
> Reviewed-by: Maxime Ripard 
> Signed-off-by: Douglas Anderson 

No issues found on i.MX8MQ.

Tested-by: Laurentiu Palcu 
Reviewed-by: Laurentiu Palcu 

Thanks,
Laurentiu

> ---
> This commit is only compile-time tested.
> 
> (no changes since v1)
> 
>  drivers/gpu/drm/imx/dcss/dcss-drv.c | 8 
>  drivers/gpu/drm/imx/dcss/dcss-kms.c | 7 +++
>  drivers/gpu/drm/imx/dcss/dcss-kms.h | 1 +
>  3 files changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-drv.c 
> b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> index c68b0d93ae9e..b61cec0cc79d 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-drv.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> @@ -92,6 +92,13 @@ static int dcss_drv_platform_remove(struct platform_device 
> *pdev)
>   return 0;
>  }
>  
> +static void dcss_drv_platform_shutdown(struct platform_device *pdev)
> +{
> + struct dcss_drv *mdrv = dev_get_drvdata(>dev);
> +
> + dcss_kms_shutdown(mdrv->kms);
> +}
> +
>  static struct dcss_type_data dcss_types[] = {
>   [DCSS_IMX8MQ] = {
>   .name = "DCSS_IMX8MQ",
> @@ -114,6 +121,7 @@ MODULE_DEVICE_TABLE(of, dcss_of_match);
>  static struct platform_driver dcss_platform_driver = {
>   .probe  = dcss_drv_platform_probe,
>   .remove = dcss_drv_platform_remove,
> + .shutdown = dcss_drv_platform_shutdown,
>   .driver = {
>   .name = "imx-dcss",
>   .of_match_table = dcss_of_match,
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
> b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> index 896de946f8df..d0ea4e97cded 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> @@ -172,3 +172,10 @@ void dcss_kms_detach(struct dcss_kms_dev *kms)
>   dcss_crtc_deinit(>crtc, drm);
>   drm->dev_private = NULL;
>  }
> +
> +void dcss_kms_shutdown(struct dcss_kms_dev *kms)
> +{
> + struct drm_device *drm = >base;
> +
> + drm_atomic_helper_shutdown(drm);
> +}
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.h 
> b/drivers/gpu/drm/imx/dcss/dcss-kms.h
> index dfe5dd99eea3..62521c1fd6d2 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-kms.h
> +++ b/drivers/gpu/drm/imx/dcss/dcss-kms.h
> @@ -34,6 +34,7 @@ struct dcss_kms_dev {
>  
>  struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss);
>  void dcss_kms_detach(struct dcss_kms_dev *kms);
> +void dcss_kms_shutdown(struct dcss_kms_dev *kms);
>  int dcss_crtc_init(struct dcss_crtc *crtc, struct drm_device *drm);
>  void dcss_crtc_deinit(struct dcss_crtc *crtc, struct drm_device *drm);
>  struct dcss_plane *dcss_plane_init(struct drm_device *drm,
> -- 
> 2.42.0.515.g380fc7ccd1-goog
> 

Re: [PATCH 1/1] drm/imx/dcss: Use dev_err_probe

[Laurentiu Palcu]

Hi,

On Mon, Jul 17, 2023 at 11:29:50AM +0200, Alexander Stein wrote:
> This helps identifying problems with downstream pipeline devices, like
> HDMI/DP output.
> 
> Signed-off-by: Alexander Stein 
Reviewed-by: Laurentiu Palcu 

Pushed to drm-misc-next.

Thanks,
Laurentiu

> ---
>  drivers/gpu/drm/imx/dcss/dcss-drv.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-drv.c 
> b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> index 4f2291610139..c68b0d93ae9e 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-drv.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> @@ -66,6 +66,7 @@ static int dcss_drv_platform_probe(struct platform_device 
> *pdev)
> mdrv->kms = dcss_kms_attach(mdrv->dcss);
> if (IS_ERR(mdrv->kms)) {
> err = PTR_ERR(mdrv->kms);
> +   dev_err_probe(dev, err, "Failed to initialize KMS\n");
> goto dcss_shutoff;
> }
> 
> --
> 2.34.1
> 

Re: [PATCH v2] drm/probe_helper: sort out poll_running vs poll_enabled

[Laurentiu Palcu]

On Wed, Jan 18, 2023 at 01:39:05AM +0200, Dmitry Baryshkov wrote:
> There are two flags attemting to guard connector polling:
> poll_enabled and poll_running. While poll_enabled semantics is clearly
> defined and fully adhered (mark that drm_kms_helper_poll_init() was
> called and not finalized by the _fini() call), the poll_running flag
> doesn't have such clearliness.
> 
> This flag is used only in drm_helper_probe_single_connector_modes() to
> guard calling of drm_kms_helper_poll_enable, it doesn't guard the
> drm_kms_helper_poll_fini(), etc. Change it to only be set if the polling
> is actually running. Tie HPD enablement to this flag.
> 
> This fixes the following warning reported after merging the HPD series:
> 
> Hot plug detection already enabled
> WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_bridge.c:1257 
> drm_bridge_hpd_enable+0x94/0x9c [drm]
> Modules linked in: videobuf2_memops snd_soc_simple_card 
> snd_soc_simple_card_utils fsl_imx8_ddr_perf videobuf2_common 
> snd_soc_imx_spdif adv7511 etnaviv imx8m_ddrc imx_dcss mc cec nwl_dsi gov
> CPU: 2 PID: 9 Comm: kworker/u8:0 Not tainted 6.2.0-rc2-15208-g25b283acd578 #6
> Hardware name: NXP i.MX8MQ EVK (DT)
> Workqueue: events_unbound deferred_probe_work_func
> pstate: 6005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> pc : drm_bridge_hpd_enable+0x94/0x9c [drm]
> lr : drm_bridge_hpd_enable+0x94/0x9c [drm]
> sp : 89ef3740
> x29: 89ef3740 x28: 09331f00 x27: 1000
> x26: 0020 x25: 81148ed8 x24: 0a8fe000
> x23: fffd x22: 05086348 x21: 81133ee0
> x20: 0550d800 x19: 05086288 x18: 0006
> x17:  x16: 896ef008 x15: 972891004260
> x14: 2a1403e19400 x13: 972891004260 x12: 2a1403e19400
> x11: 7100385f29400801 x10: 0aa0 x9 : 88112744
> x8 : 00250b00 x7 : 0003 x6 : 0011
> x5 :  x4 : bd986a48 x3 : 0001
> x2 :  x1 :  x0 : 0025
> Call trace:
>  drm_bridge_hpd_enable+0x94/0x9c [drm]
>  drm_bridge_connector_enable_hpd+0x2c/0x3c [drm_kms_helper]
>  drm_kms_helper_poll_enable+0x94/0x10c [drm_kms_helper]
>  drm_helper_probe_single_connector_modes+0x1a8/0x510 [drm_kms_helper]
>  drm_client_modeset_probe+0x204/0x1190 [drm]
>  __drm_fb_helper_initial_config_and_unlock+0x5c/0x4a4 [drm_kms_helper]
>  drm_fb_helper_initial_config+0x54/0x6c [drm_kms_helper]
>  drm_fbdev_client_hotplug+0xd0/0x140 [drm_kms_helper]
>  drm_fbdev_generic_setup+0x90/0x154 [drm_kms_helper]
>  dcss_kms_attach+0x1c8/0x254 [imx_dcss]
>  dcss_drv_platform_probe+0x90/0xfc [imx_dcss]
>  platform_probe+0x70/0xcc
>  really_probe+0xc4/0x2e0
>  __driver_probe_device+0x80/0xf0
>  driver_probe_device+0xe0/0x164
>  __device_attach_driver+0xc0/0x13c
>  bus_for_each_drv+0x84/0xe0
>  __device_attach+0xa4/0x1a0
>  device_initial_probe+0x1c/0x30
>  bus_probe_device+0xa4/0xb0
>  deferred_probe_work_func+0x90/0xd0
>  process_one_work+0x200/0x474
>  worker_thread+0x74/0x43c
>  kthread+0xfc/0x110
>  ret_from_fork+0x10/0x20
> ---[ end trace  ]---
> 
> Reported-by: Laurentiu Palcu 
> Fixes: c8268795c9a9 ("drm/probe-helper: enable and disable HPD on connectors")
> Tested-by: Marek Szyprowski 
> Tested-by: Chen-Yu Tsai 
> Signed-off-by: Dmitry Baryshkov 

I gave this a test and the warning is gone. Also, HPD works as expected.

Acked-by: Laurentiu Palcu 
Tested-by: Laurentiu Palcu 

Cheers,
Laurentiu

> ---
> 
> Changes since v1:
> - Fixed drm_kms_helper_enable_hpd() to call enable_hpd() instead of
>   disable_hpd().
> 
> ---
>  drivers/gpu/drm/drm_probe_helper.c | 110 +
>  1 file changed, 63 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_probe_helper.c 
> b/drivers/gpu/drm/drm_probe_helper.c
> index 7973f2589ced..04754bb7b131 100644
> --- a/drivers/gpu/drm/drm_probe_helper.c
> +++ b/drivers/gpu/drm/drm_probe_helper.c
> @@ -222,6 +222,45 @@ drm_connector_mode_valid(struct drm_connector *connector,
>   return ret;
>  }
>  
> +static void drm_kms_helper_disable_hpd(struct drm_device *dev)
> +{
> + struct drm_connector *connector;
> + struct drm_connector_list_iter conn_iter;
> +
> + drm_connector_list_iter_begin(dev, _iter);
> + drm_for_each_connector_iter(connector, _iter) {
> + const struct drm_connector_helper_funcs *funcs =
> + connector->helper_private;
> +
> + if (funcs && funcs->disable_hpd)
> + funcs->disable_hpd(connector);
> + }
> + drm_con

Re: [PATCH] drm/probe_helper: sort out poll_running vs poll_enabled

[Laurentiu Palcu]

Hi Dmitry,

On Thu, Jan 12, 2023 at 05:42:47PM +0200, Dmitry Baryshkov wrote:
> There are two flags attemting to guard connector polling:
> poll_enabled and poll_running. While poll_enabled semantics is clearly
> defined and fully adhered (mark that drm_kms_helper_poll_init() was
> called and not finalized by the _fini() call), the poll_running flag
> doesn't have such clearliness.
> 
> This flag is used only in drm_helper_probe_single_connector_modes() to
> guard calling of drm_kms_helper_poll_enable, it doesn't guard the
> drm_kms_helper_poll_fini(), etc. Change it to only be set if the polling
> is actually running. Tie HPD enablement to this flag.
> 
> This fix the following warning reported after merging the HPD series:

s/fix/fixes/

> 
> Hot plug detection already enabled
> WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_bridge.c:1257 
> drm_bridge_hpd_enable+0x94/0x9c [drm]
> Modules linked in: videobuf2_memops snd_soc_simple_card 
> snd_soc_simple_card_utils fsl_imx8_ddr_perf videobuf2_common 
> snd_soc_imx_spdif adv7511 etnaviv imx8m_ddrc imx_dcss mc cec nwl_dsi gov
> CPU: 2 PID: 9 Comm: kworker/u8:0 Not tainted 6.2.0-rc2-15208-g25b283acd578 #6
> Hardware name: NXP i.MX8MQ EVK (DT)
> Workqueue: events_unbound deferred_probe_work_func
> pstate: 6005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> pc : drm_bridge_hpd_enable+0x94/0x9c [drm]
> lr : drm_bridge_hpd_enable+0x94/0x9c [drm]
> sp : 89ef3740
> x29: 89ef3740 x28: 09331f00 x27: 1000
> x26: 0020 x25: 81148ed8 x24: 0a8fe000
> x23: fffd x22: 05086348 x21: 81133ee0
> x20: 0550d800 x19: 05086288 x18: 0006
> x17:  x16: 896ef008 x15: 972891004260
> x14: 2a1403e19400 x13: 972891004260 x12: 2a1403e19400
> x11: 7100385f29400801 x10: 0aa0 x9 : 88112744
> x8 : 00250b00 x7 : 0003 x6 : 0011
> x5 :  x4 : bd986a48 x3 : 0001
> x2 :  x1 :  x0 : 0025
> Call trace:
>  drm_bridge_hpd_enable+0x94/0x9c [drm]
>  drm_bridge_connector_enable_hpd+0x2c/0x3c [drm_kms_helper]
>  drm_kms_helper_poll_enable+0x94/0x10c [drm_kms_helper]
>  drm_helper_probe_single_connector_modes+0x1a8/0x510 [drm_kms_helper]
>  drm_client_modeset_probe+0x204/0x1190 [drm]
>  __drm_fb_helper_initial_config_and_unlock+0x5c/0x4a4 [drm_kms_helper]
>  drm_fb_helper_initial_config+0x54/0x6c [drm_kms_helper]
>  drm_fbdev_client_hotplug+0xd0/0x140 [drm_kms_helper]
>  drm_fbdev_generic_setup+0x90/0x154 [drm_kms_helper]
>  dcss_kms_attach+0x1c8/0x254 [imx_dcss]
>  dcss_drv_platform_probe+0x90/0xfc [imx_dcss]
>  platform_probe+0x70/0xcc
>  really_probe+0xc4/0x2e0
>  __driver_probe_device+0x80/0xf0
>  driver_probe_device+0xe0/0x164
>  __device_attach_driver+0xc0/0x13c
>  bus_for_each_drv+0x84/0xe0
>  __device_attach+0xa4/0x1a0
>  device_initial_probe+0x1c/0x30
>  bus_probe_device+0xa4/0xb0
>  deferred_probe_work_func+0x90/0xd0
>  process_one_work+0x200/0x474
>  worker_thread+0x74/0x43c
>  kthread+0xfc/0x110
>  ret_from_fork+0x10/0x20
> ---[ end trace  ]---
> 
> Reported-by: Laurentiu Palcu 
> Fixes: c8268795c9a9 ("drm/probe-helper: enable and disable HPD on connectors")
> Signed-off-by: Dmitry Baryshkov 
> ---
>  drivers/gpu/drm/drm_probe_helper.c | 110 +
>  1 file changed, 63 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_probe_helper.c 
> b/drivers/gpu/drm/drm_probe_helper.c
> index 7973f2589ced..ef919d95fea6 100644
> --- a/drivers/gpu/drm/drm_probe_helper.c
> +++ b/drivers/gpu/drm/drm_probe_helper.c
> @@ -222,6 +222,45 @@ drm_connector_mode_valid(struct drm_connector *connector,
>   return ret;
>  }
>  
> +static void drm_kms_helper_disable_hpd(struct drm_device *dev)
> +{
> + struct drm_connector *connector;
> + struct drm_connector_list_iter conn_iter;
> +
> + drm_connector_list_iter_begin(dev, _iter);
> + drm_for_each_connector_iter(connector, _iter) {
> + const struct drm_connector_helper_funcs *funcs =
> + connector->helper_private;
> +
> + if (funcs && funcs->disable_hpd)
> + funcs->disable_hpd(connector);
> + }
> + drm_connector_list_iter_end(_iter);
> +}
> +
> +static bool drm_kms_helper_enable_hpd(struct drm_device *dev)
> +{
> + bool poll = false;
> + struct drm_connector *connector;
> + struct drm_connector_list_iter conn_iter;
> +
> + drm_connector_list_iter_begin(dev, _iter);
> + drm_for_

Re: [PATCH 2/2] drm/imx/dcss: Don't call dev_set_drvdata(..., NULL);

[Laurentiu Palcu]

Hi,

On Fri, Dec 30, 2022 at 02:00:25PM +0100, Uwe Kleine-König wrote:
> The driver core takes care about removing driver data, so this can be
> dropped from the driver.
> 
> Signed-off-by: Uwe Kleine-König 
Reviewed-by: Laurentiu Palcu 

Pushed to drm-misc-next.

Thanks,
laurentiu

> ---
>  drivers/gpu/drm/imx/dcss/dcss-drv.c | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-drv.c 
> b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> index 5c88eecf2ce0..3d5402193a11 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-drv.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> @@ -74,8 +74,6 @@ static int dcss_drv_platform_probe(struct platform_device 
> *pdev)
>  dcss_shutoff:
>   dcss_dev_destroy(mdrv->dcss);
>  
> - dev_set_drvdata(dev, NULL);
> -
>  err:
>   kfree(mdrv);
>   return err;
> @@ -88,8 +86,6 @@ static int dcss_drv_platform_remove(struct platform_device 
> *pdev)
>   dcss_kms_detach(mdrv->kms);
>   dcss_dev_destroy(mdrv->dcss);
>  
> - dev_set_drvdata(>dev, NULL);
> -
>   kfree(mdrv);
>  
>   return 0;
> -- 
> 2.38.1
> 

Re: [PATCH 1/2] drm/imx/dcss: Drop if blocks with always false condition

[Laurentiu Palcu]

Hi,

On Fri, Dec 30, 2022 at 02:00:24PM +0100, Uwe Kleine-König wrote:
> dcss_drv_platform_remove() is only called for a device after
> dcss_drv_platform_probe() returned 0. In that case dev_set_drvdata() was
> called with a non-NULL value and so dev_get_drvdata() won't return NULL.
> 
> Signed-off-by: Uwe Kleine-König 
Reviewed-by: Laurentiu Palcu 

Pushed to drm-misc-next.

Thanks,
laurentiu

> ---
>  drivers/gpu/drm/imx/dcss/dcss-drv.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-drv.c 
> b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> index 1c70f70247f6..5c88eecf2ce0 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-drv.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> @@ -85,9 +85,6 @@ static int dcss_drv_platform_remove(struct platform_device 
> *pdev)
>  {
>   struct dcss_drv *mdrv = dev_get_drvdata(>dev);
>  
> - if (!mdrv)
> - return 0;
> -
>   dcss_kms_detach(mdrv->kms);
>   dcss_dev_destroy(mdrv->dcss);
>  
> -- 
> 2.38.1
> 

Re: [PATCH v3 0/7] drm/bridge_connector: perform HPD enablement automatically

[Laurentiu Palcu]

Hi,

On Mon, Jan 09, 2023 at 10:26:28PM +0200, Dmitry Baryshkov wrote:
> Hi,
> 
> On 09/01/2023 18:21, Laurentiu Palcu wrote:
> > Hi Dmitry,
> > 
> > It looks like there are some issues with this patchset... :/ I just
> > fetched the drm-tip and, with these patches included, the "Hot plug
> > detection already enabled" warning is back for i.MX DCSS.
> 
> Could you please provide a backtrace?

Sure, see below:

[ cut here ]
Hot plug detection already enabled
WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_bridge.c:1257 
drm_bridge_hpd_enable+0x94/0x9c [drm]
Modules linked in: videobuf2_memops snd_soc_simple_card 
snd_soc_simple_card_utils fsl_imx8_ddr_perf videobuf2_common snd_soc_imx_spdif 
adv7511 etnaviv imx8m_ddrc imx_dcss mc cec nwl_dsi gov
CPU: 2 PID: 9 Comm: kworker/u8:0 Not tainted 6.2.0-rc2-15208-g25b283acd578 #6
Hardware name: NXP i.MX8MQ EVK (DT)
Workqueue: events_unbound deferred_probe_work_func
pstate: 6005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : drm_bridge_hpd_enable+0x94/0x9c [drm]
lr : drm_bridge_hpd_enable+0x94/0x9c [drm]
sp : 89ef3740
x29: 89ef3740 x28: 09331f00 x27: 1000
x26: 0020 x25: 81148ed8 x24: 0a8fe000
x23: fffd x22: 05086348 x21: 81133ee0
x20: 0550d800 x19: 05086288 x18: 0006
x17:  x16: 896ef008 x15: 972891004260
x14: 2a1403e19400 x13: 972891004260 x12: 2a1403e19400
x11: 7100385f29400801 x10: 0aa0 x9 : 88112744
x8 : 00250b00 x7 : 0003 x6 : 0011
x5 :  x4 : bd986a48 x3 : 0001
x2 :  x1 :  x0 : 0025
Call trace:
 drm_bridge_hpd_enable+0x94/0x9c [drm]
 drm_bridge_connector_enable_hpd+0x2c/0x3c [drm_kms_helper]
 drm_kms_helper_poll_enable+0x94/0x10c [drm_kms_helper]
 drm_helper_probe_single_connector_modes+0x1a8/0x510 [drm_kms_helper]
 drm_client_modeset_probe+0x204/0x1190 [drm]
 __drm_fb_helper_initial_config_and_unlock+0x5c/0x4a4 [drm_kms_helper]
 drm_fb_helper_initial_config+0x54/0x6c [drm_kms_helper]
 drm_fbdev_client_hotplug+0xd0/0x140 [drm_kms_helper]
 drm_fbdev_generic_setup+0x90/0x154 [drm_kms_helper]
 dcss_kms_attach+0x1c8/0x254 [imx_dcss]
 dcss_drv_platform_probe+0x90/0xfc [imx_dcss]
 platform_probe+0x70/0xcc
 really_probe+0xc4/0x2e0
 __driver_probe_device+0x80/0xf0
 driver_probe_device+0xe0/0x164
 __device_attach_driver+0xc0/0x13c
 bus_for_each_drv+0x84/0xe0
 __device_attach+0xa4/0x1a0
 device_initial_probe+0x1c/0x30
 bus_probe_device+0xa4/0xb0
 deferred_probe_work_func+0x90/0xd0
 process_one_work+0x200/0x474
 worker_thread+0x74/0x43c
 kthread+0xfc/0x110
 ret_from_fork+0x10/0x20
---[ end trace  ]---

Cheers,
Laurentiu

> 
> > 
> > After a short investigation, it seems that we end up calling
> > drm_bridge_hpd_enable() from both drm_kms_helper_poll_init() and
> > drm_fbdev_generic_setup(), hence the warning.
> > 
> > There are drivers using the drm_bridge_connector API that also call
> > drm_kms_helper_poll_init() followed by drm_fbdev_generic_setup(). So,
> > they might experience the same behavior, unless I'm missing something...
> > :/
> > 
> > Also, even if drm_fbdev_generic_setup() is not called in the driver
> > initialization, the warning will still appear the first time the
> > GETCONNECTOR ioctl is called, because that'll call
> > drm_helper_probe_single_connector_modes() helper which will eventually
> > call drm_bridge_hpd_enable().
> > 
> > Any idea?
> > 
> > Cheers,
> > Laurentiu
> > 
> > On Wed, Nov 02, 2022 at 09:06:58PM +0300, Dmitry Baryshkov wrote:
> > >  From all the drivers using drm_bridge_connector only iMX/dcss and OMAP
> > > DRM driver do a proper work of calling
> > > drm_bridge_connector_en/disable_hpd() in right places. Rather than
> > > teaching each and every driver how to properly handle
> > > drm_bridge_connector's HPD, make that automatic.
> > > 
> > > Add two additional drm_connector helper funcs: enable_hpd() and
> > > disable_hpd(). Make drm_kms_helper_poll_* functions call them (as this
> > > is the time where the drm_bridge_connector's functions are called by the
> > > drivers too).
> > > 
> > > Changes since v2:
> > >   - Fixed a typo in the commit message of the second patch.
> > > 
> > > Changes since v1:
> > >   - Rebased on top of v6.1-rc1
> > >   - Removed the drm_bridge_connector_enable_hpd() from
> > > drm_bridge_connector_init()
> > >   - Removed extra underscore prefix from
> > > drm_bridge_connector_en/disable_hp

Re: [PATCH v3 0/7] drm/bridge_connector: perform HPD enablement automatically

[Laurentiu Palcu]

Hi Dmitry,

It looks like there are some issues with this patchset... :/ I just
fetched the drm-tip and, with these patches included, the "Hot plug
detection already enabled" warning is back for i.MX DCSS.

After a short investigation, it seems that we end up calling
drm_bridge_hpd_enable() from both drm_kms_helper_poll_init() and
drm_fbdev_generic_setup(), hence the warning.

There are drivers using the drm_bridge_connector API that also call
drm_kms_helper_poll_init() followed by drm_fbdev_generic_setup(). So,
they might experience the same behavior, unless I'm missing something...
:/

Also, even if drm_fbdev_generic_setup() is not called in the driver
initialization, the warning will still appear the first time the
GETCONNECTOR ioctl is called, because that'll call
drm_helper_probe_single_connector_modes() helper which will eventually
call drm_bridge_hpd_enable().

Any idea?

Cheers,
Laurentiu

On Wed, Nov 02, 2022 at 09:06:58PM +0300, Dmitry Baryshkov wrote:
> From all the drivers using drm_bridge_connector only iMX/dcss and OMAP
> DRM driver do a proper work of calling
> drm_bridge_connector_en/disable_hpd() in right places. Rather than
> teaching each and every driver how to properly handle
> drm_bridge_connector's HPD, make that automatic.
> 
> Add two additional drm_connector helper funcs: enable_hpd() and
> disable_hpd(). Make drm_kms_helper_poll_* functions call them (as this
> is the time where the drm_bridge_connector's functions are called by the
> drivers too).
> 
> Changes since v2:
>  - Fixed a typo in the commit message of the second patch.
> 
> Changes since v1:
>  - Rebased on top of v6.1-rc1
>  - Removed the drm_bridge_connector_enable_hpd() from
>drm_bridge_connector_init()
>  - Removed extra underscore prefix from
>drm_bridge_connector_en/disable_hpd() helpers
> 
> Dmitry Baryshkov (7):
>   drm/poll-helper: merge drm_kms_helper_poll_disable() and _fini()
>   drm/probe-helper: enable and disable HPD on connectors
>   drm/bridge_connector: rely on drm_kms_helper_poll_* for HPD enablement
>   drm/imx/dcss: stop using drm_bridge_connector_en/disable_hpd()
>   drm/msm/hdmi: stop using drm_bridge_connector_en/disable_hpd()
>   drm/omap: stop using drm_bridge_connector_en/disable_hpd()
>   drm/bridge_connector: drop drm_bridge_connector_en/disable_hpd()
> 
>  drivers/gpu/drm/drm_bridge_connector.c   | 27 +++-
>  drivers/gpu/drm/drm_probe_helper.c   | 40 ++-
>  drivers/gpu/drm/imx/dcss/dcss-dev.c  |  4 ---
>  drivers/gpu/drm/imx/dcss/dcss-kms.c  |  2 --
>  drivers/gpu/drm/msm/hdmi/hdmi.c  |  2 --
>  drivers/gpu/drm/omapdrm/omap_drv.c   | 41 
>  include/drm/drm_bridge_connector.h   |  2 --
>  include/drm/drm_modeset_helper_vtables.h | 22 +
>  8 files changed, 59 insertions(+), 81 deletions(-)
> 
> -- 
> 2.35.1
> 

Re: [PATCH 10/26] drm: imx/dcss: Remove #ifdef guards for PM related functions

[Laurentiu Palcu]

Hi Paul,

On Mon, Nov 07, 2022 at 05:50:50PM +, Paul Cercueil wrote:
> Use the EXPORT_GPL_DEV_PM_OPS() and pm_ptr() macros to handle the PM
> callbacks.
> 
> These macros allow the PM functions to be automatically dropped by the
> compiler when CONFIG_PM is disabled, without having to use #ifdef
> guards.
> 
> This has the advantage of always compiling these functions in,
> independently of any Kconfig option. Thanks to that, bugs and other
> regressions are subsequently easier to catch.
> 
> Signed-off-by: Paul Cercueil 

Reviewed-by: Laurentiu Palcu 
Tested-by: Laurentiu Palcu 

Thanks,
Laurentiu

> ---
> Cc: Laurentiu Palcu 
> Cc: Lucas Stach 
> Cc: Philipp Zabel 
> Cc: Shawn Guo 
> Cc: Sascha Hauer 
> Cc: Pengutronix Kernel Team 
> Cc: Fabio Estevam 
> Cc: NXP Linux Team 
> Cc: linux-arm-ker...@lists.infradead.org
> ---
>  drivers/gpu/drm/imx/dcss/dcss-dev.c | 17 +
>  drivers/gpu/drm/imx/dcss/dcss-dev.h |  7 +++
>  drivers/gpu/drm/imx/dcss/dcss-drv.c |  8 +---
>  3 files changed, 13 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
> b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> index 3f5750cc2673..66d9233ffb98 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> @@ -249,8 +249,7 @@ void dcss_dev_destroy(struct dcss_dev *dcss)
>   kfree(dcss);
>  }
>  
> -#ifdef CONFIG_PM_SLEEP
> -int dcss_dev_suspend(struct device *dev)
> +static int dcss_dev_suspend(struct device *dev)
>  {
>   struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
>   struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
> @@ -273,7 +272,7 @@ int dcss_dev_suspend(struct device *dev)
>   return 0;
>  }
>  
> -int dcss_dev_resume(struct device *dev)
> +static int dcss_dev_resume(struct device *dev)
>  {
>   struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
>   struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
> @@ -296,10 +295,8 @@ int dcss_dev_resume(struct device *dev)
>  
>   return 0;
>  }
> -#endif /* CONFIG_PM_SLEEP */
>  
> -#ifdef CONFIG_PM
> -int dcss_dev_runtime_suspend(struct device *dev)
> +static int dcss_dev_runtime_suspend(struct device *dev)
>  {
>   struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
>   int ret;
> @@ -313,7 +310,7 @@ int dcss_dev_runtime_suspend(struct device *dev)
>   return 0;
>  }
>  
> -int dcss_dev_runtime_resume(struct device *dev)
> +static int dcss_dev_runtime_resume(struct device *dev)
>  {
>   struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
>  
> @@ -325,4 +322,8 @@ int dcss_dev_runtime_resume(struct device *dev)
>  
>   return 0;
>  }
> -#endif /* CONFIG_PM */
> +
> +EXPORT_GPL_DEV_PM_OPS(dcss_dev_pm_ops) = {
> + RUNTIME_PM_OPS(dcss_dev_runtime_suspend, dcss_dev_runtime_resume, NULL)
> + SYSTEM_SLEEP_PM_OPS(dcss_dev_suspend, dcss_dev_resume)
> +};
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.h 
> b/drivers/gpu/drm/imx/dcss/dcss-dev.h
> index 1e582270c6ea..f27b87c09599 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-dev.h
> +++ b/drivers/gpu/drm/imx/dcss/dcss-dev.h
> @@ -9,6 +9,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  #define SET  0x04
> @@ -95,13 +96,11 @@ struct dcss_dev *dcss_drv_dev_to_dcss(struct device *dev);
>  struct drm_device *dcss_drv_dev_to_drm(struct device *dev);
>  struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output);
>  void dcss_dev_destroy(struct dcss_dev *dcss);
> -int dcss_dev_runtime_suspend(struct device *dev);
> -int dcss_dev_runtime_resume(struct device *dev);
> -int dcss_dev_suspend(struct device *dev);
> -int dcss_dev_resume(struct device *dev);
>  void dcss_enable_dtg_and_ss(struct dcss_dev *dcss);
>  void dcss_disable_dtg_and_ss(struct dcss_dev *dcss);
>  
> +extern const struct dev_pm_ops dcss_dev_pm_ops;
> +
>  /* BLKCTL */
>  int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long blkctl_base);
>  void dcss_blkctl_cfg(struct dcss_blkctl *blkctl);
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-drv.c 
> b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> index 1c70f70247f6..431510bd811b 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-drv.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-drv.c
> @@ -117,19 +117,13 @@ static const struct of_device_id dcss_of_match[] = {
>  
>  MODULE_DEVICE_TABLE(of, dcss_of_match);
>  
> -static const struct dev_pm_ops dcss_dev_pm = {
> - SET_SYSTEM_SLEEP_PM_OPS(dcss_dev_suspend, dcss_dev_resume)
> - SET_RUNTIME_PM_OPS(dcss_dev_runtime_suspend,
> -dcss_dev_runtime_resume, NULL)
> -};
> -
>  static struct platform_driver dcss_platform_driver = {
>   .probe  = dcss_drv_platform_probe,
>   .remove = dcss_drv_platform_remove,
>   .driver = {
>   .name = "imx-dcss",
>   .of_match_table = dcss_of_match,
> - .pm = _dev_pm,
> + .pm = pm_ptr(_dev_pm_ops),
>   },
>  };
>  
> -- 
> 2.35.1
> 

Re: [PATCH] drm/imx/dcss: get rid of HPD warning message

[Laurentiu Palcu]

On Thu, Jul 21, 2022 at 03:25:02PM +0300, Laurent Pinchart wrote:
> Hi Laurentiu,
> 
> Thank you for the patch.
> 
> On Thu, Jul 21, 2022 at 03:09:12PM +0300, Laurentiu Palcu wrote:
> > When DCSS + MIPI_DSI is used, and the last bridge in the chain supports
> > HPD, we can see a "Hot plug detection already enabled" warning stack
> > trace dump that's thrown when DCSS is initialized.
> > 
> > The problem appeared when HPD was enabled by default in the
> > bridge_connector initialization, which made the
> > drm_bridge_connector_enable_hpd() call, in DCSS init path, redundant.
> > So, let's remove that call.
> > 
> > Fixes: 09077bc311658 ("drm/bridge_connector: enable HPD by default if 
> > supported")
> > Signed-off-by: Laurentiu Palcu 
> 
> Reviewed-by: Laurent Pinchart 

Applied to drm-misc/drm-misc-fixes.

Thanks,
laurentiu

[PATCH] drm/imx/dcss: get rid of HPD warning message

[Laurentiu Palcu]

When DCSS + MIPI_DSI is used, and the last bridge in the chain supports
HPD, we can see a "Hot plug detection already enabled" warning stack
trace dump that's thrown when DCSS is initialized.

The problem appeared when HPD was enabled by default in the
bridge_connector initialization, which made the
drm_bridge_connector_enable_hpd() call, in DCSS init path, redundant.
So, let's remove that call.

Fixes: 09077bc311658 ("drm/bridge_connector: enable HPD by default if 
supported")
Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/imx/dcss/dcss-kms.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
b/drivers/gpu/drm/imx/dcss/dcss-kms.c
index 9b84df34a6a12..8cf3352d88582 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
@@ -142,8 +142,6 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
 
drm_kms_helper_poll_init(drm);
 
-   drm_bridge_connector_enable_hpd(kms->connector);
-
ret = drm_dev_register(drm, 0);
if (ret)
goto cleanup_crtc;
-- 
2.17.1

Re: [PATCH v2] drm/imx/dcss: Add missing of_node_put() in fail path

[Laurentiu Palcu]

Hi,

On Thu, Jul 14, 2022 at 04:13:37PM +0800, Liang He wrote:
> In dcss_dev_create() and dcss_dev_destroy(), we should call of_node_put()
> in fail path or before the dcss's destroy as of_graph_get_port_by_id() has
> increased the refcount.
>  
> Fixes: 9021c317b770 ("drm/imx: Add initial support for DCSS on iMX8MQ")
> Signed-off-by: Liang He 
Reviewed-by: Laurentiu Palcu 

Applied to drm-misc-fixes.

Thanks,
Laurentiu

> ---
>  changelog:
> 
>  v2: add of_node_put() in dcss_dev_destroy() advised by Laurentiu
>  v1: only fix bug in dcss_dev_create().
> 
>  v1 link: https://lore.kernel.org/all/20220707023214.307451-1-win...@126.com/
> 
> 
>  drivers/gpu/drm/imx/dcss/dcss-dev.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
> b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> index c849533ca83e..3f5750cc2673 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> @@ -207,6 +207,7 @@ struct dcss_dev *dcss_dev_create(struct device *dev, bool 
> hdmi_output)
>  
>   ret = dcss_submodules_init(dcss);
>   if (ret) {
> + of_node_put(dcss->of_port);
>   dev_err(dev, "submodules initialization failed\n");
>   goto clks_err;
>   }
> @@ -237,6 +238,8 @@ void dcss_dev_destroy(struct dcss_dev *dcss)
>   dcss_clocks_disable(dcss);
>   }
>  
> + of_node_put(dcss->of_port);
> +
>   pm_runtime_disable(dcss->dev);
>  
>   dcss_submodules_stop(dcss);
> -- 
> 2.25.1
> 

Re: [PATCH] drm/imx/dcss: Add missing of_node_put() in fail path

[Laurentiu Palcu]

Hi Liang,

Thanks for the patch.

The patch is ok but, since you're at it, maybe add of_node_put() in the
dcss_dev_destroy() too?

Thanks,
laurentiu

On Thu, Jul 07, 2022 at 10:32:14AM +0800, Liang He wrote:
> In dcss_dev_create(), we should call of_node_put() in fail path for
> of_graph_get_port_by_id() which will increase the refcount.
> 
> Fixes: 9021c317b770 ("drm/imx: Add initial support for DCSS on iMX8MQ")
> Signed-off-by: Liang He 
> ---
>  drivers/gpu/drm/imx/dcss/dcss-dev.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
> b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> index c849533ca83e..a99141538621 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> @@ -207,6 +207,7 @@ struct dcss_dev *dcss_dev_create(struct device *dev, bool 
> hdmi_output)
>  
>   ret = dcss_submodules_init(dcss);
>   if (ret) {
> + of_node_put(dcss->of_port);
>   dev_err(dev, "submodules initialization failed\n");
>   goto clks_err;
>   }
> -- 
> 2.25.1
> 

Re: [PATCH] drm/imx/dcss: i.MX8MQ DCSS select DRM_GEM_CMA_HELPER

[Laurentiu Palcu]

Hi Rudi,

On Wed, Feb 16, 2022 at 09:22:28PM +, Rudi Heitbaum wrote:
> Without DRM_GEM_CMA_HELPER i.MX8MQ DCSS won't build. This needs to be
> there.
> 
> Signed-off-by: Rudi Heitbaum 
Reviewed-by: Laurentiu Palcu 

...and pushed to drm-misc-fixes.

Thanks,
laurentiu

> ---
>  drivers/gpu/drm/imx/dcss/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/Kconfig 
> b/drivers/gpu/drm/imx/dcss/Kconfig
> index 7374f1952762..5c2b2277afbf 100644
> --- a/drivers/gpu/drm/imx/dcss/Kconfig
> +++ b/drivers/gpu/drm/imx/dcss/Kconfig
> @@ -2,6 +2,7 @@ config DRM_IMX_DCSS
>   tristate "i.MX8MQ DCSS"
>   select IMX_IRQSTEER
>   select DRM_KMS_HELPER
> + select DRM_GEM_CMA_HELPER
>   select VIDEOMODE_HELPERS
>   depends on DRM && ARCH_MXC && ARM64
>   help
> -- 
> 2.25.1
> 

Re: [PATCH 2/2] drm/imx/dcss: select DRM_KMS_HELPER

[Laurentiu Palcu]

Hi Lucas,

On Sat, Dec 11, 2021 at 11:18:48PM +0100, Lucas Stach wrote:
> DCSS can not be built without the DRM_KMS_HELPERs being available.
> Select this symbol to disallow this invalid configuration.
> 
> Signed-off-by: Lucas Stach 
Reviewed-by: Laurentiu Palcu 

Can you also push these 2 patches to drm-misc, when you have some time?

Thanks,
laurentiu

> ---
>  drivers/gpu/drm/imx/dcss/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/Kconfig 
> b/drivers/gpu/drm/imx/dcss/Kconfig
> index 2b17a964ff05..4c2158dc5540 100644
> --- a/drivers/gpu/drm/imx/dcss/Kconfig
> +++ b/drivers/gpu/drm/imx/dcss/Kconfig
> @@ -1,6 +1,7 @@
>  config DRM_IMX_DCSS
>   tristate "i.MX8MQ DCSS"
>   select IMX_IRQSTEER
> + select DRM_KMS_HELPER
>   select DRM_KMS_CMA_HELPER
>   select VIDEOMODE_HELPERS
>   depends on DRM && ARCH_MXC && ARM64
> -- 
> 2.31.1
> 

Re: [PATCH 1/2] drm/imx/dcss: add missing drm_bridge.h include

[Laurentiu Palcu]

Hi Lucas,

On Sat, Dec 11, 2021 at 11:18:47PM +0100, Lucas Stach wrote:
> This has been pulled in via some other include before, which is no
> longer true.
> 
> Signed-off-by: Lucas Stach 
> ---
Reviewed-by: Laurentiu Palcu 

>  drivers/gpu/drm/imx/dcss/dcss-kms.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
> b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> index 9b84df34a6a1..96a9517021fe 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> @@ -5,6 +5,7 @@
>  
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> -- 
> 2.31.1
> 

Re: [PATCH v2 09/22] drm/imx: Don't set struct drm_device.irq_enabled

[Laurentiu Palcu]

Hi Thomas,

On Tue, Jun 22, 2021 at 04:09:49PM +0200, Thomas Zimmermann wrote:
> The field drm_device.irq_enabled is only used by legacy drivers
> with userspace modesetting. Don't set it in imx.
> 
> Signed-off-by: Thomas Zimmermann 
> ---
>  drivers/gpu/drm/imx/dcss/dcss-kms.c |  3 ---

Not sure if it's worth the effort but, since DCSS is a completely
self-contained driver, maybe it would be good to split this patch in 2
as well.

Anyway, for DCSS bit:

Acked-by: Laurentiu Palcu 

Thanks,
laurentiu

>  drivers/gpu/drm/imx/imx-drm-core.c  | 11 ---
>  2 files changed, 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
> b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> index 37ae68a7fba5..917834b1c80e 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> @@ -133,8 +133,6 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev 
> *dcss)
>   if (ret)
>   goto cleanup_mode_config;
>  
> - drm->irq_enabled = true;
> -
>   ret = dcss_kms_bridge_connector_init(kms);
>   if (ret)
>   goto cleanup_mode_config;
> @@ -178,7 +176,6 @@ void dcss_kms_detach(struct dcss_kms_dev *kms)
>   drm_kms_helper_poll_fini(drm);
>   drm_atomic_helper_shutdown(drm);
>   drm_crtc_vblank_off(>crtc.base);
> - drm->irq_enabled = false;
>   drm_mode_config_cleanup(drm);
>   dcss_crtc_deinit(>crtc, drm);
>   drm->dev_private = NULL;
> diff --git a/drivers/gpu/drm/imx/imx-drm-core.c 
> b/drivers/gpu/drm/imx/imx-drm-core.c
> index 76819a8ac37f..9558e9e1b431 100644
> --- a/drivers/gpu/drm/imx/imx-drm-core.c
> +++ b/drivers/gpu/drm/imx/imx-drm-core.c
> @@ -207,17 +207,6 @@ static int imx_drm_bind(struct device *dev)
>   if (IS_ERR(drm))
>   return PTR_ERR(drm);
>  
> - /*
> -  * enable drm irq mode.
> -  * - with irq_enabled = true, we can use the vblank feature.
> -  *
> -  * P.S. note that we wouldn't use drm irq handler but
> -  *  just specific driver own one instead because
> -  *  drm framework supports only one irq handler and
> -  *  drivers can well take care of their interrupts
> -  */
> - drm->irq_enabled = true;
> -
>   /*
>* set max width and height as default value(4096x4096).
>* this value would be used to check framebuffer size limitation
> -- 
> 2.32.0
> 

Re: [PATCH v9 6/6] MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver

[Laurentiu Palcu]

Hi,

On Mon, Mar 29, 2021 at 01:57:26PM +0800, Liu Ying wrote:
> Add myself as the maintainer of the i.MX8qxp DPU DRM driver.
> 
> Signed-off-by: Liu Ying 

Acked-by: Laurentiu Palcu 

Thanks,
laurentiu

> ---
> v8->v9:
> * No change.
> 
> v7->v8:
> * No change.
> 
> v6->v7:
> * No change.
> 
> v5->v6:
> * No change.
> 
> v4->v5:
> * No change.
> 
> v3->v4:
> * No change.
> 
> v2->v3:
> * No change.
> 
> v1->v2:
> * No change.
> 
>  MAINTAINERS | 9 +
>  1 file changed, 9 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a247285..ec82d42 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5946,6 +5946,15 @@ F: Documentation/devicetree/bindings/display/imx/
>  F:   drivers/gpu/drm/imx/
>  F:   drivers/gpu/ipu-v3/
>  
> +DRM DRIVERS FOR FREESCALE i.MX8QXP
> +M:   Liu Ying 
> +L:   dri-devel@lists.freedesktop.org
> +S:   Maintained
> +F:   Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
> +F:   Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
> +F:   Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
> +F:   drivers/gpu/drm/imx/dpu/
> +
>  DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets)
>  M:   Patrik Jakobsson 
>  L:   dri-devel@lists.freedesktop.org
> -- 
> 2.7.4
> 
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Re: [PATCH] drm/imx/dcss: Use device_get_match_data()

[Laurentiu Palcu]

Hi Fabio,

On Mon, Mar 15, 2021 at 09:38:11AM -0300, Fabio Estevam wrote:
> The retrieval of driver data can be a bit simplified by using
> device_get_match_data(), so switch to it.
> 
> Signed-off-by: Fabio Estevam 

Reviewed-by: Laurentiu Palcu 

> ---
>  drivers/gpu/drm/imx/dcss/dcss-dev.c | 9 +
>  1 file changed, 1 insertion(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
> b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> index c849533ca83e..de0f02de94c4 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
> @@ -168,13 +168,6 @@ struct dcss_dev *dcss_dev_create(struct device *dev, 
> bool hdmi_output)
>   int ret;
>   struct resource *res;
>   struct dcss_dev *dcss;
> - const struct dcss_type_data *devtype;
> -
> - devtype = of_device_get_match_data(dev);
> - if (!devtype) {
> - dev_err(dev, "no device match found\n");
> - return ERR_PTR(-ENODEV);
> - }
>  
>   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>   if (!res) {
> @@ -187,7 +180,7 @@ struct dcss_dev *dcss_dev_create(struct device *dev, bool 
> hdmi_output)
>   return ERR_PTR(-ENOMEM);
>  
>   dcss->dev = dev;
> - dcss->devtype = devtype;
> + dcss->devtype = device_get_match_data(dev);
>   dcss->hdmi_output = hdmi_output;
>  
>   ret = dcss_clks_init(dcss);
> -- 
> 2.17.1
> 
___
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Re: [PATCH v8 5/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM

[Laurentiu Palcu]

Hi Liu Ying,

One comment below.

On Tue, Mar 02, 2021 at 02:33:15PM +0800, Liu Ying wrote:
> This patch introduces i.MX8qm/qxp Display Processing Unit(DPU) DRM support.
> 
> DPU is comprised of two main components that include a blit engine for
> 2D graphics accelerations(with composition support) and a display controller
> for display output processing, as well as a command sequencer.  Outside of
> DPU, optional prefetch engines, a.k.a, Prefetch Resolve Gasket(PRG) and
> Display Prefetch Resolve(DPR), can fetch data from memory prior to some DPU
> fetchunits of blit engine and display controller.  The prefetch engines
> support reading linear formats and resolving Vivante GPU tile formats.
> 
> This patch adds kernel modesetting support for the display controller part.
> The driver supports two CRTCs per display controller, planes backed by
> four fetchunits(decode0/1, fetchlayer, fetchwarp), fetchunit allocation
> logic for the two CRTCs, prefetch engines(with tile resolving supported),
> plane upscaling/deinterlacing/yuv2rgb CSC/alpha blending and CRTC gamma
> correction.  The registers of the controller is accessed without command
> sequencer involved, instead just by using CPU.
> 
> Reference manual can be found at:
> https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
> 
> Signed-off-by: Liu Ying 
> ---
> Laurentiu, I see your R-b tag on this patch of v7.
> As this patch is changed in v8, can you please help review and maybe add your
> R-b tag again?
> 
> v7->v8:
> * Update dpu_plane_atomic_check() and dpu_plane_atomic_update(), due to DRM
>   plane helper functions API change(atomic_check and atomic_update) from DRM
>   atomic core.  Also, rename plane->state variables and relevant DPU plane
>   state variables in those two functions to reflect they are new states, like
>   the patch 'drm: Rename plane->state variables in atomic update and disable'
>   recently landed in drm-misc-next.
> * Replace drm_gem_fb_prepare_fb() with drm_gem_plane_helper_prepare_fb(),
>   due to DRM core API change.
> * Use 256byte DPR burst length for GPU standard tile and 128byte DPR burst
>   length for 32bpp GPU super tile to align with the latest version of internal
>   HW documention.
> 
> v6->v7:
> * Fix return value of dpu_get_irqs() if platform_get_irq() fails. (Laurentiu)
> * Use the function array dpu_irq_handler[] to store individual DPU irq 
> handlers.
>   (Laurentiu)
> * Call get/put() hooks directly to get/put DPU fetchunits for DPU plane 
> groups.
>   (Laurentiu)
> * Shorten the names of individual DPU irq handlers by using DPU unit abbrev
>   names to make writing dpu_irq_handler[] easier.
> 
> v5->v6:
> * Do not use macros where possible. (Laurentiu)
> * Break dpu_plane_atomic_check() into some smaller functions. (Laurentiu)
> * Address some minor comments from Laurentiu.
> * Add dpu_crtc_err() helper marco to tell dmesg which CRTC generates error.
> * Drop calling dev_set_drvdata() from dpu_drm_bind/unbind() as it is done
>   in dpu_drm_probe().
> * Some trivial tweaks.
> 
> v4->v5:
> * Rebase up onto the latest drm-misc-next branch and remove the hook to
>   drm_atomic_helper_legacy_gamma_set(), because it was dropped by the newly
>   landed commit 'drm: automatic legacy gamma support'.
> * Remove a redundant blank line from dpu_plane_atomic_update().
> 
> v3->v4:
> * No change.
> 
> v2->v3:
> * Fix build warnings Reported-by: kernel test robot .
> * Drop build dependency on IMX_SCU, as dummy SCU functions have been added in
>   header files by the patch 'firmware: imx: add dummy functions' which has
>   landed in linux-next/master branch.
> 
> v1->v2:
> * Add compatible for i.MX8qm DPU, as this is tested with i.MX8qm LVDS 
> displays.
>   (Laurentiu)
> * Fix PRG burst size and stride. (Laurentiu)
> * Put 'ports' OF node to fix the bail-out logic in dpu_drm_probe(). 
> (Laurentiu)
> 
>  drivers/gpu/drm/imx/Kconfig   |1 +
>  drivers/gpu/drm/imx/Makefile  |1 +
>  drivers/gpu/drm/imx/dpu/Kconfig   |   10 +
>  drivers/gpu/drm/imx/dpu/Makefile  |   10 +
>  drivers/gpu/drm/imx/dpu/dpu-constframe.c  |  171 +
>  drivers/gpu/drm/imx/dpu/dpu-core.c| 1054 
> +
>  drivers/gpu/drm/imx/dpu/dpu-crtc.c|  967 ++
>  drivers/gpu/drm/imx/dpu/dpu-crtc.h|   66 ++
>  drivers/gpu/drm/imx/dpu/dpu-disengcfg.c   |  117 
>  drivers/gpu/drm/imx/dpu/dpu-dprc.c|  722 
>  drivers/gpu/drm/imx/dpu/dpu-dprc.h|   40 ++
>  drivers/gpu/drm/imx/dpu/dpu-drv.c |  292 
>  drivers/gpu/drm/imx/dpu/dpu-drv.h |   28 +
>  drivers/gpu/drm/imx/dpu/dpu-extdst.c  |  299 
>  drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c |  294 
>  drivers/gpu/drm/imx/dpu/dpu-fetcheco.c|  224 ++
>  drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c  |  154 +
>  drivers/gpu/drm/imx/dpu/dpu-fetchunit.c   |  609 +
>  

Re: [PATCH v6 5/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM

[Laurentiu Palcu]

Hi Liu Ying,

Just some minor comments below.

On Thu, Jan 21, 2021 at 03:14:22PM +0800, Liu Ying wrote:
> This patch introduces i.MX8qm/qxp Display Processing Unit(DPU) DRM support.
> 
> DPU is comprised of two main components that include a blit engine for
> 2D graphics accelerations(with composition support) and a display controller
> for display output processing, as well as a command sequencer.  Outside of
> DPU, optional prefetch engines, a.k.a, Prefetch Resolve Gasket(PRG) and
> Display Prefetch Resolve(DPR), can fetch data from memory prior to some DPU
> fetchunits of blit engine and display controller.  The prefetch engines
> support reading linear formats and resolving Vivante GPU tile formats.
> 
> This patch adds kernel modesetting support for the display controller part.
> The driver supports two CRTCs per display controller, planes backed by
> four fetchunits(decode0/1, fetchlayer, fetchwarp), fetchunit allocation
> logic for the two CRTCs, prefetch engines(with tile resolving supported),
> plane upscaling/deinterlacing/yuv2rgb CSC/alpha blending and CRTC gamma
> correction.  The registers of the controller is accessed without command
> sequencer involved, instead just by using CPU.
> 
> Reference manual can be found at:
> https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
> 
> Signed-off-by: Liu Ying 
> ---
> v5->v6:
> * Do not use macros where possible. (Laurentiu)
> * Break dpu_plane_atomic_check() into some smaller functions. (Laurentiu)
> * Address some minor comments from Laurentiu.
> * Add dpu_crtc_err() helper marco to tell dmesg which CRTC generates error.
> * Drop calling dev_set_drvdata() from dpu_drm_bind/unbind() as it is done
>   in dpu_drm_probe().
> * Some trivial tweaks.
> 
> v4->v5:
> * Rebase up onto the latest drm-misc-next branch and remove the hook to
>   drm_atomic_helper_legacy_gamma_set(), because it was dropped by the newly
>   landed commit 'drm: automatic legacy gamma support'.
> * Remove a redundant blank line from dpu_plane_atomic_update().
> 
> v3->v4:
> * No change.
> 
> v2->v3:
> * Fix build warnings Reported-by: kernel test robot .
> * Drop build dependency on IMX_SCU, as dummy SCU functions have been added in
>   header files by the patch 'firmware: imx: add dummy functions' which has
>   landed in linux-next/master branch.
> 
> v1->v2:
> * Add compatible for i.MX8qm DPU, as this is tested with i.MX8qm LVDS 
> displays.
>   (Laurentiu)
> * Fix PRG burst size and stride. (Laurentiu)
> * Put 'ports' OF node to fix the bail-out logic in dpu_drm_probe(). 
> (Laurentiu)
> 
>  drivers/gpu/drm/imx/Kconfig   |1 +
>  drivers/gpu/drm/imx/Makefile  |1 +
>  drivers/gpu/drm/imx/dpu/Kconfig   |   10 +
>  drivers/gpu/drm/imx/dpu/Makefile  |   10 +
>  drivers/gpu/drm/imx/dpu/dpu-constframe.c  |  171 +
>  drivers/gpu/drm/imx/dpu/dpu-core.c| 1094 
> +
>  drivers/gpu/drm/imx/dpu/dpu-crtc.c|  967 +
>  drivers/gpu/drm/imx/dpu/dpu-crtc.h|   66 ++
>  drivers/gpu/drm/imx/dpu/dpu-disengcfg.c   |  117 +++
>  drivers/gpu/drm/imx/dpu/dpu-dprc.c|  718 +++
>  drivers/gpu/drm/imx/dpu/dpu-dprc.h|   40 ++
>  drivers/gpu/drm/imx/dpu/dpu-drv.c |  292 
>  drivers/gpu/drm/imx/dpu/dpu-drv.h |   28 +
>  drivers/gpu/drm/imx/dpu/dpu-extdst.c  |  299 
>  drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c |  294 
>  drivers/gpu/drm/imx/dpu/dpu-fetcheco.c|  224 ++
>  drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c  |  154 
>  drivers/gpu/drm/imx/dpu/dpu-fetchunit.c   |  609 
>  drivers/gpu/drm/imx/dpu/dpu-fetchunit.h   |  191 +
>  drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c   |  250 +++
>  drivers/gpu/drm/imx/dpu/dpu-framegen.c|  395 +++
>  drivers/gpu/drm/imx/dpu/dpu-gammacor.c|  223 ++
>  drivers/gpu/drm/imx/dpu/dpu-hscaler.c |  275 
>  drivers/gpu/drm/imx/dpu/dpu-kms.c |  540 ++
>  drivers/gpu/drm/imx/dpu/dpu-kms.h |   23 +
>  drivers/gpu/drm/imx/dpu/dpu-layerblend.c  |  348 +
>  drivers/gpu/drm/imx/dpu/dpu-plane.c   |  799 +
>  drivers/gpu/drm/imx/dpu/dpu-plane.h   |   56 ++
>  drivers/gpu/drm/imx/dpu/dpu-prg.c |  433 
>  drivers/gpu/drm/imx/dpu/dpu-prg.h |   45 ++
>  drivers/gpu/drm/imx/dpu/dpu-prv.h |  233 ++
>  drivers/gpu/drm/imx/dpu/dpu-tcon.c|  250 +++
>  drivers/gpu/drm/imx/dpu/dpu-vscaler.c |  308 
>  drivers/gpu/drm/imx/dpu/dpu.h |  385 ++
>  34 files changed, 9849 insertions(+)
>  create mode 100644 drivers/gpu/drm/imx/dpu/Kconfig
>  create mode 100644 drivers/gpu/drm/imx/dpu/Makefile
>  create mode 100644 drivers/gpu/drm/imx/dpu/dpu-constframe.c
>  create mode 100644 drivers/gpu/drm/imx/dpu/dpu-core.c
>  create mode 100644 drivers/gpu/drm/imx/dpu/dpu-crtc.c
>  create mode 100644 

Re: [PATCH v5 5/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM

[Laurentiu Palcu]

Hi Liu Ying,

On Wed, Jan 20, 2021 at 04:42:50PM +0800, Liu Ying wrote:
> Hi Laurentiu,
>
> On Fri, 2021-01-15 at 19:27 +0200, Laurentiu Palcu wrote:
> > Hi Liu Ying,
> >
> > I promised I would have a second, more in-depth, look at this and I finally
> > managed to do it.
>
> Thanks.
>
> >
> > I have to admit it was a challenge. Partially because I'm not very familiar
> > with DPU but mostly because of the abundance of macros used. It's true, 
> > macros
> > make the code more compact. However they made the entire code hard to read,
> > as neither ctags nor cscope were able to cross-reference it properly, and I
> > fear it will be even harder to maintain in the long run... :/ For example,
> > trying to figure out where dpu_*_hw_init() functions were called from was no
> > easy task. Or dpu_*_put(). Or dpu_*_get(). :/
> >
> > Also, most of the macros are not in-line with Linux Kernel coding
> > style when it comes to macro usage: they affect control flow and some depend
> > on other local variables being already defined.
> >
> > The good news is most macros can be replaced with helper functions and it 
> > would
> > not add too much extra code.
>
> Ok, I'll remove macros where possible.
>
> >
> > More comments below.
>
> Please find feedbacks below.
>
> >
> > On Fri, Dec 18, 2020 at 11:23:52AM +0800, Liu Ying wrote:
> > > This patch introduces i.MX8qm/qxp Display Processing Unit(DPU) DRM 
> > > support.
> > >
> > > DPU is comprised of two main components that include a blit engine for
> > > 2D graphics accelerations(with composition support) and a display 
> > > controller
> > > for display output processing, as well as a command sequencer.  Outside of
> > > DPU, optional prefetch engines, a.k.a, Prefetch Resolve Gasket(PRG) and
> > > Display Prefetch Resolve(DPR), can fetch data from memory prior to some 
> > > DPU
> > > fetchunits of blit engine and display controller.  The prefetch engines
> > > support reading linear formats and resolving Vivante GPU tile formats.
> > >
> > > This patch adds kernel modesetting support for the display controller 
> > > part.
> > > The driver supports two CRTCs per display controller, planes backed by
> > > four fetchunits(decode0/1, fetchlayer, fetchwarp), fetchunit allocation
> > > logic for the two CRTCs, prefetch engines(with tile resolving supported),
> > > plane upscaling/deinterlacing/yuv2rgb CSC/alpha blending and CRTC gamma
> > > correction.  The registers of the controller is accessed without command
> > > sequencer involved, instead just by using CPU.
> > >
> > > Reference manual can be found at:
> > > https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
> > >
> > > Signed-off-by: Liu Ying 
> > > ---
> > > v4->v5:
> > > * Rebase up onto the latest drm-misc-next branch and remove the hook to
> > >   drm_atomic_helper_legacy_gamma_set(), because it was dropped by the 
> > > newly
> > >   landed commit 'drm: automatic legacy gamma support'.
> > > * Remove a redundant blank line from dpu_plane_atomic_update().
> > >
> > > v3->v4:
> > > * No change.
> > >
> > > v2->v3:
> > > * Fix build warnings Reported-by: kernel test robot .
> > > * Drop build dependency on IMX_SCU, as dummy SCU functions have been 
> > > added in
> > >   header files by the patch 'firmware: imx: add dummy functions' which has
> > >   landed in linux-next/master branch.
> > >
> > > v1->v2:
> > > * Add compatible for i.MX8qm DPU, as this is tested with i.MX8qm LVDS 
> > > displays.
> > >   (Laurentiu)
> > > * Fix PRG burst size and stride. (Laurentiu)
> > > * Put 'ports' OF node to fix the bail-out logic in dpu_drm_probe(). 
> > > (Laurentiu)
> > >
> > >  drivers/gpu/drm/imx/Kconfig   |   1 +
> > >  drivers/gpu/drm/imx/Makefile  |   1 +
> > >  drivers/gpu/drm/imx/dpu/Kconfig   |  10 +
> > >  drivers/gpu/drm/imx/dpu/Makefile  |  10 +
> > >  drivers/gpu/drm/imx/dpu/dpu-constframe.c  | 170 ++
> > >  drivers/gpu/drm/imx/dpu/dpu-core.c| 881 
> > > 
> > >  drivers/gpu/drm/imx/dpu/dpu-crtc.c| 925 
> > > ++
> > >  drivers/gpu/drm/imx/dpu/dpu-crtc.h|  62 ++
> > >  drivers/gpu/drm/imx/dpu/dpu-disengcfg.c   | 114 
> &g

Re: [PATCH v5 5/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM

[Laurentiu Palcu]

Hi Liu Ying,

I promised I would have a second, more in-depth, look at this and I finally
managed to do it.

I have to admit it was a challenge. Partially because I'm not very familiar
with DPU but mostly because of the abundance of macros used. It's true, macros
make the code more compact. However they made the entire code hard to read,
as neither ctags nor cscope were able to cross-reference it properly, and I
fear it will be even harder to maintain in the long run... :/ For example,
trying to figure out where dpu_*_hw_init() functions were called from was no
easy task. Or dpu_*_put(). Or dpu_*_get(). :/

Also, most of the macros are not in-line with Linux Kernel coding
style when it comes to macro usage: they affect control flow and some depend
on other local variables being already defined.

The good news is most macros can be replaced with helper functions and it would
not add too much extra code.

More comments below.

On Fri, Dec 18, 2020 at 11:23:52AM +0800, Liu Ying wrote:
> This patch introduces i.MX8qm/qxp Display Processing Unit(DPU) DRM support.
> 
> DPU is comprised of two main components that include a blit engine for
> 2D graphics accelerations(with composition support) and a display controller
> for display output processing, as well as a command sequencer.  Outside of
> DPU, optional prefetch engines, a.k.a, Prefetch Resolve Gasket(PRG) and
> Display Prefetch Resolve(DPR), can fetch data from memory prior to some DPU
> fetchunits of blit engine and display controller.  The prefetch engines
> support reading linear formats and resolving Vivante GPU tile formats.
> 
> This patch adds kernel modesetting support for the display controller part.
> The driver supports two CRTCs per display controller, planes backed by
> four fetchunits(decode0/1, fetchlayer, fetchwarp), fetchunit allocation
> logic for the two CRTCs, prefetch engines(with tile resolving supported),
> plane upscaling/deinterlacing/yuv2rgb CSC/alpha blending and CRTC gamma
> correction.  The registers of the controller is accessed without command
> sequencer involved, instead just by using CPU.
> 
> Reference manual can be found at:
> https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
> 
> Signed-off-by: Liu Ying 
> ---
> v4->v5:
> * Rebase up onto the latest drm-misc-next branch and remove the hook to
>   drm_atomic_helper_legacy_gamma_set(), because it was dropped by the newly
>   landed commit 'drm: automatic legacy gamma support'.
> * Remove a redundant blank line from dpu_plane_atomic_update().
> 
> v3->v4:
> * No change.
> 
> v2->v3:
> * Fix build warnings Reported-by: kernel test robot .
> * Drop build dependency on IMX_SCU, as dummy SCU functions have been added in
>   header files by the patch 'firmware: imx: add dummy functions' which has
>   landed in linux-next/master branch.
> 
> v1->v2:
> * Add compatible for i.MX8qm DPU, as this is tested with i.MX8qm LVDS 
> displays.
>   (Laurentiu)
> * Fix PRG burst size and stride. (Laurentiu)
> * Put 'ports' OF node to fix the bail-out logic in dpu_drm_probe(). 
> (Laurentiu)
> 
>  drivers/gpu/drm/imx/Kconfig   |   1 +
>  drivers/gpu/drm/imx/Makefile  |   1 +
>  drivers/gpu/drm/imx/dpu/Kconfig   |  10 +
>  drivers/gpu/drm/imx/dpu/Makefile  |  10 +
>  drivers/gpu/drm/imx/dpu/dpu-constframe.c  | 170 ++
>  drivers/gpu/drm/imx/dpu/dpu-core.c| 881 
>  drivers/gpu/drm/imx/dpu/dpu-crtc.c| 925 
> ++
>  drivers/gpu/drm/imx/dpu/dpu-crtc.h|  62 ++
>  drivers/gpu/drm/imx/dpu/dpu-disengcfg.c   | 114 
>  drivers/gpu/drm/imx/dpu/dpu-dprc.c| 721 +++
>  drivers/gpu/drm/imx/dpu/dpu-dprc.h|  40 ++
>  drivers/gpu/drm/imx/dpu/dpu-drv.c | 297 ++
>  drivers/gpu/drm/imx/dpu/dpu-drv.h |  28 +
>  drivers/gpu/drm/imx/dpu/dpu-extdst.c  | 296 ++
>  drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c | 291 ++
>  drivers/gpu/drm/imx/dpu/dpu-fetcheco.c| 221 +++
>  drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c  | 151 +
>  drivers/gpu/drm/imx/dpu/dpu-fetchunit.c   | 609 
>  drivers/gpu/drm/imx/dpu/dpu-fetchunit.h   | 191 ++
>  drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c   | 247 
>  drivers/gpu/drm/imx/dpu/dpu-framegen.c| 392 +
>  drivers/gpu/drm/imx/dpu/dpu-gammacor.c| 220 +++
>  drivers/gpu/drm/imx/dpu/dpu-hscaler.c | 272 +
>  drivers/gpu/drm/imx/dpu/dpu-kms.c | 543 ++
>  drivers/gpu/drm/imx/dpu/dpu-kms.h |  23 +
>  drivers/gpu/drm/imx/dpu/dpu-layerblend.c  | 345 +++
>  drivers/gpu/drm/imx/dpu/dpu-plane.c   | 702 +++
>  drivers/gpu/drm/imx/dpu/dpu-plane.h   |  56 ++
>  drivers/gpu/drm/imx/dpu/dpu-prg.c | 433 ++
>  drivers/gpu/drm/imx/dpu/dpu-prg.h |  45 ++
>  drivers/gpu/drm/imx/dpu/dpu-prv.h | 203 +++
>  

Re: [RFC] dcss: fix attaching to sn56dsi86 bridge

[Laurentiu Palcu]

Hi Lukas,

On Tue, Nov 24, 2020 at 06:19:57PM +0100, Lukas F. Hartmann wrote:
> The sn56dsi86 DSI to eDP bridge driver does not support attaching
> without a drm connector.

I think the SN65DSI86 driver is exactly what you should focus on, so
that it works when connector is optional. The ADV7511/ADV7533/ADV7535
driver provides the best example on how it should be done.

Thanks,
laurentiu

> This patch makes the attachment work. Required for the display chain
> in MNT Reform 2.0 (DCSS->NWL DSI->SN56DSI86->EDP).
> 
> Signed-off-by: Lukas F. Hartmann 
> ---
>  drivers/gpu/drm/imx/dcss/dcss-kms.c | 15 ---
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
> b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> index 135a62366..4967f828b 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> @@ -82,6 +82,7 @@ static int dcss_kms_bridge_connector_init(struct 
> dcss_kms_dev *kms)
>   struct drm_crtc *crtc = (struct drm_crtc *)>crtc;
>   struct drm_panel *panel;
>   struct drm_bridge *bridge;
> + struct drm_connector_list_iter iter;
>   int ret;
> 
>   ret = drm_of_find_panel_or_bridge(ddev->dev->of_node, 0, 0,
> @@ -104,19 +105,19 @@ static int dcss_kms_bridge_connector_init(struct 
> dcss_kms_dev *kms)
>   return ret;
>   }
> 
> - ret = drm_bridge_attach(encoder, bridge, NULL,
> - DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> + ret = drm_bridge_attach(encoder, bridge, NULL, 0);
>   if (ret < 0) {
>   dev_err(ddev->dev, "Unable to attach bridge %pOF\n",
>   bridge->of_node);
>   return ret;
>   }
> 
> - kms->connector = drm_bridge_connector_init(ddev, encoder);
> - if (IS_ERR(kms->connector)) {
> - dev_err(ddev->dev, "Unable to create bridge connector.\n");
> - return PTR_ERR(kms->connector);
> - }
> + /*
> +  * This hack to look up the connector is copied from mxsfb.
> +  */
> + drm_connector_list_iter_begin(ddev, );
> + kms->connector = drm_connector_list_iter_next();
> + drm_connector_list_iter_end();
> 
>   drm_connector_attach_encoder(kms->connector, encoder);
> 
> --
> 2.28.0
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 5/8] drm/imx: Introduce i.MX8qxp DPU DRM

[Laurentiu Palcu]

Hi Liu Ying,

On Mon, Nov 23, 2020 at 10:45:38AM +0800, Liu Ying wrote:
> Hi Laurentiu,
> 
> On Fri, 2020-11-20 at 16:38 +0200, Laurentiu Palcu wrote:
> > Hi Liu Ying,
> > 
> > I gave this a first look but, since this is a huge piece of code and I'm not
> > very familiar with DPU, I'll probably give it another pass next week.
> > 
> > Anyway, some comments/questions inline.
> > 
> > On Thu, Nov 19, 2020 at 11:22:22AM +0200, Liu Ying wrote:
> > > This patch introduces i.MX8qxp Display Processing Unit(DPU) DRM support.
> > > 
> > > DPU is comprised of two main components that include a blit engine for
> > > 2D graphics accelerations(with composition support) and a display 
> > > controller
> > > for display output processing, as well as a command sequencer.  Outside of
> > > DPU, optional prefetch engines, a.k.a, Prefetch Resolve Gasket(PRG) and
> > > Display Prefetch Resolve(DPR), can fetch data from memory prior to some 
> > > DPU
> > > fetchunits of blit engine and display controller.  The prefetch engines
> > > support reading linear formats and resolving Vivante GPU tile formats.
> > > 
> > > This patch adds kernel modesetting support for the display controller 
> > > part.
> > > The driver supports two CRTCs per display controller, planes backed by
> > > four fetchunits(decode0/1, fetchlayer, fetchwarp), fetchunit allocation
> > > logic for the two CRTCs, prefetch engines(with tile resolving supported),
> > > plane upscaling/deinterlacing/yuv2rgb CSC/alpha blending and CRTC gamma
> > > correction.  The registers of the controller is accessed without command
> > > sequencer involved, instead just by using CPU.
> > 
> > Will you also add support for command sequencer in the future? The command
> > sequencer seems to have the same purpose as the DCSS context loader on 
> > iMX8MQ,
> > which is very useful for configuring the various DC blocks right in the
> > blanking period without having to worry about synchronization. Why not use 
> > it
> > from the very beginning?
> 
> The single command sequencer(cmdseq) per DPU supports
> NOP/CALL/RET/WRITE/COPY/CCOPY/SYNC instructions.
> 
> It is designed to autonomously process command lists.
> 
> Two reasons for not using cmdseq for display controller(kms):
> 
> 1) performance consideration:
> 
> The SYNC instruction stops processing the subsequent command list until
> one specific hardware event of the DPU is triggered, like shadow loaded
> event, ComCtrl_SW0(cmdseq sequence complete event), etc. To use the
> autonomous command list processing, we would queue command blocks to a
> chain. The command blocks are usually comprised of some initial WRITE
> instructions and a final SYNC instruction(to make sure the WRITE
> instructions take effect).  The command blocks could be for blit engine
> or display controller.  As blit engine and display controller
> operations are naturally async, those SYNC instructions would impact
> the blit and display performance.  Even the two display pipelines(two
> CRTCs) of DPU themselves could impact each other's performance, because
> there could be parallel atomic commits for the two pipelines. 
> 
> 2) no cmdseq read instructions: 
> 
> The KMS driver for the display controller needs to read DPU registers
> to report CRTC scannout position, vlbank count and CRC data(DPU
> Signature units). Also, it needs to read DPU registers to sync some
> events(like FrameGen counter moving). Inserting CPU read operations
> into command sequence would pollute the pure cmdseq programming model.
> 
> 
> In general, cmdseq is probably better to be reserved for blit engine,
> since I assume blit engine, as a 2D engine, usually doesn't need
> reading registers.  Also, blit performance would be good.

Thanks for clarifying this.

> 
> > 
> > > Reference manual can be found at:
> > > https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
> > > 
> > > Signed-off-by: Liu Ying 
> > > ---
> > 
> > [...]
> > 
> > > diff --git a/drivers/gpu/drm/imx/dpu/dpu-core.c 
> > > b/drivers/gpu/drm/imx/dpu/dpu-core.c
> > > new file mode 100644
> > > index ..1583c7a
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/imx/dpu/dpu-core.c
> > > @@ -0,0 +1,880 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +
> > > +/*
> > > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > > + * Copyright 2017-2020 NXP
> > > + */
> > > +
> > > +#includ

Re: [PATCH 5/8] drm/imx: Introduce i.MX8qxp DPU DRM

[Laurentiu Palcu]

Hi Liu Ying,

I gave this a first look but, since this is a huge piece of code and I'm not
very familiar with DPU, I'll probably give it another pass next week.

Anyway, some comments/questions inline.

On Thu, Nov 19, 2020 at 11:22:22AM +0200, Liu Ying wrote:
> This patch introduces i.MX8qxp Display Processing Unit(DPU) DRM support.
> 
> DPU is comprised of two main components that include a blit engine for
> 2D graphics accelerations(with composition support) and a display controller
> for display output processing, as well as a command sequencer.  Outside of
> DPU, optional prefetch engines, a.k.a, Prefetch Resolve Gasket(PRG) and
> Display Prefetch Resolve(DPR), can fetch data from memory prior to some DPU
> fetchunits of blit engine and display controller.  The prefetch engines
> support reading linear formats and resolving Vivante GPU tile formats.
> 
> This patch adds kernel modesetting support for the display controller part.
> The driver supports two CRTCs per display controller, planes backed by
> four fetchunits(decode0/1, fetchlayer, fetchwarp), fetchunit allocation
> logic for the two CRTCs, prefetch engines(with tile resolving supported),
> plane upscaling/deinterlacing/yuv2rgb CSC/alpha blending and CRTC gamma
> correction.  The registers of the controller is accessed without command
> sequencer involved, instead just by using CPU.

Will you also add support for command sequencer in the future? The command
sequencer seems to have the same purpose as the DCSS context loader on iMX8MQ,
which is very useful for configuring the various DC blocks right in the
blanking period without having to worry about synchronization. Why not use it
from the very beginning?

> 
> Reference manual can be found at:
> https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
> 
> Signed-off-by: Liu Ying 
> ---

[...]

> diff --git a/drivers/gpu/drm/imx/dpu/dpu-core.c 
> b/drivers/gpu/drm/imx/dpu/dpu-core.c
> new file mode 100644
> index ..1583c7a
> --- /dev/null
> +++ b/drivers/gpu/drm/imx/dpu/dpu-core.c
> @@ -0,0 +1,880 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017-2020 NXP
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "dpu.h"
> +#include "dpu-prv.h"
> +
> +static inline u32 dpu_comctrl_read(struct dpu_soc *dpu, unsigned int offset)
> +{
> + return readl(dpu->comctrl_reg + offset);
> +}
> +
> +static inline void dpu_comctrl_write(struct dpu_soc *dpu,
> +  unsigned int offset, u32 value)
> +{
> + writel(value, dpu->comctrl_reg + offset);
> +}
> +
> +/* Constant Frame */
> +static const unsigned int cf_ids[] = {0, 1, 4, 5};
> +static const enum dpu_unit_type cf_types[] = {DPU_DISP, DPU_DISP,
> +   DPU_DISP, DPU_DISP};
> +static const unsigned long cf_ofss[] = {0x4400, 0x5400, 0x4c00, 0x5c00};
> +static const unsigned long cf_pec_ofss[] = {0x960, 0x9e0, 0x9a0, 0xa20};
> +
> +/* Display Engine Configuration */
> +static const unsigned int dec_ids[] = {0, 1};
> +static const enum dpu_unit_type dec_types[] = {DPU_DISP, DPU_DISP};
> +static const unsigned long dec_ofss[] = {0xb400, 0xb420};
> +
> +/* External Destination */
> +static const unsigned int ed_ids[] = {0, 1, 4, 5};
> +static const enum dpu_unit_type ed_types[] = {DPU_DISP, DPU_DISP,
> +   DPU_DISP, DPU_DISP};
> +static const unsigned long ed_ofss[] = {0x4800, 0x5800, 0x5000, 0x6000};
> +static const unsigned long ed_pec_ofss[] = {0x980, 0xa00, 0x9c0, 0xa40};
> +
> +/* Fetch Decode */
> +static const unsigned int fd_ids[] = {0, 1, 9};
> +static const enum dpu_unit_type fd_types[] = {DPU_DISP, DPU_DISP, DPU_BLIT};
> +static const unsigned long fd_ofss[] = {0x6c00, 0x7800, 0x1000};
> +static const unsigned long fd_pec_ofss[] = {0xa80, 0xaa0, 0x820};
> +
> +/* Fetch ECO */
> +static const unsigned int fe_ids[] = {0, 1, 2, 9};
> +static const enum dpu_unit_type fe_types[] = {DPU_DISP, DPU_DISP,
> +   DPU_DISP, DPU_BLIT};
> +static const unsigned long fe_ofss[] = {0x7400, 0x8000, 0x6800, 0x1c00};
> +static const unsigned long fe_pec_ofss[] = {0xa90, 0xab0, 0xa70, 0x850};
> +
> +/* Frame Generator */
> +static const unsigned int fg_ids[] = {0, 1};
> +static const enum dpu_unit_type fg_types[] = {DPU_DISP, DPU_DISP};
> +static const unsigned long fg_ofss[] = {0xb800, 0xd400};
> +
> +/* Fetch Layer */
> +static const unsigned int fl_ids[] = {0};
> +static const enum dpu_unit_type fl_types[] = {DPU_DISP};
> +static const unsigned long fl_ofss[] = {0x8400};
> +static const unsigned long fl_pec_ofss[] = {0xac0};
> +
> +/* Fetch Warp */
> +static const unsigned int fw_ids[] = {2, 9};
> +static const enum dpu_unit_type fw_types[] = {DPU_DISP, DPU_BLIT};
> +static const unsigned long fw_ofss[] = {0x6400, 

Re: [PATCH 0/8] drm/imx: Introduce i.MX8qxp DPU DRM

[Laurentiu Palcu]

Hi Liu Ying,

On Thu, Nov 19, 2020 at 05:22:17PM +0800, Liu Ying wrote:
> Hi,
> 
> 
> This patch set introduces i.MX8qxp Display Processing Unit(DPU) DRM support.

Glad to see this series out. However, something went wrong with it as
patch 5/8 didn't make it to dri-devel mailing list... :/

https://lists.freedesktop.org/archives/dri-devel/2020-November/thread.html

So, people on to dri-devel may not be able to review it...

However, it did make it to LKML:

https://lkml.org/lkml/2020/11/19/249

Not sure what happened here... :/

Thanks,
laurentiu


> 
> DPU is comprised of a blit engine for 2D graphics, a display controller
> and a command sequencer.  Outside of DPU, optional prefetch engines can
> fetch data from memory prior to some DPU fetchunits of blit engine and
> display controller.  The pre-fetchers support linear formats and Vivante
> GPU tile formats.
> 
> Reference manual can be found at:
> https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
> 
> 
> This patch set adds kernel modesetting support for the display controller 
> part.
> It supports two CRTCs per display controller, several planes, prefetch
> engines and some properties of CRTC and plane.  Currently, the registers of
> the controller is accessed without command sequencer involved, instead just by
> using CPU.  DRM connectors would be created from the DPU KMS driver.
> 
> 
> If people want to try this series, clock patches can be found at:
> https://www.spinics.net/lists/arm-kernel/msg856137.html
> 
> and, power domain patches at:
> https://www.spinics.net/lists/arm-kernel/msg856097.html
> 
> 
> I will send other patch sets to add downstream bridges(embedded in i.MX8qxp)
> to support LVDS displays.
> 
> A brief look at the pipe:
> prefetch eng -> DPU -> pixel combiner -> pixel link -> pixel to DPI(pxl2dpi) 
> ->
> LVDS display bridge(LDB)
> 
> 
> Patch 1 ~ 3 add dt-bindings for DPU and prefetch engines.
> Patch 4 is a minor improvement of a macro to suppress warning as the KMS 
> driver
> uses it.
> Patch 5 introduces the DPU DRM support.
> Patch 6 updates MAINTAINERS.
> Patch 7 & 8 add DPU and prefetch engines support in the device tree of
> i.MX8qxp MEK platform.
> 
> 
> Welcome comments, thanks.
> 
> 
> Liu Ying (8):
>   dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
>   dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding
>   dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding
>   drm/atomic: Avoid unused-but-set-variable warning on
> for_each_old_plane_in_state
>   drm/imx: Introduce i.MX8qxp DPU DRM
>   MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver
>   arm64: imx8qxp:dtsi: Introduce DC0 subsystem
>   arm64: dts: imx8qxp-mek: Enable DPU and it's prefetch engines
> 
>  .../bindings/display/imx/fsl,imx8qxp-dprc.yaml |  87 ++
>  .../bindings/display/imx/fsl,imx8qxp-dpu.yaml  | 358 
>  .../bindings/display/imx/fsl,imx8qxp-prg.yaml  |  60 ++
>  MAINTAINERS|   9 +
>  arch/arm64/boot/dts/freescale/imx8qxp-mek.dts  |  64 ++
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 313 +++
>  drivers/gpu/drm/imx/Kconfig|   1 +
>  drivers/gpu/drm/imx/Makefile   |   1 +
>  drivers/gpu/drm/imx/dpu/Kconfig|  10 +
>  drivers/gpu/drm/imx/dpu/Makefile   |  10 +
>  drivers/gpu/drm/imx/dpu/dpu-constframe.c   | 170 
>  drivers/gpu/drm/imx/dpu/dpu-core.c | 880 
>  drivers/gpu/drm/imx/dpu/dpu-crtc.c | 926 
> +
>  drivers/gpu/drm/imx/dpu/dpu-crtc.h |  62 ++
>  drivers/gpu/drm/imx/dpu/dpu-disengcfg.c| 114 +++
>  drivers/gpu/drm/imx/dpu/dpu-dprc.c | 721 
>  drivers/gpu/drm/imx/dpu/dpu-dprc.h |  40 +
>  drivers/gpu/drm/imx/dpu/dpu-drv.c  | 296 +++
>  drivers/gpu/drm/imx/dpu/dpu-drv.h  |  28 +
>  drivers/gpu/drm/imx/dpu/dpu-extdst.c   | 296 +++
>  drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c  | 291 +++
>  drivers/gpu/drm/imx/dpu/dpu-fetcheco.c | 221 +
>  drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c   | 151 
>  drivers/gpu/drm/imx/dpu/dpu-fetchunit.c| 609 ++
>  drivers/gpu/drm/imx/dpu/dpu-fetchunit.h| 191 +
>  drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c| 247 ++
>  drivers/gpu/drm/imx/dpu/dpu-framegen.c | 392 +
>  drivers/gpu/drm/imx/dpu/dpu-gammacor.c | 220 +
>  drivers/gpu/drm/imx/dpu/dpu-hscaler.c  | 272 ++
>  drivers/gpu/drm/imx/dpu/dpu-kms.c  | 543 
>  drivers/gpu/drm/imx/dpu/dpu-kms.h  |  23 +
>  drivers/gpu/drm/imx/dpu/dpu-layerblend.c   | 345 
>  drivers/gpu/drm/imx/dpu/dpu-plane.c| 703 
>  drivers/gpu/drm/imx/dpu/dpu-plane.h   

[PATCH] drm/imx/dcss: allow using nearest neighbor interpolation scaling

[Laurentiu Palcu]

This patch adds support for using NN interpolation scaling by setting the
SCALING_FILTER plane property to 1. Otherwise, the default method is used.

Signed-off-by: Laurentiu Palcu 
---
I had no retro pixel art games to test this with, so I used modetest to see the
results:

To test, I used a 240x135 buffer, upscaled 8 times to 1920x1080:
 * default scaling method using gaussian filter:
/usr/bin/modetest -M imx-dcss -w 33:SCALING_FILTER:0 -P 33@38:240x135*8@XR24
 * NN interpolation method:
/usr/bin/modetest -M imx-dcss -w 33:SCALING_FILTER:1 -P 33@38:240x135*8@XR24

Thanks,
laurentiu

 drivers/gpu/drm/imx/dcss/dcss-dev.h|  3 ++
 drivers/gpu/drm/imx/dcss/dcss-plane.c  | 10 +-
 drivers/gpu/drm/imx/dcss/dcss-scaler.c | 47 +-
 3 files changed, 50 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.h 
b/drivers/gpu/drm/imx/dcss/dcss-dev.h
index c642ae17837f..1e582270c6ea 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-dev.h
+++ b/drivers/gpu/drm/imx/dcss/dcss-dev.h
@@ -7,6 +7,7 @@
 #define __DCSS_PRV_H__
 
 #include 
+#include 
 #include 
 #include 
 
@@ -165,6 +166,8 @@ void dcss_ss_sync_set(struct dcss_ss *ss, struct videomode 
*vm,
 /* SCALER */
 int dcss_scaler_init(struct dcss_dev *dcss, unsigned long scaler_base);
 void dcss_scaler_exit(struct dcss_scaler *scl);
+void dcss_scaler_set_filter(struct dcss_scaler *scl, int ch_num,
+   enum drm_scaling_filter scaling_filter);
 void dcss_scaler_setup(struct dcss_scaler *scl, int ch_num,
   const struct drm_format_info *format,
   int src_xres, int src_yres, int dst_xres, int dst_yres,
diff --git a/drivers/gpu/drm/imx/dcss/dcss-plane.c 
b/drivers/gpu/drm/imx/dcss/dcss-plane.c
index 5db093aada2f..03ba88f7f995 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-plane.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-plane.c
@@ -257,7 +257,8 @@ static bool dcss_plane_needs_setup(struct drm_plane_state 
*state,
   state->src_h  != old_state->src_h  ||
   fb->format->format != old_fb->format->format ||
   fb->modifier  != old_fb->modifier ||
-  state->rotation != old_state->rotation;
+  state->rotation != old_state->rotation ||
+  state->scaling_filter != old_state->scaling_filter;
 }
 
 static void dcss_plane_atomic_update(struct drm_plane *plane,
@@ -313,6 +314,9 @@ static void dcss_plane_atomic_update(struct drm_plane 
*plane,
is_rotation_90_or_270 = state->rotation & (DRM_MODE_ROTATE_90 |
   DRM_MODE_ROTATE_270);
 
+   dcss_scaler_set_filter(dcss->scaler, dcss_plane->ch_num,
+  state->scaling_filter);
+
dcss_scaler_setup(dcss->scaler, dcss_plane->ch_num,
  state->fb->format,
  is_rotation_90_or_270 ? src_h : src_w,
@@ -394,6 +398,10 @@ struct dcss_plane *dcss_plane_init(struct drm_device *drm,
if (ret)
return ERR_PTR(ret);
 
+   drm_plane_create_scaling_filter_property(_plane->base,
+   BIT(DRM_SCALING_FILTER_DEFAULT) |
+   
BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
+
drm_plane_create_rotation_property(_plane->base,
   DRM_MODE_ROTATE_0,
   DRM_MODE_ROTATE_0   |
diff --git a/drivers/gpu/drm/imx/dcss/dcss-scaler.c 
b/drivers/gpu/drm/imx/dcss/dcss-scaler.c
index cd21905de580..47852b9dd5ea 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-scaler.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-scaler.c
@@ -77,6 +77,8 @@ struct dcss_scaler_ch {
 
u32 c_vstart;
u32 c_hstart;
+
+   bool use_nn_interpolation;
 };
 
 struct dcss_scaler {
@@ -243,6 +245,17 @@ static void dcss_scaler_gaussian_filter(int fc_q, bool 
use_5_taps,
}
 }
 
+static void dcss_scaler_nearest_neighbor_filter(bool use_5_taps,
+   int coef[][PSC_NUM_TAPS])
+{
+   int i, j;
+
+   for (i = 0; i < PSC_STORED_PHASES; i++)
+   for (j = 0; j < PSC_NUM_TAPS; j++)
+   coef[i][j] = j == PSC_NUM_TAPS >> 1 ?
+   (1 << PSC_COEFF_PRECISION) : 0;
+}
+
 /**
  * dcss_scaler_filter_design() - Compute filter coefficients using
  *  Gaussian filter.
@@ -253,7 +266,8 @@ static void dcss_scaler_gaussian_filter(int fc_q, bool 
use_5_taps,
  */
 static void dcss_scaler_filter_design(int src_length, int dst_length,
  bool use_5_taps, bool phase0_identity,
- int coef[][PSC_NUM_TAPS])
+ int coef[][PSC_NUM_TAPS],
+ bool nn_interp

[PATCH 2/2] drm/imx/dcss: fix coccinelle warning

[Laurentiu Palcu]

This small patch fixes a warning that I got while running coccinelle:

  CHECK   drivers/gpu/drm/imx/dcss/dcss-plane.c
  drivers/gpu/drm/imx/dcss/dcss-plane.c:107:21-23: WARNING !A || A && B is 
equivalent to !A || B

Fixes: 9021c317b770 ("drm/imx: Add initial support for DCSS on iMX8MQ")
Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/imx/dcss/dcss-plane.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/imx/dcss/dcss-plane.c 
b/drivers/gpu/drm/imx/dcss/dcss-plane.c
index 46a188dd02ad..5db093aada2f 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-plane.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-plane.c
@@ -103,8 +103,7 @@ static bool dcss_plane_can_rotate(const struct 
drm_format_info *format,
  bool mod_present, u64 modifier,
  unsigned int rotation)
 {
-   bool linear_format = !mod_present ||
-(mod_present && modifier == DRM_FORMAT_MOD_LINEAR);
+   bool linear_format = !mod_present || modifier == DRM_FORMAT_MOD_LINEAR;
u32 supported_rotation = DRM_MODE_ROTATE_0;
 
if (!format->is_yuv && linear_format)
-- 
2.23.0

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[PATCH 0/2] drm/imx/dcss: a couple of fixes

[Laurentiu Palcu]

Hi,

This patchset fixes 90/270 rotations for Vivante tiled and super-tiled
formats and a Coccinelle warning.

Thanks,
laurentiu

Laurentiu Palcu (2):
  drm/imx/dcss: fix rotations for Vivante tiled formats
  drm/imx/dcss: fix coccinelle warning

 drivers/gpu/drm/imx/dcss/dcss-plane.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

-- 
2.23.0

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[PATCH 1/2] drm/imx/dcss: fix rotations for Vivante tiled formats

[Laurentiu Palcu]

DCSS supports 90/180/270 degree rotations for Vivante tiled and super-tiled
formats. Unfortunately, with the current code, they didn't work properly.

This simple patch makes the rotations work by fixing the way the scaler is set
up for 90/270 degree rotations. In this particular case, the source width and
height need to be swapped since DPR is sending the buffer to scaler already
rotated.

Also, make sure to allow full rotations for DRM_FORMAT_MOD_VIVANTE_SUPER_TILED.

Fixes: 9021c317b770 ("drm/imx: Add initial support for DCSS on iMX8MQ")
Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/imx/dcss/dcss-plane.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/imx/dcss/dcss-plane.c 
b/drivers/gpu/drm/imx/dcss/dcss-plane.c
index e13652e3a115..46a188dd02ad 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-plane.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-plane.c
@@ -111,7 +111,8 @@ static bool dcss_plane_can_rotate(const struct 
drm_format_info *format,
supported_rotation = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
 DRM_MODE_REFLECT_MASK;
else if (!format->is_yuv &&
-modifier == DRM_FORMAT_MOD_VIVANTE_TILED)
+(modifier == DRM_FORMAT_MOD_VIVANTE_TILED ||
+ modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED))
supported_rotation = DRM_MODE_ROTATE_MASK |
 DRM_MODE_REFLECT_MASK;
else if (format->is_yuv && linear_format &&
@@ -272,6 +273,7 @@ static void dcss_plane_atomic_update(struct drm_plane 
*plane,
u32 src_w, src_h, dst_w, dst_h;
struct drm_rect src, dst;
bool enable = true;
+   bool is_rotation_90_or_270;
 
if (!fb || !state->crtc || !state->visible)
return;
@@ -309,8 +311,13 @@ static void dcss_plane_atomic_update(struct drm_plane 
*plane,
 
dcss_plane_atomic_set_base(dcss_plane);
 
+   is_rotation_90_or_270 = state->rotation & (DRM_MODE_ROTATE_90 |
+  DRM_MODE_ROTATE_270);
+
dcss_scaler_setup(dcss->scaler, dcss_plane->ch_num,
- state->fb->format, src_w, src_h,
+ state->fb->format,
+ is_rotation_90_or_270 ? src_h : src_w,
+ is_rotation_90_or_270 ? src_w : src_h,
  dst_w, dst_h,
  drm_mode_vrefresh(_state->mode));
 
-- 
2.23.0

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Re: [PATCH v3 07/22] drm/imx/dcss: Initialize DRM driver instance with CMA helper macro

[Laurentiu Palcu]

Hi Thomas,

On Wed, Sep 23, 2020 at 12:21:44PM +0200, Thomas Zimmermann wrote:
> The i.MX DCSS driver uses CMA helpers with default callback functions.
> Initialize the driver structure with the rsp CMA helper macro. The
> driver is being converted to use GEM object functions as part of
> this change.
> 
> Two callbacks, .gem_prime_export and .gem_prime_import, were initialized
> to their default implementations, so they are just kept empty now.
> 
> Signed-off-by: Thomas Zimmermann 
> Reported-by: kernel test robot 
> ---

Reviewed-by: Laurentiu Palcu 

Thanks,
laurentiu

>  drivers/gpu/drm/imx/dcss/dcss-kms.c | 14 +-
>  1 file changed, 1 insertion(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
> b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> index 135a62366ab8..b72e5cef7e40 100644
> --- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
> +++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
> @@ -28,19 +28,7 @@ static const struct drm_mode_config_funcs 
> dcss_drm_mode_config_funcs = {
>  
>  static struct drm_driver dcss_kms_driver = {
>   .driver_features= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> - .gem_free_object_unlocked = drm_gem_cma_free_object,
> - .gem_vm_ops = _gem_cma_vm_ops,
> - .dumb_create= drm_gem_cma_dumb_create,
> -
> - .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> - .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> - .gem_prime_import   = drm_gem_prime_import,
> - .gem_prime_export   = drm_gem_prime_export,
> - .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> - .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> - .gem_prime_vmap = drm_gem_cma_prime_vmap,
> - .gem_prime_vunmap   = drm_gem_cma_prime_vunmap,
> - .gem_prime_mmap = drm_gem_cma_prime_mmap,
> + DRM_GEM_CMA_DRIVER_OPS,
>   .fops   = _cma_fops,
>   .name   = "imx-dcss",
>   .desc   = "i.MX8MQ Display Subsystem",
> -- 
> 2.28.0
> 
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[PATCH] drm/imx/dcss: fix 64-bit divisions

[Laurentiu Palcu]

Use div_s64() for the 64-bit divisions. This would allow the driver to compile
on 32-bit architectures, if needed.

Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/imx/dcss/dcss-scaler.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/imx/dcss/dcss-scaler.c 
b/drivers/gpu/drm/imx/dcss/dcss-scaler.c
index cd21905de580..7c1e0e461244 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-scaler.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-scaler.c
@@ -134,7 +134,7 @@ static int div_q(int A, int B)
else
temp -= B / 2;
 
-   result = (int)(temp / B);
+   result = (int)(div_s64(temp, B));
return result;
 }
 
@@ -237,7 +237,7 @@ static void dcss_scaler_gaussian_filter(int fc_q, bool 
use_5_taps,
ll_temp = coef[phase][i];
ll_temp <<= PSC_COEFF_PRECISION;
ll_temp += sum >> 1;
-   ll_temp /= sum;
+   ll_temp = div_s64(ll_temp, sum);
coef[phase][i] = (int)ll_temp;
}
}
-- 
2.17.1

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Re: per-plane LUTs and CSCs?

[Laurentiu Palcu]

Hi Pekka,

On Thu, Sep 10, 2020 at 01:28:03PM +0300, Pekka Paalanen wrote:
> On Thu, 10 Sep 2020 12:30:09 +0300
> Laurentiu Palcu  wrote:
> 
> > Hi Pekka,
> > 
> > On Thu, Sep 10, 2020 at 11:50:26AM +0300, Pekka Paalanen wrote:
> > > On Thu, 10 Sep 2020 09:52:26 +0200
> > > Daniel Vetter  wrote:
> > >   
> > > > On Thu, Sep 10, 2020 at 10:25:43AM +0300, Pekka Paalanen wrote:  
> > > > > On Wed, 9 Sep 2020 13:57:28 +0300
> > > > > Laurentiu Palcu  wrote:
> > > > > 
> > > > > > Hi all,
> > > > > > 
> > > > > > I was wondering whether you could give me an advise on how to 
> > > > > > proceed further
> > > > > > with the following issue as I'm preparing to upstream the next set 
> > > > > > of patches
> > > > > > for the iMX8MQ display controller(DCSS). The display controller has 
> > > > > > 3 planes,
> > > > > > each with 2 CSCs and one degamma LUT. The CSCs are in front and 
> > > > > > after the LUT
> > > > > > respectively. Then the output from those 3 pipes is blended 
> > > > > > together and then
> > > > > > gamma correction is applied using a linear-to-nonlinear LUT and 
> > > > > > another CSC, if
> > > > > > needed.  
> > > 
> > > Hi,
> > > 
> > > hmm, so FB -> CSC -> LUT -> CSC -> blending?
> > > 
> > > Is it then
> > >   blending -> LUT -> CSC -> encoder
> > > or
> > >   blending -> CSC -> LUT -> encoder?  
> > 
> > The DCSS pipeline topology is this:
> > 
> > FB1->CSC_A->LUT->CSC_B-\
> > FB2->CSC_A->LUT->CSC_B-|-blender->LUT->CSC_O->encoder
> > FB3->CSC_A->LUT->CSC_B-/
> > 
> > Basically, CSC_A is used to convert to a common colorspace if needed
> > (YUV->RGB) as well as to perform pixel range conversions: limited->full.
> > CSC_B is for gamut conversions(like 709->2020). The CSC_O is used to
> > convert to the colorspace used by the output (like RGB->YUV).
> 
> I didn't realize that it would be correct to do RGB-YUV conversion in
> non-linear space, but yeah, that's what most software do too I guess.
> 
> > > 
> > > Are all these LUTs per-channel 1D LUTs or something else?  
> > 
> > LUTs are 3D, per pixel component.
> 
> Sorry, which one?
> 
> An example of a 3D LUT is 32x32x32 entries with each entry being a
> triplet, while a 1D LUT could be 1024 entries with each entry being a
> scalar. 1D LUTs are used per-channel so you need three of them, 3D LUTs
> you need just one for the color value triplet mapping.
> 
> A 3D LUT can express much more than a 4x4 CTM. A 1D LUT cannot do the
> channel mixing that a CTM can.
> 
> So if you truly have 3D LUTs everywhere, I wonder why the CSC matrix
> blocks exist...

Indeed, it's 1D LUTs. I got them mixed up... :/ Sorry about that.

Thanks,
Laurentiu

> 
> 
> Thanks,
> pq


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Re: [PATCH] drm/imx/dcss: fix compilation issue on 32bit

[Laurentiu Palcu]

Hi Lucas,

On Thu, Sep 10, 2020 at 12:24:44PM +0200, Lucas Stach wrote:
> On Do, 2020-09-10 at 13:21 +0300, Laurentiu Palcu wrote:
> > On Thu, Sep 10, 2020 at 11:57:10AM +0200, Daniel Vetter wrote:
> > > On Thu, Sep 10, 2020 at 11:53 AM Laurentiu Palcu
> > >  wrote:
> > > > When compiling for 32bit platforms, the compilation fails with:
> > > > 
> > > > ERROR: modpost: "__aeabi_ldivmod"
> > > > [drivers/gpu/drm/imx/dcss/imx-dcss.ko] undefined!
> > > > ERROR: modpost: "__aeabi_uldivmod"
> > > > [drivers/gpu/drm/imx/dcss/imx-dcss.ko] undefined!
> > > > 
> > > > This patch adds a dependency on ARM64 since no 32bit SoCs have DCSS, so 
> > > > far.
> > > 
> > > Usual way to fix this correctly is using the right division macros,
> > > not limiting the driver to 64bit. But this works for now, would be
> > > good to fix this properly for compile-testing and all that.
> > 
> > I didn't see the point in using the macros since this is running only on
> > 64bit. Though I will probably revisit it and fix it properly in a
> > subsequent patch.
> > 
> > > > Signed-off-by: Laurentiu Palcu 
> > > > Reported-by: Daniel Vetter 
> > > 
> > > Reviewed-by: Daniel Vetter 
> > > 
> > > Please push to drm-misc-next.
> > 
> > About that, I may need some help pushing it.
> 
> I've already pushed a few minutes ago, so we don't disturb the build
> tests any longer.

Thanks a lot,
laurentiu

> 
> Regards,
> Lucas
> 
> > Apparently, my request for
> > a legacy SSH account for contributing to drm-misc got stalled:
> > 
> > https://gitlab.freedesktop.org/freedesktop/freedesktop/-/issues/289
> > 
> > Thanks,
> > laurentiu
> > 
> > > -Daniel
> > > 
> > > 
> > > 
> > > ---
> > > >  drivers/gpu/drm/imx/dcss/Kconfig | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/imx/dcss/Kconfig 
> > > > b/drivers/gpu/drm/imx/dcss/Kconfig
> > > > index 69860de8861f..2b17a964ff05 100644
> > > > --- a/drivers/gpu/drm/imx/dcss/Kconfig
> > > > +++ b/drivers/gpu/drm/imx/dcss/Kconfig
> > > > @@ -3,7 +3,7 @@ config DRM_IMX_DCSS
> > > > select IMX_IRQSTEER
> > > > select DRM_KMS_CMA_HELPER
> > > > select VIDEOMODE_HELPERS
> > > > -   depends on DRM && ARCH_MXC
> > > > +   depends on DRM && ARCH_MXC && ARM64
> > > > help
> > > >   Choose this if you have a NXP i.MX8MQ based system and want 
> > > > to use the
> > > >   Display Controller Subsystem. This option enables DCSS 
> > > > support.
> > > > --
> > > > 2.17.1
> > > > 
> > > 
> > > -- 
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > http://blog.ffwll.ch
> 
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Re: [PATCH] drm/imx/dcss: fix compilation issue on 32bit

[Laurentiu Palcu]

On Thu, Sep 10, 2020 at 11:57:10AM +0200, Daniel Vetter wrote:
> On Thu, Sep 10, 2020 at 11:53 AM Laurentiu Palcu
>  wrote:
> >
> > When compiling for 32bit platforms, the compilation fails with:
> >
> > ERROR: modpost: "__aeabi_ldivmod"
> > [drivers/gpu/drm/imx/dcss/imx-dcss.ko] undefined!
> > ERROR: modpost: "__aeabi_uldivmod"
> > [drivers/gpu/drm/imx/dcss/imx-dcss.ko] undefined!
> >
> > This patch adds a dependency on ARM64 since no 32bit SoCs have DCSS, so far.
> 
> Usual way to fix this correctly is using the right division macros,
> not limiting the driver to 64bit. But this works for now, would be
> good to fix this properly for compile-testing and all that.

I didn't see the point in using the macros since this is running only on
64bit. Though I will probably revisit it and fix it properly in a
subsequent patch.

> 
> > Signed-off-by: Laurentiu Palcu 
> > Reported-by: Daniel Vetter 
> 
> Reviewed-by: Daniel Vetter 
> 
> Please push to drm-misc-next.

About that, I may need some help pushing it. Apparently, my request for
a legacy SSH account for contributing to drm-misc got stalled:

https://gitlab.freedesktop.org/freedesktop/freedesktop/-/issues/289

Thanks,
laurentiu

> -Daniel
> 
> 
> 
> ---
> >  drivers/gpu/drm/imx/dcss/Kconfig | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/imx/dcss/Kconfig 
> > b/drivers/gpu/drm/imx/dcss/Kconfig
> > index 69860de8861f..2b17a964ff05 100644
> > --- a/drivers/gpu/drm/imx/dcss/Kconfig
> > +++ b/drivers/gpu/drm/imx/dcss/Kconfig
> > @@ -3,7 +3,7 @@ config DRM_IMX_DCSS
> > select IMX_IRQSTEER
> > select DRM_KMS_CMA_HELPER
> > select VIDEOMODE_HELPERS
> > -   depends on DRM && ARCH_MXC
> > +   depends on DRM && ARCH_MXC && ARM64
> > help
> >   Choose this if you have a NXP i.MX8MQ based system and want to 
> > use the
> >   Display Controller Subsystem. This option enables DCSS support.
> > --
> > 2.17.1
> >
> 
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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[PATCH] drm/imx/dcss: fix compilation issue on 32bit

[Laurentiu Palcu]

When compiling for 32bit platforms, the compilation fails with:

ERROR: modpost: "__aeabi_ldivmod"
[drivers/gpu/drm/imx/dcss/imx-dcss.ko] undefined!
ERROR: modpost: "__aeabi_uldivmod"
[drivers/gpu/drm/imx/dcss/imx-dcss.ko] undefined!

This patch adds a dependency on ARM64 since no 32bit SoCs have DCSS, so far.

Signed-off-by: Laurentiu Palcu 
Reported-by: Daniel Vetter 
---
 drivers/gpu/drm/imx/dcss/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/imx/dcss/Kconfig b/drivers/gpu/drm/imx/dcss/Kconfig
index 69860de8861f..2b17a964ff05 100644
--- a/drivers/gpu/drm/imx/dcss/Kconfig
+++ b/drivers/gpu/drm/imx/dcss/Kconfig
@@ -3,7 +3,7 @@ config DRM_IMX_DCSS
select IMX_IRQSTEER
select DRM_KMS_CMA_HELPER
select VIDEOMODE_HELPERS
-   depends on DRM && ARCH_MXC
+   depends on DRM && ARCH_MXC && ARM64
help
  Choose this if you have a NXP i.MX8MQ based system and want to use the
  Display Controller Subsystem. This option enables DCSS support.
-- 
2.17.1

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Re: per-plane LUTs and CSCs?

[Laurentiu Palcu]

Hi Pekka,

On Thu, Sep 10, 2020 at 11:50:26AM +0300, Pekka Paalanen wrote:
> On Thu, 10 Sep 2020 09:52:26 +0200
> Daniel Vetter  wrote:
> 
> > On Thu, Sep 10, 2020 at 10:25:43AM +0300, Pekka Paalanen wrote:
> > > On Wed, 9 Sep 2020 13:57:28 +0300
> > > Laurentiu Palcu  wrote:
> > >   
> > > > Hi all,
> > > > 
> > > > I was wondering whether you could give me an advise on how to proceed 
> > > > further
> > > > with the following issue as I'm preparing to upstream the next set of 
> > > > patches
> > > > for the iMX8MQ display controller(DCSS). The display controller has 3 
> > > > planes,
> > > > each with 2 CSCs and one degamma LUT. The CSCs are in front and after 
> > > > the LUT
> > > > respectively. Then the output from those 3 pipes is blended together 
> > > > and then
> > > > gamma correction is applied using a linear-to-nonlinear LUT and another 
> > > > CSC, if
> > > > needed.
> 
> Hi,
> 
> hmm, so FB -> CSC -> LUT -> CSC -> blending?
> 
> Is it then
>   blending -> LUT -> CSC -> encoder
> or
>   blending -> CSC -> LUT -> encoder?

The DCSS pipeline topology is this:

FB1->CSC_A->LUT->CSC_B-\
FB2->CSC_A->LUT->CSC_B-|-blender->LUT->CSC_O->encoder
FB3->CSC_A->LUT->CSC_B-/

Basically, CSC_A is used to convert to a common colorspace if needed
(YUV->RGB) as well as to perform pixel range conversions: limited->full.
CSC_B is for gamut conversions(like 709->2020). The CSC_O is used to
convert to the colorspace used by the output (like RGB->YUV).

> 
> Are all these LUTs per-channel 1D LUTs or something else?

LUTs are 3D, per pixel component.

Thanks,
laurentiu

> 
> What ever the KMS UAPI for these is going to be looking like, it
> obviously needs to define all this. So I'm guessing we need to define
> the abstract color pipeline of KMS in general that includes everything
> any driver might want to expose. Then each driver picks the blocks in
> the pipeline it wants to expose and the other blocks are assumed to be
> "identity transform".
> 
> Without such general abstract color pipeline defined and documented it
> is very unlikely IMO for generic userspace to make use of the driver
> features.
> 
> All blocks must also default to identity transform. A block
> unimplemented by a driver is the same as a block not used or understood
> by a KMS client.
> 
> Userspace that does not understand all the blocks will need to use the
> "harmless default values". This then ties in with what I've discussed
> with danvet before: when you are VT-switching from one KMS client to
> another, how do you reset the full KMS state (including blocks you
> don't understand) to the same state you had before. The other KMS
> client may have messed them up while you were gone.
> 
> All this default value talk is to ensure that the abstract KMS color
> pipeline can be extended without breaking existing userspace.
> 
> ...
> 
> > > > So, how should I continue with this one? Any pointers?  
> > > 
> > > Hi,
> > > 
> > > I can't help you, but I can say that we are currently in the process of
> > > designing a color management and HDR extension for Wayland, and I'm
> > > sure in the long term I would like to use per-plane color space
> > > transformation features of KMS in Weston eventually.
> > > 
> > > IOW, one more userspace that is going to be taking advantage of such
> > > features as long as they are not too driver-specific.  
> > 
> > Personally I think best to wait for userspace to come up with color
> > manager protocols, that should give us a much clearer idea of what the
> > kernel interface should look like. Since hw is pretty special in this
> > area, I expect we'll have to do a bunch of impendendance mismatching in
> > the kernel anyway.
> 
> Speaking of that, where should we scream if we feel like we are missing
> KMS properties to get the best out of color management and HDR in
> Weston, assuming we're not kernel devs?
> 
> Who to Cc?
> 
> We currently have intel and AMD hardware at hand if that makes any
> difference.
> 
> 
> Thanks,
> pq


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Re: [PATCH v9 0/5] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

Hi Daniel,

On Thu, Sep 10, 2020 at 08:47:34AM +0200, Daniel Vetter wrote:
> On Wed, Sep 9, 2020 at 5:03 PM Lucas Stach  wrote:
> >
> > Hi Laurentiu,
> >
> > On Mo, 2020-08-31 at 14:24 +0300, Laurentiu Palcu wrote:
> > > Hi Lucas, Sam,
> > >
> > > On Mon, Aug 31, 2020 at 12:37:23PM +0200, Lucas Stach wrote:
> > > > Hi Laurentiu,
> > > >
> > > > On Fr, 2020-08-28 at 11:36 +0300, Laurentiu Palcu wrote:
> > > > > Hi Lucas,
> > > > >
> > > > > I was wondering about the plans to merge this series. Since not many
> > > > > people can test it properly due to lack of DCSS support in the 
> > > > > upstream
> > > > > NWL driver (which I heard it's coming soon) and a completely 
> > > > > nonexistent
> > > > > HDP driver, are we going to take a leap of faith and merge it as is? 
> > > > > Or
> > > > > should we wait?
> > > >
> > > > I think even if the bridges aren't ready yet, the driver is in a good
> > > > enough shape to merge it. There's no point in letting it accumulate
> > > > bitrot while waiting for the bridges to land. Also I guess it will make
> > > > bridge driver development a lot easier when the DCSS driver is in-tree.
> > >
> > > OK, fair enough.
> > >
> > > > > As to who is going to do the actual merge, I know we had a brief
> > > > > discussion about it some time ago and I was supposed to apply for
> > > > > drm-misc rights, however it feels a little awkward to merge my own
> > > > > code... :) Though, I might not even qualify for drm-misc rights 
> > > > > anyway,
> > > > > considering I haven't been very active in this area... :/
> > > >
> > > > Please consider applying for drm-misc merge rights. Even if you don't
> > > > do the initial merge I think it will come in handy in the long run.
> > >
> > > OK, I'll apply for drm-misc rights. Sam also encouraged me to do this in
> > > a previous email. Since this series will be followed by a bunch of other
> > > patches, enabling support for video planes, among other things, I guess
> > > I'll need the rights anyway.
> > >
> > > > > On that note, I will probably need help with the merging, provided 
> > > > > it's
> > > > > still happenning. Will you be able to help me out with this?
> > > >
> > > > Sure, I'm having some time available this week. I'll give this v9
> > > > another spin on my boards and will do the merge after that.
> > >
> > > Thanks Lucas. As a matter of fact, after Sam's email, I was preparing a
> > > v10 after rebasing to latest drm-next. However, no conflicts were 
> > > encountered
> > > and the v9 series applied cleanly. Let me know if you encounter any
> > > issues and I can resend it.
> >
> > I've tested this together with a hacked up eDP bridge driver stack on
> > my boards. The testing hasn't been really in-depth, but things seem to
> > work fine. I have now pushed the whole series into drm-misc-next.
> 
> Something doesn't compile too well
> 
> ERROR: modpost: "__aeabi_ldivmod"
> [drivers/gpu/drm/imx/dcss/imx-dcss.ko] undefined!
> ERROR: modpost: "__aeabi_uldivmod"
> [drivers/gpu/drm/imx/dcss/imx-dcss.ko] undefined!

Oops... :/ I guess we need an ARM64 dependency in Kconfig. No
32bit NXP SoC uses this particular display controller. So, that should
fix the compilation issue on 32bit.

I'll send a fix shortly.

Thanks,
laurentiu

> 
> Cheers, Daniel
> >
> > Regards,
> > Lucas
> >
> > > Thanks,
> > > Laurentiu
> > >
> > > > Regards,
> > > > Lucas
> > > >
> > > > > Thanks,
> > > > > laurentiu
> > > > >
> > > > > On Fri, Jul 31, 2020 at 11:18:28AM +0300, Laurentiu Palcu wrote:
> > > > > > From: Laurentiu Palcu 
> > > > > >
> > > > > > Hi,
> > > > > >
> > > > > > This patchset adds initial DCSS support for iMX8MQ chip. Initial 
> > > > > > support
> > > > > > includes only graphics plane support (no video planes), no HDR10 
> > > > > > capabilities,
> > > > > > no graphics decompression (only linear, tiled and super-tiled 
> > > > > > buffers allowed).
> > > > > >
> > > > &g

per-plane LUTs and CSCs?

[Laurentiu Palcu]

Hi all,

I was wondering whether you could give me an advise on how to proceed further
with the following issue as I'm preparing to upstream the next set of patches
for the iMX8MQ display controller(DCSS). The display controller has 3 planes,
each with 2 CSCs and one degamma LUT. The CSCs are in front and after the LUT
respectively. Then the output from those 3 pipes is blended together and then
gamma correction is applied using a linear-to-nonlinear LUT and another CSC, if
needed.

Currently, downstream, we have all those CSCs and LUTs hard-coded into a header
file. Based on the colorspace, range, gamut selected for the output and/or
plane input, we pick up the right CSCs and LUTs from that header file to
configure our pipes... I guess this solution does the job, userspace doesn't
need to care much about how to generate those tables. But, it's also not very
flexible in case there is an app smart enough to know and actually generate
their own custom tables. :/

Looking through the dri-devel archives, I've seen that there was a tentative to
implement a more or less generic per-plane LUT/CSC solution but it didn't make
it in due to lack of userspace consumers...

Adding CSC and degamma LUT properties for each plane as well as a gamma
LUT and CSC for CRTC, would help get rid of the LUT/CSC header and rely
entirely on userspace to fill in those tables. But userspace has to know
how to generate those LUTs and colorspace conversion matrices in the
first place...

So, how should I continue with this one? Any pointers?

Thanks,
Laurentiu
___
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dri-devel@lists.freedesktop.org
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Re: [PATCH v9 0/5] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

Hi Lucas, Sam,

On Mon, Aug 31, 2020 at 12:37:23PM +0200, Lucas Stach wrote:
> Hi Laurentiu,
> 
> On Fr, 2020-08-28 at 11:36 +0300, Laurentiu Palcu wrote:
> > Hi Lucas,
> > 
> > I was wondering about the plans to merge this series. Since not many
> > people can test it properly due to lack of DCSS support in the upstream
> > NWL driver (which I heard it's coming soon) and a completely nonexistent
> > HDP driver, are we going to take a leap of faith and merge it as is? Or
> > should we wait?
> 
> I think even if the bridges aren't ready yet, the driver is in a good
> enough shape to merge it. There's no point in letting it accumulate
> bitrot while waiting for the bridges to land. Also I guess it will make
> bridge driver development a lot easier when the DCSS driver is in-tree.

OK, fair enough.

> 
> > As to who is going to do the actual merge, I know we had a brief
> > discussion about it some time ago and I was supposed to apply for
> > drm-misc rights, however it feels a little awkward to merge my own
> > code... :) Though, I might not even qualify for drm-misc rights anyway,
> > considering I haven't been very active in this area... :/
> 
> Please consider applying for drm-misc merge rights. Even if you don't
> do the initial merge I think it will come in handy in the long run.

OK, I'll apply for drm-misc rights. Sam also encouraged me to do this in
a previous email. Since this series will be followed by a bunch of other
patches, enabling support for video planes, among other things, I guess
I'll need the rights anyway.

> 
> > On that note, I will probably need help with the merging, provided it's
> > still happenning. Will you be able to help me out with this?
> 
> Sure, I'm having some time available this week. I'll give this v9
> another spin on my boards and will do the merge after that.

Thanks Lucas. As a matter of fact, after Sam's email, I was preparing a
v10 after rebasing to latest drm-next. However, no conflicts were encountered
and the v9 series applied cleanly. Let me know if you encounter any
issues and I can resend it.

Thanks,
Laurentiu

> 
> Regards,
> Lucas
> 
> > Thanks,
> > laurentiu
> > 
> > On Fri, Jul 31, 2020 at 11:18:28AM +0300, Laurentiu Palcu wrote:
> > > From: Laurentiu Palcu 
> > > 
> > > Hi,
> > > 
> > > This patchset adds initial DCSS support for iMX8MQ chip. Initial support
> > > includes only graphics plane support (no video planes), no HDR10 
> > > capabilities,
> > > no graphics decompression (only linear, tiled and super-tiled buffers 
> > > allowed).
> > > 
> > > Support for the rest of the features will be added incrementally, in 
> > > subsequent
> > > patches.
> > > 
> > > The patchset was tested with both HDP driver (in the downstream tree) and 
> > > the upstream
> > > MIPI-DSI driver (with a couple of patches on top, to make it work 
> > > correctly with DCSS).
> > > 
> > > Thanks,
> > > Laurentiu
> > > 
> > > Changes in v9:
> > >  * Fixed a compilation issue found by Guido in his setup: 'select
> > >VIDEOMODE_HELPERS' was missing from Kconfig;
> > >  * Use imx8mq-clock.h in the bindings file so one can understand what
> > >those clock values mean;
> > >  * no other changes done. Couldn't address the hang Guido reported as
> > >it's not happening in my setup. However, in my tree, there are some
> > >extra NWL and ADV patches applied on top of upstream ones... Also,
> > >removing them and testing only with upstream, even if there's no
> > >image out, does not produce a hang... :/
> > > 
> > > Changes in v8:
> > >  * Removed 'select RESET_CONTROLLER" from Kconfig as Philipp pointed
> > >out. SRC is not used in DCSS driver;
> > >  * Nothing else changed;
> > > 
> > > Changes in v7:
> > >  * Added a patch to initialize the connector using the 
> > > drm_bridge_connector
> > >API as Sam suggested. Tested it using NWL_DSI and ADV7535 with
> > >Guido's patch [1] applied and one fix for ADV [2]. Also, some extra
> > >patches for ADV and NWL were needed, from our downstream tree, which
> > >will be upstreamed soon by their author;
> > >  * Rest of the patches are untouched;
> > > 
> > > [1] https://lists.freedesktop.org/archives/dri-devel/2020-July/273025.html
> > > [2] https://lists.freedesktop.org/archives/dri-devel/2020-July/273132.html
> > > 
> > > Changes in v6:
> > >  * Addressed Rob's 

Re: [PATCH v9 0/5] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

Hi Lucas,

I was wondering about the plans to merge this series. Since not many
people can test it properly due to lack of DCSS support in the upstream
NWL driver (which I heard it's coming soon) and a completely nonexistent
HDP driver, are we going to take a leap of faith and merge it as is? Or
should we wait?

As to who is going to do the actual merge, I know we had a brief
discussion about it some time ago and I was supposed to apply for
drm-misc rights, however it feels a little awkward to merge my own
code... :) Though, I might not even qualify for drm-misc rights anyway,
considering I haven't been very active in this area... :/

On that note, I will probably need help with the merging, provided it's
still happenning. Will you be able to help me out with this?

Thanks,
laurentiu

On Fri, Jul 31, 2020 at 11:18:28AM +0300, Laurentiu Palcu wrote:
> From: Laurentiu Palcu 
> 
> Hi,
> 
> This patchset adds initial DCSS support for iMX8MQ chip. Initial support
> includes only graphics plane support (no video planes), no HDR10 capabilities,
> no graphics decompression (only linear, tiled and super-tiled buffers 
> allowed).
> 
> Support for the rest of the features will be added incrementally, in 
> subsequent
> patches.
> 
> The patchset was tested with both HDP driver (in the downstream tree) and the 
> upstream
> MIPI-DSI driver (with a couple of patches on top, to make it work correctly 
> with DCSS).
> 
> Thanks,
> Laurentiu
> 
> Changes in v9:
>  * Fixed a compilation issue found by Guido in his setup: 'select
>VIDEOMODE_HELPERS' was missing from Kconfig;
>  * Use imx8mq-clock.h in the bindings file so one can understand what
>those clock values mean;
>  * no other changes done. Couldn't address the hang Guido reported as
>it's not happening in my setup. However, in my tree, there are some
>extra NWL and ADV patches applied on top of upstream ones... Also,
>removing them and testing only with upstream, even if there's no
>image out, does not produce a hang... :/
> 
> Changes in v8:
>  * Removed 'select RESET_CONTROLLER" from Kconfig as Philipp pointed
>out. SRC is not used in DCSS driver;
>  * Nothing else changed;
> 
> Changes in v7:
>  * Added a patch to initialize the connector using the drm_bridge_connector
>API as Sam suggested. Tested it using NWL_DSI and ADV7535 with
>Guido's patch [1] applied and one fix for ADV [2]. Also, some extra
>patches for ADV and NWL were needed, from our downstream tree, which
>will be upstreamed soon by their author;
>  * Rest of the patches are untouched;
> 
> [1] https://lists.freedesktop.org/archives/dri-devel/2020-July/273025.html
> [2] https://lists.freedesktop.org/archives/dri-devel/2020-July/273132.html
> 
> Changes in v6:
>  * Addressed Rob's comment and added "additionalProperties: false" at
>the end of the bindings' properties. However, this change surfaced
>an issue with the assigned-clock* properties not being documented in
>the properties section. Added the descriptions and the bindings patch
>will need another review;
>  * Added an entry for DCSS driver in the MAINTAINERS file;
>  * Removed the component framework patch altogether;
> 
> Changes in v5:
>  * Rebased to latest;
>  * Took out component framework support and made it a separate patch so
>that people can still test with HDP driver, which makes use of it.
>But the idea is to get rid of it once HDP driver's next versions
>will remove component framework as well;
>  * Slight improvement to modesetting: avoid cutting off the pixel clock
>if the new mode and the old one are equal. Also, in this case, is
>not necessary to wait for DTG to shut off. This would allow to switch
>from 8b RGB to 12b YUV422, for example, with no interruptions (at least
>from DCSS point of view);
>  * Do not fire off CTXLD when going to suspend, unless it still has
>entries that need to be committed to DCSS;
>  * Addressed Rob's comments on bindings;
> 
> Changes in v4:
>  * Addressed Lucas and Philipp's comments:
>* Added DRM_KMS_CMA_HELPER dependency in Kconfig;
>* Removed usage of devm_ functions since I'm already doing all the
>  clean-up in the submodules_deinit();
>* Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush();
>* Removed en_completion variable from dcss_crtc since this was
>  introduced mainly to avoid vblank timeout warnings which were fixed
>  by arming the vblank event in flush() instead of begin();
>* Removed clks_on and irq_enabled flags since all the calls to
>  enabling/disabling clocks and interrupts were balanced;
>* Removed the custom atomic_commit callback and used the DRM core
>  helpe

[PATCH v9 3/5] drm/imx/dcss: use drm_bridge_connector API

[Laurentiu Palcu]

From: Laurentiu Palcu 

Make use of drm_bridge_connector API to have the connector initialized by the
display controller.

Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/imx/dcss/dcss-dev.c | 17 +---
 drivers/gpu/drm/imx/dcss/dcss-kms.c | 31 -
 drivers/gpu/drm/imx/dcss/dcss-kms.h |  1 +
 3 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
b/drivers/gpu/drm/imx/dcss/dcss-dev.c
index 83a4840435cf..c849533ca83e 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
@@ -8,9 +8,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 
 #include "dcss-dev.h"
+#include "dcss-kms.h"
 
 static void dcss_clocks_enable(struct dcss_dev *dcss)
 {
@@ -247,9 +250,13 @@ void dcss_dev_destroy(struct dcss_dev *dcss)
 int dcss_dev_suspend(struct device *dev)
 {
struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
+   struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
+   struct dcss_kms_dev *kms = container_of(ddev, struct dcss_kms_dev, 
base);
int ret;
 
-   drm_mode_config_helper_suspend(dcss_drv_dev_to_drm(dev));
+   drm_bridge_connector_disable_hpd(kms->connector);
+
+   drm_mode_config_helper_suspend(ddev);
 
if (pm_runtime_suspended(dev))
return 0;
@@ -266,9 +273,11 @@ int dcss_dev_suspend(struct device *dev)
 int dcss_dev_resume(struct device *dev)
 {
struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
+   struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
+   struct dcss_kms_dev *kms = container_of(ddev, struct dcss_kms_dev, 
base);
 
if (pm_runtime_suspended(dev)) {
-   drm_mode_config_helper_resume(dcss_drv_dev_to_drm(dev));
+   drm_mode_config_helper_resume(ddev);
return 0;
}
 
@@ -278,7 +287,9 @@ int dcss_dev_resume(struct device *dev)
 
dcss_ctxld_resume(dcss->ctxld);
 
-   drm_mode_config_helper_resume(dcss_drv_dev_to_drm(dev));
+   drm_mode_config_helper_resume(ddev);
+
+   drm_bridge_connector_enable_hpd(kms->connector);
 
return 0;
 }
diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
b/drivers/gpu/drm/imx/dcss/dcss-kms.c
index 3ca49d0a3e61..135a62366ab8 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
@@ -5,6 +5,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -74,7 +75,7 @@ static const struct drm_encoder_funcs 
dcss_kms_simple_encoder_funcs = {
.destroy = drm_encoder_cleanup,
 };
 
-static int dcss_kms_setup_encoder(struct dcss_kms_dev *kms)
+static int dcss_kms_bridge_connector_init(struct dcss_kms_dev *kms)
 {
struct drm_device *ddev = >base;
struct drm_encoder *encoder = >encoder;
@@ -103,7 +104,23 @@ static int dcss_kms_setup_encoder(struct dcss_kms_dev *kms)
return ret;
}
 
-   return drm_bridge_attach(encoder, bridge, NULL, 0);
+   ret = drm_bridge_attach(encoder, bridge, NULL,
+   DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+   if (ret < 0) {
+   dev_err(ddev->dev, "Unable to attach bridge %pOF\n",
+   bridge->of_node);
+   return ret;
+   }
+
+   kms->connector = drm_bridge_connector_init(ddev, encoder);
+   if (IS_ERR(kms->connector)) {
+   dev_err(ddev->dev, "Unable to create bridge connector.\n");
+   return PTR_ERR(kms->connector);
+   }
+
+   drm_connector_attach_encoder(kms->connector, encoder);
+
+   return 0;
 }
 
 struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
@@ -131,18 +148,20 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev 
*dcss)
 
drm->irq_enabled = true;
 
-   ret = dcss_crtc_init(crtc, drm);
+   ret = dcss_kms_bridge_connector_init(kms);
if (ret)
goto cleanup_mode_config;
 
-   ret = dcss_kms_setup_encoder(kms);
+   ret = dcss_crtc_init(crtc, drm);
if (ret)
-   goto cleanup_crtc;
+   goto cleanup_mode_config;
 
drm_mode_config_reset(drm);
 
drm_kms_helper_poll_init(drm);
 
+   drm_bridge_connector_enable_hpd(kms->connector);
+
ret = drm_dev_register(drm, 0);
if (ret)
goto cleanup_crtc;
@@ -152,6 +171,7 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
return kms;
 
 cleanup_crtc:
+   drm_bridge_connector_disable_hpd(kms->connector);
drm_kms_helper_poll_fini(drm);
dcss_crtc_deinit(crtc, drm);
 
@@ -167,6 +187,7 @@ void dcss_kms_detach(struct dcss_kms_dev *kms)
struct drm_device *drm = >base;
 
drm_dev_unregister(drm);
+   drm_bridge_connector_disable_hpd(kms->connector);
drm_kms_helper_poll_fini(drm);
drm_atomic_helper_shutdown(d

[PATCH v9 0/5] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

From: Laurentiu Palcu 

Hi,

This patchset adds initial DCSS support for iMX8MQ chip. Initial support
includes only graphics plane support (no video planes), no HDR10 capabilities,
no graphics decompression (only linear, tiled and super-tiled buffers allowed).

Support for the rest of the features will be added incrementally, in subsequent
patches.

The patchset was tested with both HDP driver (in the downstream tree) and the 
upstream
MIPI-DSI driver (with a couple of patches on top, to make it work correctly 
with DCSS).

Thanks,
Laurentiu

Changes in v9:
 * Fixed a compilation issue found by Guido in his setup: 'select
   VIDEOMODE_HELPERS' was missing from Kconfig;
 * Use imx8mq-clock.h in the bindings file so one can understand what
   those clock values mean;
 * no other changes done. Couldn't address the hang Guido reported as
   it's not happening in my setup. However, in my tree, there are some
   extra NWL and ADV patches applied on top of upstream ones... Also,
   removing them and testing only with upstream, even if there's no
   image out, does not produce a hang... :/

Changes in v8:
 * Removed 'select RESET_CONTROLLER" from Kconfig as Philipp pointed
   out. SRC is not used in DCSS driver;
 * Nothing else changed;

Changes in v7:
 * Added a patch to initialize the connector using the drm_bridge_connector
   API as Sam suggested. Tested it using NWL_DSI and ADV7535 with
   Guido's patch [1] applied and one fix for ADV [2]. Also, some extra
   patches for ADV and NWL were needed, from our downstream tree, which
   will be upstreamed soon by their author;
 * Rest of the patches are untouched;

[1] https://lists.freedesktop.org/archives/dri-devel/2020-July/273025.html
[2] https://lists.freedesktop.org/archives/dri-devel/2020-July/273132.html

Changes in v6:
 * Addressed Rob's comment and added "additionalProperties: false" at
   the end of the bindings' properties. However, this change surfaced
   an issue with the assigned-clock* properties not being documented in
   the properties section. Added the descriptions and the bindings patch
   will need another review;
 * Added an entry for DCSS driver in the MAINTAINERS file;
 * Removed the component framework patch altogether;

Changes in v5:
 * Rebased to latest;
 * Took out component framework support and made it a separate patch so
   that people can still test with HDP driver, which makes use of it.
   But the idea is to get rid of it once HDP driver's next versions
   will remove component framework as well;
 * Slight improvement to modesetting: avoid cutting off the pixel clock
   if the new mode and the old one are equal. Also, in this case, is
   not necessary to wait for DTG to shut off. This would allow to switch
   from 8b RGB to 12b YUV422, for example, with no interruptions (at least
   from DCSS point of view);
 * Do not fire off CTXLD when going to suspend, unless it still has
   entries that need to be committed to DCSS;
 * Addressed Rob's comments on bindings;

Changes in v4:
 * Addressed Lucas and Philipp's comments:
   * Added DRM_KMS_CMA_HELPER dependency in Kconfig;
   * Removed usage of devm_ functions since I'm already doing all the
 clean-up in the submodules_deinit();
   * Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush();
   * Removed en_completion variable from dcss_crtc since this was
 introduced mainly to avoid vblank timeout warnings which were fixed
 by arming the vblank event in flush() instead of begin();
   * Removed clks_on and irq_enabled flags since all the calls to
 enabling/disabling clocks and interrupts were balanced;
   * Removed the custom atomic_commit callback and used the DRM core
 helper and, in the process, got rid of a workqueue that wasn't
 necessary anymore;
   * Fixed some minor DT binding issues flagged by Philipp;
   * Some other minor changes suggested by Lucas;
 * Removed YUV formats from the supported formats as these cannot work
   without the HDR10 module CSCs and LUTs. Will add them back when I
   will add support for video planes;

Changes in v3:
 * rebased to latest linux-next and made it compile as drmP.h was
   removed;
 * removed the patch adding the VIDEO2_PLL clock. It's already applied;
 * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set();
 * fixed a a spurious hang reported by Lukas Hartmann and encountered
   by me several times;
 * mask DPR and DTG interrupts by default, as they may come enabled from
   U-boot;

Changes in v2:
 * Removed '0x' in node's unit-address both in DT and yaml;
 * Made the address region size lowercase, to be consistent;
 * Removed some left-over references to P010;
 * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence 
compilation
   issues reported by kbuild for other architectures;


Laurentiu Palcu (5):
  drm/imx: compile imx directory by default
  drm/imx: Add initial support for DCSS on iMX8MQ
  drm/imx/dcss: use drm_bridge_connector API
  MAINTAINERS:

[PATCH v9 2/5] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

From: Laurentiu Palcu 

This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
Some of its capabilities include:
 * 4K@60fps;
 * HDR10;
 * one graphics and 2 video pipelines;
 * on-the-fly decompression of compressed video and graphics;

The reference manual can be found here:
https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM

The current patch adds only basic functionality: one primary plane for
graphics, linear, tiled and super-tiled buffers support (no graphics
decompression yet), no HDR10 and no video planes.

Video planes support and HDR10 will be added in subsequent patches once
per-plane de-gamma/CSC/gamma support is in.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Lucas Stach 
---
 drivers/gpu/drm/imx/Kconfig|   2 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig   |   9 +
 drivers/gpu/drm/imx/dcss/Makefile  |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  70 +++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 219 +++
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 424 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c| 314 ++
 drivers/gpu/drm/imx/dcss/dcss-dev.h| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-dpr.c| 562 +
 drivers/gpu/drm/imx/dcss/dcss-drv.c| 138 +
 drivers/gpu/drm/imx/dcss/dcss-dtg.c| 409 
 drivers/gpu/drm/imx/dcss/dcss-kms.c| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-kms.h|  43 ++
 drivers/gpu/drm/imx/dcss/dcss-plane.c  | 405 
 drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
 drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++
 17 files changed, 3962 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..6231048aa5aa 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,5 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+source "drivers/gpu/drm/imx/dcss/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..b644deffe948 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
diff --git a/drivers/gpu/drm/imx/dcss/Kconfig b/drivers/gpu/drm/imx/dcss/Kconfig
new file mode 100644
index ..69860de8861f
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Kconfig
@@ -0,0 +1,9 @@
+config DRM_IMX_DCSS
+   tristate "i.MX8MQ DCSS"
+   select IMX_IRQSTEER
+   select DRM_KMS_CMA_HELPER
+   select VIDEOMODE_HELPERS
+   depends on DRM && ARCH_MXC
+   help
+ Choose this if you have a NXP i.MX8MQ based system and want to use the
+ Display Controller Subsystem. This option enables DCSS support.
diff --git a/drivers/gpu/drm/imx/dcss/Makefile 
b/drivers/gpu/drm/imx/dcss/Makefile
new file mode 100644
index ..8c7c8da42792
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Makefile
@@ -0,0 +1,6 @@
+imx-dcss-objs := dcss-drv.o dcss-dev.o dcss-blkctl.o dcss-ctxld.o dcss-dtg.o \
+dcss-ss.o dcss-dpr.o dcss-scaler.o dcss-kms.o 
dcss-crtc.o \
+dcss-plane.o
+
+obj-$(CONFIG_DRM_IMX_DCSS) += imx-dcss.o
+
diff --git a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c 
b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
new file mode 100644
index ..c9b54bb2692d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP.
+ */
+
+#include 
+#include 
+#include 
+
+#include "dcss-dev.h"
+
+#define DCSS_BLKCTL_RESET_CTRL 0x00
+#define   B_CLK_RESETN BIT(0)
+#define   APB_CLK_RESETN   BIT(1)
+#define   P_CLK_RESETN BIT(2)
+#define   RTR_CLK_RESETN   BIT(4)
+#define DCSS_BLKCTL_CONTROL0   0x10
+#define   HDMI_M

[PATCH v9 1/5] drm/imx: compile imx directory by default

[Laurentiu Palcu]

From: Laurentiu Palcu 

Currently the drm/imx/ directory is compiled only if DRM_IMX is set. Adding a
new IMX related IP in the same directory would need DRM_IMX to be set, which 
would
bring in also IPUv3 core driver...

The current patch would allow adding new IPs in the imx/ directory without 
needing
to set DRM_IMX.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Lucas Stach 
---
 drivers/gpu/drm/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 2f31579f91d4..81569009f884 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -100,7 +100,7 @@ obj-$(CONFIG_DRM_MSM) += msm/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-$(CONFIG_DRM_STM) += stm/
 obj-$(CONFIG_DRM_STI) += sti/
-obj-$(CONFIG_DRM_IMX) += imx/
+obj-y  += imx/
 obj-$(CONFIG_DRM_INGENIC) += ingenic/
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
 obj-$(CONFIG_DRM_MESON)+= meson/
-- 
2.23.0

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[PATCH v9 5/5] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

From: Laurentiu Palcu 

Add bindings for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu 
---
Changes in v9:
 * Include imx8mq-clock.h in the example so we can use clock names
   instead of their values;

 .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 108 ++
 1 file changed, 108 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 
b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
new file mode 100644
index ..f1f25aa794d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: iMX8MQ Display Controller Subsystem (DCSS)
+
+maintainers:
+  - Laurentiu Palcu 
+
+description:
+
+  The DCSS (display controller sub system) is used to source up to three
+  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
+  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
+  image processing capabilities are included to provide a solution capable of
+  driving next generation high dynamic range displays.
+
+properties:
+  compatible:
+const: nxp,imx8mq-dcss
+
+  reg:
+items:
+  - description: DCSS base address and size, up to IRQ steer start
+  - description: DCSS BLKCTL base address and size
+
+  interrupts:
+items:
+  - description: Context loader completion and error interrupt
+  - description: DTG interrupt used to signal context loader trigger time
+  - description: DTG interrupt for Vblank
+
+  interrupt-names:
+items:
+  - const: ctxld
+  - const: ctxld_kick
+  - const: vblank
+
+  clocks:
+items:
+  - description: Display APB clock for all peripheral PIO access interfaces
+  - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
+  - description: RTRAM clock
+  - description: Pixel clock, can be driven either by HDMI phy clock or 
MIPI
+  - description: DTRC clock, needed by video decompressor
+
+  clock-names:
+items:
+  - const: apb
+  - const: axi
+  - const: rtrm
+  - const: pix
+  - const: dtrc
+
+  assigned-clocks:
+items:
+  - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
+  - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
+  - description: Phandle and clock specifier of either 
IMX8MQ_VIDEO2_PLL1_REF_SEL or
+ IMX8MQ_VIDEO_PLL1_REF_SEL
+
+  assigned-clock-parents:
+items:
+  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+  - description: Phandle and clock specifier of IMX8MQ_CLK_27M
+
+  assigned-clock-rates:
+items:
+  - description: Must be 800 MHz
+  - description: Must be 400 MHz
+
+  port:
+type: object
+description:
+  A port node pointing to the input port of a HDMI/DP or MIPI display 
bridge.
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+dcss: display-controller@32e0 {
+compatible = "nxp,imx8mq-dcss";
+reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+interrupts = <6>, <8>, <9>;
+interrupt-names = "ctxld", "ctxld_kick", "vblank";
+interrupt-parent = <>;
+clocks = < IMX8MQ_CLK_DISP_APB_ROOT>, < 
IMX8MQ_CLK_DISP_AXI_ROOT>,
+ < IMX8MQ_CLK_DISP_RTRM_ROOT>, < 
IMX8MQ_VIDEO2_PLL_OUT>,
+ < IMX8MQ_CLK_DISP_DTRC>;
+clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+assigned-clocks = < IMX8MQ_CLK_DISP_AXI>, < 
IMX8MQ_CLK_DISP_RTRM>,
+  < IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+assigned-clock-parents = < IMX8MQ_SYS1_PLL_800M>, < 
IMX8MQ_SYS1_PLL_800M>,
+ < IMX8MQ_CLK_27M>;
+assigned-clock-rates = <8>,
+   <4>;
+port {
+dcss_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
-- 
2.23.0

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[PATCH v9 4/5] MAINTAINERS: Add entry for i.MX 8MQ DCSS driver

[Laurentiu Palcu]

From: Laurentiu Palcu 

The driver is part of DRM subsystem and is located in drivers/gpu/drm/imx/dcss.

Signed-off-by: Laurentiu Palcu 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2c669c07fa35..1a22038f2869 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12281,6 +12281,14 @@ F: drivers/iio/gyro/fxas21002c_core.c
 F: drivers/iio/gyro/fxas21002c_i2c.c
 F: drivers/iio/gyro/fxas21002c_spi.c
 
+NXP i.MX 8MQ DCSS DRIVER
+M: Laurentiu Palcu 
+R: Lucas Stach 
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+F: Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
+F: drivers/gpu/drm/imx/dcss/
+
 NXP SGTL5000 DRIVER
 M: Fabio Estevam 
 L: alsa-de...@alsa-project.org (moderated for non-subscribers)
-- 
2.23.0

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Re: [PATCH v8 0/5] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

Hi Guido,

On Wed, Jul 29, 2020 at 05:09:52PM +0200, Guido Günther wrote:
> Hi,
> On Wed, Jul 29, 2020 at 05:16:47PM +0300, Laurentiu Palcu wrote:
> > Hi Guido,
> > 
> > On Wed, Jul 29, 2020 at 03:59:48PM +0200, Guido Günther wrote:
> > > Hi,
> > > On Fri, Jul 24, 2020 at 12:07:29PM +0300, Laurentiu Palcu wrote:
> > > > From: Laurentiu Palcu 
> > > > 
> > > > Hi,
> > > > 
> > > > This patchset adds initial DCSS support for iMX8MQ chip. Initial support
> > > > includes only graphics plane support (no video planes), no HDR10 
> > > > capabilities,
> > > > no graphics decompression (only linear, tiled and super-tiled buffers 
> > > > allowed).
> > > > 
> > > > Support for the rest of the features will be added incrementally, in 
> > > > subsequent
> > > > patches.
> > > > 
> > > > The patchset was tested with both HDP driver (in the downstream tree) 
> > > > and the upstream
> > > > MIPI-DSI driver (with a couple of patches on top, to make it work
> > > > correctly with DCSS).
> > > 
> > > While i could run earlier versions of this  series with NWL I'm seeing
> > > only a brief image that then turns black (backlight still on) with this 
> > > current version and
> > > the board hangs soon after.(for reference using mxsfb works nicely with
> > > the very same DT on next-20200727). If I do a drm.debug=0x3f i can see
> > > that display output stops around:
> > > 
> > > [   15.394473] imx-dcss 32e0.display-controller: 
> > > [drm:drm_update_vblank_count] updating vblank count on crtc 0: 
> > > current=22, diff=1, hw=0 hw_last=0
> > > [   15.397575] device: 'input1': device_add
> > > [   15.444658] imx-dcss 32e0.display-controller: 
> > > [drm:drm_update_vblank_count] updating vblank count on crtc 0: 
> > > current=23, diff=1, hw=0 hw_last=0
> > > [   15.465946] PM: Adding info for No Bus:input1
> > > [   15.494842] imx-dcss 32e0.display-controller: 
> > > [drm:drm_update_vblank_count] updating vblank count on crtc 0: 
> > > current=24, diff=1, hw=0 hw_last=0
> > > [   15.511694] input: gpio-keys as 
> > > /devices/platform/gpio-keys/input/input1
> > > [   15.545025] imx-dcss 32e0.display-controller: 
> > > [drm:drm_update_vblank_count] updating vblank count on crtc 0: 
> > > current=25, diff=1, hw=0 hw_last=0
> > > [   15.557869] device: 'event1': device_add
> > > [   15.595209] imx-dcss 32e0.display-controller: 
> > > [drm:drm_update_vblank_count] updating vblank count on crtc 0: 
> > > current=26, diff=1, hw=0 hw_last=0
> > > [   15.605363] PM: Adding info for No Bus:event1
> > > [   15.645394] imx-dcss 32e0.display-controller: 
> > > [drm:drm_update_vblank_count] updating vblank count on crtc 0: 
> > > current=27, diff=1, hw=0 hw_last=0
> > > [   19.427039] imx-dcss 32e0.display-controller: 
> > > [drm:vblank_disable_fn] disabling vblank on crtc 0
> > > [   19.436135] device: 'wakeup6': device_add
> > > [   19.448202] imx-dcss 32e0.display-controller: 
> > > [drm:drm_update_vblank_count] updating vblank count on crtc 0: 
> > > current=28, diff=0, hw=0 hw_last=0
> > > 
> > > (and there's no further logging from drm from there on).
> > > 
> > > Would any the above mentioned patches do anything in that area?
> > 
> > The NWL driver is missing at least one fix that is needed for DCSS to
> > work nicely with it. One thing that needs fixed is the polarity. I added
> > a patch for that in our tree... :/
> > 
> > Currently, in NWL upstream, we have
> > 
> > adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> > adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> > 
> > However DCSS works with:
> > 
> > adjusted->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> > adjusted->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> 
> Thanks! I remember not getting any output at all with DCSS without what
> you suggest above but now i get some output and then a hang so there
> seems to be something else off.

What's the hang about? Any backtrace?

Thanks,
laurentiu

> 
> Cheers,
>  -- Guido
> 
> > 
> > I CCed Robert. He'll work on upstreaming these NWL changes in the following
> > period of time.
> > 
> > Thanks,
> > laurentiu
> > 
> > > 

Re: [PATCH v8 5/5] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

On Wed, Jul 29, 2020 at 03:27:30PM +0200, Guido Günther wrote:
> Hi,
> On Fri, Jul 24, 2020 at 12:07:34PM +0300, Laurentiu Palcu wrote:
> > From: Laurentiu Palcu 
> > 
> > Add bindings for iMX8MQ Display Controller Subsystem.
> > 
> > Signed-off-by: Laurentiu Palcu 
> > Reviewed-by: Rob Herring 
> > ---
> >  .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 ++
> >  1 file changed, 104 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 
> > b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > new file mode 100644
> > index ..68e4635e4874
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > @@ -0,0 +1,104 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright 2019 NXP
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> > +
> > +title: iMX8MQ Display Controller Subsystem (DCSS)
> > +
> > +maintainers:
> > +  - Laurentiu Palcu 
> > +
> > +description:
> > +
> > +  The DCSS (display controller sub system) is used to source up to three
> > +  display buffers, compose them, and drive a display using HDMI 2.0a(with 
> > HDCP
> > +  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. 
> > HDR10
> > +  image processing capabilities are included to provide a solution capable 
> > of
> > +  driving next generation high dynamic range displays.
> > +
> > +properties:
> > +  compatible:
> > +const: nxp,imx8mq-dcss
> > +
> > +  reg:
> > +items:
> > +  - description: DCSS base address and size, up to IRQ steer start
> > +  - description: DCSS BLKCTL base address and size
> > +
> > +  interrupts:
> > +items:
> > +  - description: Context loader completion and error interrupt
> > +  - description: DTG interrupt used to signal context loader trigger 
> > time
> > +  - description: DTG interrupt for Vblank
> > +
> > +  interrupt-names:
> > +items:
> > +  - const: ctxld
> > +  - const: ctxld_kick
> > +  - const: vblank
> > +
> > +  clocks:
> > +items:
> > +  - description: Display APB clock for all peripheral PIO access 
> > interfaces
> > +  - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
> > +  - description: RTRAM clock
> > +  - description: Pixel clock, can be driven either by HDMI phy clock 
> > or MIPI
> > +  - description: DTRC clock, needed by video decompressor
> > +
> > +  clock-names:
> > +items:
> > +  - const: apb
> > +  - const: axi
> > +  - const: rtrm
> > +  - const: pix
> > +  - const: dtrc
> > +
> > +  assigned-clocks:
> > +items:
> > +  - description: Phandle and clock specifier of 
> > IMX8MQ_CLK_DISP_AXI_ROOT
> > +  - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
> > +  - description: Phandle and clock specifier of either 
> > IMX8MQ_VIDEO2_PLL1_REF_SEL or
> > + IMX8MQ_VIDEO_PLL1_REF_SEL
> > +
> > +  assigned-clock-parents:
> > +items:
> > +  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
> > +  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
> > +  - description: Phandle and clock specifier of IMX8MQ_CLK_27M
> > +
> > +  assigned-clock-rates:
> > +items:
> > +  - description: Must be 800 MHz
> > +  - description: Must be 400 MHz
> > +
> > +  port:
> > +type: object
> > +description:
> > +  A port node pointing to the input port of a HDMI/DP or MIPI display 
> > bridge.
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> 
> it would be nice to
> 
> #include 
> 
> here...
> 
> > +dcss: display-controller@32e0 {
> > +compatible = "nxp,imx8mq-dcss";
> > +reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
> > +interrupts = <6>, <8>, <9>;
> > +interrupt-names = "ctxld", "ctxld_kick", "vblank";
> > +  

Re: [PATCH v8 0/5] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

Hi Guido,

On Wed, Jul 29, 2020 at 03:59:48PM +0200, Guido Günther wrote:
> Hi,
> On Fri, Jul 24, 2020 at 12:07:29PM +0300, Laurentiu Palcu wrote:
> > From: Laurentiu Palcu 
> > 
> > Hi,
> > 
> > This patchset adds initial DCSS support for iMX8MQ chip. Initial support
> > includes only graphics plane support (no video planes), no HDR10 
> > capabilities,
> > no graphics decompression (only linear, tiled and super-tiled buffers 
> > allowed).
> > 
> > Support for the rest of the features will be added incrementally, in 
> > subsequent
> > patches.
> > 
> > The patchset was tested with both HDP driver (in the downstream tree) and 
> > the upstream
> > MIPI-DSI driver (with a couple of patches on top, to make it work
> > correctly with DCSS).
> 
> While i could run earlier versions of this  series with NWL I'm seeing
> only a brief image that then turns black (backlight still on) with this 
> current version and
> the board hangs soon after.(for reference using mxsfb works nicely with
> the very same DT on next-20200727). If I do a drm.debug=0x3f i can see
> that display output stops around:
> 
> [   15.394473] imx-dcss 32e0.display-controller: 
> [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=22, 
> diff=1, hw=0 hw_last=0
> [   15.397575] device: 'input1': device_add
> [   15.444658] imx-dcss 32e0.display-controller: 
> [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=23, 
> diff=1, hw=0 hw_last=0
> [   15.465946] PM: Adding info for No Bus:input1
> [   15.494842] imx-dcss 32e0.display-controller: 
> [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=24, 
> diff=1, hw=0 hw_last=0
> [   15.511694] input: gpio-keys as /devices/platform/gpio-keys/input/input1
> [   15.545025] imx-dcss 32e0.display-controller: 
> [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=25, 
> diff=1, hw=0 hw_last=0
> [   15.557869] device: 'event1': device_add
> [   15.595209] imx-dcss 32e0.display-controller: 
> [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=26, 
> diff=1, hw=0 hw_last=0
> [   15.605363] PM: Adding info for No Bus:event1
> [   15.645394] imx-dcss 32e0.display-controller: 
> [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=27, 
> diff=1, hw=0 hw_last=0
> [   19.427039] imx-dcss 32e0.display-controller: [drm:vblank_disable_fn] 
> disabling vblank on crtc 0
> [   19.436135] device: 'wakeup6': device_add
> [   19.448202] imx-dcss 32e0.display-controller: 
> [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=28, 
> diff=0, hw=0 hw_last=0
> 
> (and there's no further logging from drm from there on).
> 
> Would any the above mentioned patches do anything in that area?

The NWL driver is missing at least one fix that is needed for DCSS to
work nicely with it. One thing that needs fixed is the polarity. I added
a patch for that in our tree... :/

Currently, in NWL upstream, we have

adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);

However DCSS works with:

adjusted->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
adjusted->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);

I CCed Robert. He'll work on upstreaming these NWL changes in the following
period of time.

Thanks,
laurentiu

> 
> Cheers,
>  -- Guido
> 
> > 
> > Thanks,
> > Laurentiu
> > 
> > Changes in v8:
> >  * Removed 'select RESET_CONTROLLER" from Kconfig as Philipp pointed
> >out. SRC is not used in DCSS driver;
> >  * Nothing else changed;
> > 
> > Changes in v7:
> >  * Added a patch to initialize the connector using the drm_bridge_connector
> >API as Sam suggested. Tested it using NWL_DSI and ADV7535 with
> >Guido's patch [1] applied and one fix for ADV [2]. Also, some extra
> >patches for ADV and NWL were needed, from our downstream tree, which
> >will be upstreamed soon by their author;
> >  * Rest of the patches are untouched;
> > 
> > [1] https://lists.freedesktop.org/archives/dri-devel/2020-July/273025.html
> > [2] https://lists.freedesktop.org/archives/dri-devel/2020-July/273132.html
> > 
> > Changes in v6:
> >  * Addressed Rob's comment and added "additionalProperties: false" at
> >the end of the bindings' properties. However, this change surfaced
> >an issue with the assigned-clock* properties not being documented in
> >the properties section. Added the descriptions and the bindings patch
> >

Re: [PATCH v8 2/5] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

Hi Guido,

On Wed, Jul 29, 2020 at 03:11:21PM +0200, Guido Günther wrote:
> Hi Laurentiu,
> On Fri, Jul 24, 2020 at 12:07:31PM +0300, Laurentiu Palcu wrote:
> > From: Laurentiu Palcu 
> > 
> > This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
> > Some of its capabilities include:
> >  * 4K@60fps;
> >  * HDR10;
> >  * one graphics and 2 video pipelines;
> >  * on-the-fly decompression of compressed video and graphics;
> > 
> > The reference manual can be found here:
> > https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM
> > 
> > The current patch adds only basic functionality: one primary plane for
> > graphics, linear, tiled and super-tiled buffers support (no graphics
> > decompression yet), no HDR10 and no video planes.
> > 
> > Video planes support and HDR10 will be added in subsequent patches once
> > per-plane de-gamma/CSC/gamma support is in.
> > 
> > Signed-off-by: Laurentiu Palcu 
> > Reviewed-by: Lucas Stach 
> > ---
> >  drivers/gpu/drm/imx/Kconfig|   2 +
> >  drivers/gpu/drm/imx/Makefile   |   1 +
> >  drivers/gpu/drm/imx/dcss/Kconfig   |   8 +
> >  drivers/gpu/drm/imx/dcss/Makefile  |   6 +
> >  drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  70 +++
> >  drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 219 +++
> >  drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 424 +
> >  drivers/gpu/drm/imx/dcss/dcss-dev.c| 314 ++
> >  drivers/gpu/drm/imx/dcss/dcss-dev.h| 177 ++
> >  drivers/gpu/drm/imx/dcss/dcss-dpr.c| 562 +
> >  drivers/gpu/drm/imx/dcss/dcss-drv.c| 138 +
> >  drivers/gpu/drm/imx/dcss/dcss-dtg.c| 409 
> >  drivers/gpu/drm/imx/dcss/dcss-kms.c| 177 ++
> >  drivers/gpu/drm/imx/dcss/dcss-kms.h|  43 ++
> >  drivers/gpu/drm/imx/dcss/dcss-plane.c  | 405 
> >  drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
> >  drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++
> >  17 files changed, 3961 insertions(+)
> >  create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
> >  create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c
> > 
> > diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
> > index 207bf7409dfb..6231048aa5aa 100644
> > --- a/drivers/gpu/drm/imx/Kconfig
> > +++ b/drivers/gpu/drm/imx/Kconfig
> > @@ -39,3 +39,5 @@ config DRM_IMX_HDMI
> > depends on DRM_IMX
> > help
> >   Choose this if you want to use HDMI on i.MX6.
> > +
> > +source "drivers/gpu/drm/imx/dcss/Kconfig"
> > diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
> > index 21cdcc2faabc..b644deffe948 100644
> > --- a/drivers/gpu/drm/imx/Makefile
> > +++ b/drivers/gpu/drm/imx/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
> >  obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
> >  
> >  obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
> > +obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
> > diff --git a/drivers/gpu/drm/imx/dcss/Kconfig 
> > b/drivers/gpu/drm/imx/dcss/Kconfig
> > new file mode 100644
> > index ..a76435924b6a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/imx/dcss/Kconfig
> > @@ -0,0 +1,8 @@
> > +config DRM_IMX_DCSS
> > +   tristate "i.MX8MQ DCSS"
> > +   select IMX_IRQSTEER
> > +   select DRM_KMS_CMA_HELPER
> > +   depends on DRM && ARCH_MXC
> 
> I need a
> 
> select VIDEOMODE_HELPERS
> 
> here otherwise the build fails like
> 
>  LD  .tmp_vmlinux.kallsyms1
>  aarch64-linux-gnu-ld: warning: -z norelro ignored
>  aarch64-linux-gnu-ld: drivers/gpu/drm/imx/dcss/dcss-crtc.o: in function 
> `dcss_crtc_atomic_enable':
>  dcss-crtc.c:(.text+0x2a8): un

[PATCH v8 3/5] drm/imx/dcss: use drm_bridge_connector API

[Laurentiu Palcu]

From: Laurentiu Palcu 

Make use of drm_bridge_connector API to have the connector initialized by the
display controller.

Signed-off-by: Laurentiu Palcu 
CC: Sam Ravnborg 
CC: Laurent Pinchart 
---
 drivers/gpu/drm/imx/dcss/dcss-dev.c | 17 +---
 drivers/gpu/drm/imx/dcss/dcss-kms.c | 31 -
 drivers/gpu/drm/imx/dcss/dcss-kms.h |  1 +
 3 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
b/drivers/gpu/drm/imx/dcss/dcss-dev.c
index 83a4840435cf..c849533ca83e 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
@@ -8,9 +8,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 
 #include "dcss-dev.h"
+#include "dcss-kms.h"
 
 static void dcss_clocks_enable(struct dcss_dev *dcss)
 {
@@ -247,9 +250,13 @@ void dcss_dev_destroy(struct dcss_dev *dcss)
 int dcss_dev_suspend(struct device *dev)
 {
struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
+   struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
+   struct dcss_kms_dev *kms = container_of(ddev, struct dcss_kms_dev, 
base);
int ret;
 
-   drm_mode_config_helper_suspend(dcss_drv_dev_to_drm(dev));
+   drm_bridge_connector_disable_hpd(kms->connector);
+
+   drm_mode_config_helper_suspend(ddev);
 
if (pm_runtime_suspended(dev))
return 0;
@@ -266,9 +273,11 @@ int dcss_dev_suspend(struct device *dev)
 int dcss_dev_resume(struct device *dev)
 {
struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
+   struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
+   struct dcss_kms_dev *kms = container_of(ddev, struct dcss_kms_dev, 
base);
 
if (pm_runtime_suspended(dev)) {
-   drm_mode_config_helper_resume(dcss_drv_dev_to_drm(dev));
+   drm_mode_config_helper_resume(ddev);
return 0;
}
 
@@ -278,7 +287,9 @@ int dcss_dev_resume(struct device *dev)
 
dcss_ctxld_resume(dcss->ctxld);
 
-   drm_mode_config_helper_resume(dcss_drv_dev_to_drm(dev));
+   drm_mode_config_helper_resume(ddev);
+
+   drm_bridge_connector_enable_hpd(kms->connector);
 
return 0;
 }
diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
b/drivers/gpu/drm/imx/dcss/dcss-kms.c
index 3ca49d0a3e61..135a62366ab8 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
@@ -5,6 +5,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -74,7 +75,7 @@ static const struct drm_encoder_funcs 
dcss_kms_simple_encoder_funcs = {
.destroy = drm_encoder_cleanup,
 };
 
-static int dcss_kms_setup_encoder(struct dcss_kms_dev *kms)
+static int dcss_kms_bridge_connector_init(struct dcss_kms_dev *kms)
 {
struct drm_device *ddev = >base;
struct drm_encoder *encoder = >encoder;
@@ -103,7 +104,23 @@ static int dcss_kms_setup_encoder(struct dcss_kms_dev *kms)
return ret;
}
 
-   return drm_bridge_attach(encoder, bridge, NULL, 0);
+   ret = drm_bridge_attach(encoder, bridge, NULL,
+   DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+   if (ret < 0) {
+   dev_err(ddev->dev, "Unable to attach bridge %pOF\n",
+   bridge->of_node);
+   return ret;
+   }
+
+   kms->connector = drm_bridge_connector_init(ddev, encoder);
+   if (IS_ERR(kms->connector)) {
+   dev_err(ddev->dev, "Unable to create bridge connector.\n");
+   return PTR_ERR(kms->connector);
+   }
+
+   drm_connector_attach_encoder(kms->connector, encoder);
+
+   return 0;
 }
 
 struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
@@ -131,18 +148,20 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev 
*dcss)
 
drm->irq_enabled = true;
 
-   ret = dcss_crtc_init(crtc, drm);
+   ret = dcss_kms_bridge_connector_init(kms);
if (ret)
goto cleanup_mode_config;
 
-   ret = dcss_kms_setup_encoder(kms);
+   ret = dcss_crtc_init(crtc, drm);
if (ret)
-   goto cleanup_crtc;
+   goto cleanup_mode_config;
 
drm_mode_config_reset(drm);
 
drm_kms_helper_poll_init(drm);
 
+   drm_bridge_connector_enable_hpd(kms->connector);
+
ret = drm_dev_register(drm, 0);
if (ret)
goto cleanup_crtc;
@@ -152,6 +171,7 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
return kms;
 
 cleanup_crtc:
+   drm_bridge_connector_disable_hpd(kms->connector);
drm_kms_helper_poll_fini(drm);
dcss_crtc_deinit(crtc, drm);
 
@@ -167,6 +187,7 @@ void dcss_kms_detach(struct dcss_kms_dev *kms)
struct drm_device *drm = >base;
 
drm_dev_unregister(drm);
+   drm_bridge_connector_disable_hpd(kms->connector);
drm_kms_helper_poll_fini(drm)

[PATCH v8 5/5] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

From: Laurentiu Palcu 

Add bindings for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Rob Herring 
---
 .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 ++
 1 file changed, 104 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 
b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
new file mode 100644
index ..68e4635e4874
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: iMX8MQ Display Controller Subsystem (DCSS)
+
+maintainers:
+  - Laurentiu Palcu 
+
+description:
+
+  The DCSS (display controller sub system) is used to source up to three
+  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
+  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
+  image processing capabilities are included to provide a solution capable of
+  driving next generation high dynamic range displays.
+
+properties:
+  compatible:
+const: nxp,imx8mq-dcss
+
+  reg:
+items:
+  - description: DCSS base address and size, up to IRQ steer start
+  - description: DCSS BLKCTL base address and size
+
+  interrupts:
+items:
+  - description: Context loader completion and error interrupt
+  - description: DTG interrupt used to signal context loader trigger time
+  - description: DTG interrupt for Vblank
+
+  interrupt-names:
+items:
+  - const: ctxld
+  - const: ctxld_kick
+  - const: vblank
+
+  clocks:
+items:
+  - description: Display APB clock for all peripheral PIO access interfaces
+  - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
+  - description: RTRAM clock
+  - description: Pixel clock, can be driven either by HDMI phy clock or 
MIPI
+  - description: DTRC clock, needed by video decompressor
+
+  clock-names:
+items:
+  - const: apb
+  - const: axi
+  - const: rtrm
+  - const: pix
+  - const: dtrc
+
+  assigned-clocks:
+items:
+  - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
+  - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
+  - description: Phandle and clock specifier of either 
IMX8MQ_VIDEO2_PLL1_REF_SEL or
+ IMX8MQ_VIDEO_PLL1_REF_SEL
+
+  assigned-clock-parents:
+items:
+  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+  - description: Phandle and clock specifier of IMX8MQ_CLK_27M
+
+  assigned-clock-rates:
+items:
+  - description: Must be 800 MHz
+  - description: Must be 400 MHz
+
+  port:
+type: object
+description:
+  A port node pointing to the input port of a HDMI/DP or MIPI display 
bridge.
+
+additionalProperties: false
+
+examples:
+  - |
+dcss: display-controller@32e0 {
+compatible = "nxp,imx8mq-dcss";
+reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+interrupts = <6>, <8>, <9>;
+interrupt-names = "ctxld", "ctxld_kick", "vblank";
+interrupt-parent = <>;
+clocks = < 248>, < 247>, < 249>,
+ < 254>,< 122>;
+clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+assigned-clocks = < 107>, < 109>, < 266>;
+assigned-clock-parents = < 78>, < 78>, < 3>;
+assigned-clock-rates = <8>,
+   <4>;
+port {
+dcss_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
-- 
2.23.0

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[PATCH v8 1/5] drm/imx: compile imx directory by default

[Laurentiu Palcu]

From: Laurentiu Palcu 

Currently the drm/imx/ directory is compiled only if DRM_IMX is set. Adding a
new IMX related IP in the same directory would need DRM_IMX to be set, which 
would
bring in also IPUv3 core driver...

The current patch would allow adding new IPs in the imx/ directory without 
needing
to set DRM_IMX.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Lucas Stach 
---
 drivers/gpu/drm/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 2c0e5a7e5953..c4d12e756c63 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -100,7 +100,7 @@ obj-$(CONFIG_DRM_MSM) += msm/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-$(CONFIG_DRM_STM) += stm/
 obj-$(CONFIG_DRM_STI) += sti/
-obj-$(CONFIG_DRM_IMX) += imx/
+obj-y  += imx/
 obj-$(CONFIG_DRM_INGENIC) += ingenic/
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
 obj-$(CONFIG_DRM_MESON)+= meson/
-- 
2.23.0

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[PATCH v8 4/5] MAINTAINERS: Add entry for i.MX 8MQ DCSS driver

[Laurentiu Palcu]

From: Laurentiu Palcu 

The driver is part of DRM subsystem and is located in drivers/gpu/drm/imx/dcss.

Signed-off-by: Laurentiu Palcu 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index dad5a62d21a7..200c5985b41f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12276,6 +12276,14 @@ F: drivers/iio/gyro/fxas21002c_core.c
 F: drivers/iio/gyro/fxas21002c_i2c.c
 F: drivers/iio/gyro/fxas21002c_spi.c
 
+NXP i.MX 8MQ DCSS DRIVER
+M: Laurentiu Palcu 
+R: Lucas Stach 
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+F: Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
+F: drivers/gpu/drm/imx/dcss/
+
 NXP SGTL5000 DRIVER
 M: Fabio Estevam 
 L: alsa-de...@alsa-project.org (moderated for non-subscribers)
-- 
2.23.0

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[PATCH v8 2/5] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

From: Laurentiu Palcu 

This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
Some of its capabilities include:
 * 4K@60fps;
 * HDR10;
 * one graphics and 2 video pipelines;
 * on-the-fly decompression of compressed video and graphics;

The reference manual can be found here:
https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM

The current patch adds only basic functionality: one primary plane for
graphics, linear, tiled and super-tiled buffers support (no graphics
decompression yet), no HDR10 and no video planes.

Video planes support and HDR10 will be added in subsequent patches once
per-plane de-gamma/CSC/gamma support is in.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Lucas Stach 
---
 drivers/gpu/drm/imx/Kconfig|   2 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig   |   8 +
 drivers/gpu/drm/imx/dcss/Makefile  |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  70 +++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 219 +++
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 424 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c| 314 ++
 drivers/gpu/drm/imx/dcss/dcss-dev.h| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-dpr.c| 562 +
 drivers/gpu/drm/imx/dcss/dcss-drv.c| 138 +
 drivers/gpu/drm/imx/dcss/dcss-dtg.c| 409 
 drivers/gpu/drm/imx/dcss/dcss-kms.c| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-kms.h|  43 ++
 drivers/gpu/drm/imx/dcss/dcss-plane.c  | 405 
 drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
 drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++
 17 files changed, 3961 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..6231048aa5aa 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,5 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+source "drivers/gpu/drm/imx/dcss/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..b644deffe948 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
diff --git a/drivers/gpu/drm/imx/dcss/Kconfig b/drivers/gpu/drm/imx/dcss/Kconfig
new file mode 100644
index ..a76435924b6a
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Kconfig
@@ -0,0 +1,8 @@
+config DRM_IMX_DCSS
+   tristate "i.MX8MQ DCSS"
+   select IMX_IRQSTEER
+   select DRM_KMS_CMA_HELPER
+   depends on DRM && ARCH_MXC
+   help
+ Choose this if you have a NXP i.MX8MQ based system and want to use the
+ Display Controller Subsystem. This option enables DCSS support.
diff --git a/drivers/gpu/drm/imx/dcss/Makefile 
b/drivers/gpu/drm/imx/dcss/Makefile
new file mode 100644
index ..8c7c8da42792
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Makefile
@@ -0,0 +1,6 @@
+imx-dcss-objs := dcss-drv.o dcss-dev.o dcss-blkctl.o dcss-ctxld.o dcss-dtg.o \
+dcss-ss.o dcss-dpr.o dcss-scaler.o dcss-kms.o 
dcss-crtc.o \
+dcss-plane.o
+
+obj-$(CONFIG_DRM_IMX_DCSS) += imx-dcss.o
+
diff --git a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c 
b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
new file mode 100644
index ..c9b54bb2692d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP.
+ */
+
+#include 
+#include 
+#include 
+
+#include "dcss-dev.h"
+
+#define DCSS_BLKCTL_RESET_CTRL 0x00
+#define   B_CLK_RESETN BIT(0)
+#define   APB_CLK_RESETN   BIT(1)
+#define   P_CLK_RESETN BIT(2)
+#define   RTR_CLK_RESETN   BIT(4)
+#define DCSS_BLKCTL_CONTROL0   0x10
+#define   HDMI_MIPI_CLK_SELBIT(0)
+#define   D

[PATCH v8 0/5] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

From: Laurentiu Palcu 

Hi,

This patchset adds initial DCSS support for iMX8MQ chip. Initial support
includes only graphics plane support (no video planes), no HDR10 capabilities,
no graphics decompression (only linear, tiled and super-tiled buffers allowed).

Support for the rest of the features will be added incrementally, in subsequent
patches.

The patchset was tested with both HDP driver (in the downstream tree) and the 
upstream
MIPI-DSI driver (with a couple of patches on top, to make it work correctly 
with DCSS).

Thanks,
Laurentiu

Changes in v8:
 * Removed 'select RESET_CONTROLLER" from Kconfig as Philipp pointed
   out. SRC is not used in DCSS driver;
 * Nothing else changed;

Changes in v7:
 * Added a patch to initialize the connector using the drm_bridge_connector
   API as Sam suggested. Tested it using NWL_DSI and ADV7535 with
   Guido's patch [1] applied and one fix for ADV [2]. Also, some extra
   patches for ADV and NWL were needed, from our downstream tree, which
   will be upstreamed soon by their author;
 * Rest of the patches are untouched;

[1] https://lists.freedesktop.org/archives/dri-devel/2020-July/273025.html
[2] https://lists.freedesktop.org/archives/dri-devel/2020-July/273132.html

Changes in v6:
 * Addressed Rob's comment and added "additionalProperties: false" at
   the end of the bindings' properties. However, this change surfaced
   an issue with the assigned-clock* properties not being documented in
   the properties section. Added the descriptions and the bindings patch
   will need another review;
 * Added an entry for DCSS driver in the MAINTAINERS file;
 * Removed the component framework patch altogether;

Changes in v5:
 * Rebased to latest;
 * Took out component framework support and made it a separate patch so
   that people can still test with HDP driver, which makes use of it.
   But the idea is to get rid of it once HDP driver's next versions
   will remove component framework as well;
 * Slight improvement to modesetting: avoid cutting off the pixel clock
   if the new mode and the old one are equal. Also, in this case, is
   not necessary to wait for DTG to shut off. This would allow to switch
   from 8b RGB to 12b YUV422, for example, with no interruptions (at least
   from DCSS point of view);
 * Do not fire off CTXLD when going to suspend, unless it still has
   entries that need to be committed to DCSS;
 * Addressed Rob's comments on bindings;

Changes in v4:
 * Addressed Lucas and Philipp's comments:
   * Added DRM_KMS_CMA_HELPER dependency in Kconfig;
   * Removed usage of devm_ functions since I'm already doing all the
 clean-up in the submodules_deinit();
   * Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush();
   * Removed en_completion variable from dcss_crtc since this was
 introduced mainly to avoid vblank timeout warnings which were fixed
 by arming the vblank event in flush() instead of begin();
   * Removed clks_on and irq_enabled flags since all the calls to
 enabling/disabling clocks and interrupts were balanced;
   * Removed the custom atomic_commit callback and used the DRM core
 helper and, in the process, got rid of a workqueue that wasn't
 necessary anymore;
   * Fixed some minor DT binding issues flagged by Philipp;
   * Some other minor changes suggested by Lucas;
 * Removed YUV formats from the supported formats as these cannot work
   without the HDR10 module CSCs and LUTs. Will add them back when I
   will add support for video planes;

Changes in v3:
 * rebased to latest linux-next and made it compile as drmP.h was
   removed;
 * removed the patch adding the VIDEO2_PLL clock. It's already applied;
 * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set();
 * fixed a a spurious hang reported by Lukas Hartmann and encountered
   by me several times;
 * mask DPR and DTG interrupts by default, as they may come enabled from
   U-boot;

Changes in v2:
 * Removed '0x' in node's unit-address both in DT and yaml;
 * Made the address region size lowercase, to be consistent;
 * Removed some left-over references to P010;
 * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence 
compilation
   issues reported by kbuild for other architectures;


Laurentiu Palcu (5):
  drm/imx: compile imx directory by default
  drm/imx: Add initial support for DCSS on iMX8MQ
  drm/imx/dcss: use drm_bridge_connector API
  MAINTAINERS: Add entry for i.MX 8MQ DCSS driver
  dt-bindings: display: imx: add bindings for DCSS

 .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 +++
 MAINTAINERS   |   8 +
 drivers/gpu/drm/Makefile  |   2 +-
 drivers/gpu/drm/imx/Kconfig   |   2 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig  |   8 +
 drivers/gpu/drm/imx/dcss/Makefile |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c|  70 ++
 drivers/gpu/d

Re: [PATCH v7 2/5] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

Hi Philipp,

On Tue, Jul 21, 2020 at 02:43:28PM +0200, Philipp Zabel wrote:
> Hi Laurentiu,
> 
> On Tue, 2020-07-21 at 13:20 +0300, Laurentiu Palcu wrote:
> > From: Laurentiu Palcu 
> > 
> > This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
> > Some of its capabilities include:
> >  * 4K@60fps;
> >  * HDR10;
> >  * one graphics and 2 video pipelines;
> >  * on-the-fly decompression of compressed video and graphics;
> > 
> > The reference manual can be found here:
> > https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM
> > 
> > The current patch adds only basic functionality: one primary plane for
> > graphics, linear, tiled and super-tiled buffers support (no graphics
> > decompression yet), no HDR10 and no video planes.
> > 
> > Video planes support and HDR10 will be added in subsequent patches once
> > per-plane de-gamma/CSC/gamma support is in.
> > 
> > Signed-off-by: Laurentiu Palcu 
> > Reviewed-by: Lucas Stach 
> > ---
> >  drivers/gpu/drm/imx/Kconfig|   2 +
> >  drivers/gpu/drm/imx/Makefile   |   1 +
> >  drivers/gpu/drm/imx/dcss/Kconfig   |   9 +
> >  drivers/gpu/drm/imx/dcss/Makefile  |   6 +
> >  drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  70 +++
> >  drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 219 +++
> >  drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 424 +
> >  drivers/gpu/drm/imx/dcss/dcss-dev.c| 314 ++
> >  drivers/gpu/drm/imx/dcss/dcss-dev.h| 177 ++
> >  drivers/gpu/drm/imx/dcss/dcss-dpr.c| 562 +
> >  drivers/gpu/drm/imx/dcss/dcss-drv.c| 138 +
> >  drivers/gpu/drm/imx/dcss/dcss-dtg.c| 409 
> >  drivers/gpu/drm/imx/dcss/dcss-kms.c| 177 ++
> >  drivers/gpu/drm/imx/dcss/dcss-kms.h|  43 ++
> >  drivers/gpu/drm/imx/dcss/dcss-plane.c  | 405 
> >  drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
> >  drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++
> >  17 files changed, 3962 insertions(+)
> >  create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
> >  create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c
> > 
> > diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
> > index 207bf7409dfb..6231048aa5aa 100644
> > --- a/drivers/gpu/drm/imx/Kconfig
> > +++ b/drivers/gpu/drm/imx/Kconfig
> > @@ -39,3 +39,5 @@ config DRM_IMX_HDMI
> > depends on DRM_IMX
> > help
> >   Choose this if you want to use HDMI on i.MX6.
> > +
> > +source "drivers/gpu/drm/imx/dcss/Kconfig"
> > diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
> > index 21cdcc2faabc..b644deffe948 100644
> > --- a/drivers/gpu/drm/imx/Makefile
> > +++ b/drivers/gpu/drm/imx/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
> >  obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
> >  
> >  obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
> > +obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
> > diff --git a/drivers/gpu/drm/imx/dcss/Kconfig 
> > b/drivers/gpu/drm/imx/dcss/Kconfig
> > new file mode 100644
> > index ..988979bc22cc
> > --- /dev/null
> > +++ b/drivers/gpu/drm/imx/dcss/Kconfig
> > @@ -0,0 +1,9 @@
> > +config DRM_IMX_DCSS
> > +   tristate "i.MX8MQ DCSS"
> > +   select RESET_CONTROLLER
> 
> Why does DCSS select RESET_CONTROLLER?

Why indeed? Apparently, for no reason at all... :/ I must've used SRC at
some point, at the very beginning, though I don't even remember using
it... Hmm, weird. I'll remove it. Thanks for spotting it.

Thanks,
Laurentiu

> 
> regards
> Philipp
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[PATCH v7 5/5] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

From: Laurentiu Palcu 

Add bindings for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Rob Herring 
---
 .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 ++
 1 file changed, 104 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 
b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
new file mode 100644
index ..68e4635e4874
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: iMX8MQ Display Controller Subsystem (DCSS)
+
+maintainers:
+  - Laurentiu Palcu 
+
+description:
+
+  The DCSS (display controller sub system) is used to source up to three
+  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
+  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
+  image processing capabilities are included to provide a solution capable of
+  driving next generation high dynamic range displays.
+
+properties:
+  compatible:
+const: nxp,imx8mq-dcss
+
+  reg:
+items:
+  - description: DCSS base address and size, up to IRQ steer start
+  - description: DCSS BLKCTL base address and size
+
+  interrupts:
+items:
+  - description: Context loader completion and error interrupt
+  - description: DTG interrupt used to signal context loader trigger time
+  - description: DTG interrupt for Vblank
+
+  interrupt-names:
+items:
+  - const: ctxld
+  - const: ctxld_kick
+  - const: vblank
+
+  clocks:
+items:
+  - description: Display APB clock for all peripheral PIO access interfaces
+  - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
+  - description: RTRAM clock
+  - description: Pixel clock, can be driven either by HDMI phy clock or 
MIPI
+  - description: DTRC clock, needed by video decompressor
+
+  clock-names:
+items:
+  - const: apb
+  - const: axi
+  - const: rtrm
+  - const: pix
+  - const: dtrc
+
+  assigned-clocks:
+items:
+  - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
+  - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
+  - description: Phandle and clock specifier of either 
IMX8MQ_VIDEO2_PLL1_REF_SEL or
+ IMX8MQ_VIDEO_PLL1_REF_SEL
+
+  assigned-clock-parents:
+items:
+  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+  - description: Phandle and clock specifier of IMX8MQ_CLK_27M
+
+  assigned-clock-rates:
+items:
+  - description: Must be 800 MHz
+  - description: Must be 400 MHz
+
+  port:
+type: object
+description:
+  A port node pointing to the input port of a HDMI/DP or MIPI display 
bridge.
+
+additionalProperties: false
+
+examples:
+  - |
+dcss: display-controller@32e0 {
+compatible = "nxp,imx8mq-dcss";
+reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+interrupts = <6>, <8>, <9>;
+interrupt-names = "ctxld", "ctxld_kick", "vblank";
+interrupt-parent = <>;
+clocks = < 248>, < 247>, < 249>,
+ < 254>,< 122>;
+clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+assigned-clocks = < 107>, < 109>, < 266>;
+assigned-clock-parents = < 78>, < 78>, < 3>;
+assigned-clock-rates = <8>,
+   <4>;
+port {
+dcss_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
-- 
2.23.0

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[PATCH v7 2/5] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

From: Laurentiu Palcu 

This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
Some of its capabilities include:
 * 4K@60fps;
 * HDR10;
 * one graphics and 2 video pipelines;
 * on-the-fly decompression of compressed video and graphics;

The reference manual can be found here:
https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM

The current patch adds only basic functionality: one primary plane for
graphics, linear, tiled and super-tiled buffers support (no graphics
decompression yet), no HDR10 and no video planes.

Video planes support and HDR10 will be added in subsequent patches once
per-plane de-gamma/CSC/gamma support is in.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Lucas Stach 
---
 drivers/gpu/drm/imx/Kconfig|   2 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig   |   9 +
 drivers/gpu/drm/imx/dcss/Makefile  |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  70 +++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 219 +++
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 424 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c| 314 ++
 drivers/gpu/drm/imx/dcss/dcss-dev.h| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-dpr.c| 562 +
 drivers/gpu/drm/imx/dcss/dcss-drv.c| 138 +
 drivers/gpu/drm/imx/dcss/dcss-dtg.c| 409 
 drivers/gpu/drm/imx/dcss/dcss-kms.c| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-kms.h|  43 ++
 drivers/gpu/drm/imx/dcss/dcss-plane.c  | 405 
 drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
 drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++
 17 files changed, 3962 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..6231048aa5aa 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,5 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+source "drivers/gpu/drm/imx/dcss/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..b644deffe948 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
diff --git a/drivers/gpu/drm/imx/dcss/Kconfig b/drivers/gpu/drm/imx/dcss/Kconfig
new file mode 100644
index ..988979bc22cc
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Kconfig
@@ -0,0 +1,9 @@
+config DRM_IMX_DCSS
+   tristate "i.MX8MQ DCSS"
+   select RESET_CONTROLLER
+   select IMX_IRQSTEER
+   select DRM_KMS_CMA_HELPER
+   depends on DRM && ARCH_MXC
+   help
+ Choose this if you have a NXP i.MX8MQ based system and want to use the
+ Display Controller Subsystem. This option enables DCSS support.
diff --git a/drivers/gpu/drm/imx/dcss/Makefile 
b/drivers/gpu/drm/imx/dcss/Makefile
new file mode 100644
index ..8c7c8da42792
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Makefile
@@ -0,0 +1,6 @@
+imx-dcss-objs := dcss-drv.o dcss-dev.o dcss-blkctl.o dcss-ctxld.o dcss-dtg.o \
+dcss-ss.o dcss-dpr.o dcss-scaler.o dcss-kms.o 
dcss-crtc.o \
+dcss-plane.o
+
+obj-$(CONFIG_DRM_IMX_DCSS) += imx-dcss.o
+
diff --git a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c 
b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
new file mode 100644
index ..c9b54bb2692d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP.
+ */
+
+#include 
+#include 
+#include 
+
+#include "dcss-dev.h"
+
+#define DCSS_BLKCTL_RESET_CTRL 0x00
+#define   B_CLK_RESETN BIT(0)
+#define   APB_CLK_RESETN   BIT(1)
+#define   P_CLK_RESETN BIT(2)
+#define   RTR_CLK_RESETN   BIT(4)
+#define DCSS_BLKCTL_CONTROL0   0x10
+#define   HDMI_M

[PATCH v7 4/5] MAINTAINERS: Add entry for i.MX 8MQ DCSS driver

[Laurentiu Palcu]

From: Laurentiu Palcu 

The driver is part of DRM subsystem and is located in drivers/gpu/drm/imx/dcss.

Signed-off-by: Laurentiu Palcu 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index dad5a62d21a7..200c5985b41f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12276,6 +12276,14 @@ F: drivers/iio/gyro/fxas21002c_core.c
 F: drivers/iio/gyro/fxas21002c_i2c.c
 F: drivers/iio/gyro/fxas21002c_spi.c
 
+NXP i.MX 8MQ DCSS DRIVER
+M: Laurentiu Palcu 
+R: Lucas Stach 
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+F: Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
+F: drivers/gpu/drm/imx/dcss/
+
 NXP SGTL5000 DRIVER
 M: Fabio Estevam 
 L: alsa-de...@alsa-project.org (moderated for non-subscribers)
-- 
2.23.0

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[PATCH v7 3/5] drm/imx/dcss: use drm_bridge_connector API

[Laurentiu Palcu]

From: Laurentiu Palcu 

Make use of drm_bridge_connector API to have the connector initialized by the
display controller.

Signed-off-by: Laurentiu Palcu 
CC: Sam Ravnborg 
CC: Laurent Pinchart 
---
 drivers/gpu/drm/imx/dcss/dcss-dev.c | 17 +---
 drivers/gpu/drm/imx/dcss/dcss-kms.c | 31 -
 drivers/gpu/drm/imx/dcss/dcss-kms.h |  1 +
 3 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c 
b/drivers/gpu/drm/imx/dcss/dcss-dev.c
index 83a4840435cf..c849533ca83e 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
@@ -8,9 +8,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 
 #include "dcss-dev.h"
+#include "dcss-kms.h"
 
 static void dcss_clocks_enable(struct dcss_dev *dcss)
 {
@@ -247,9 +250,13 @@ void dcss_dev_destroy(struct dcss_dev *dcss)
 int dcss_dev_suspend(struct device *dev)
 {
struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
+   struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
+   struct dcss_kms_dev *kms = container_of(ddev, struct dcss_kms_dev, 
base);
int ret;
 
-   drm_mode_config_helper_suspend(dcss_drv_dev_to_drm(dev));
+   drm_bridge_connector_disable_hpd(kms->connector);
+
+   drm_mode_config_helper_suspend(ddev);
 
if (pm_runtime_suspended(dev))
return 0;
@@ -266,9 +273,11 @@ int dcss_dev_suspend(struct device *dev)
 int dcss_dev_resume(struct device *dev)
 {
struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev);
+   struct drm_device *ddev = dcss_drv_dev_to_drm(dev);
+   struct dcss_kms_dev *kms = container_of(ddev, struct dcss_kms_dev, 
base);
 
if (pm_runtime_suspended(dev)) {
-   drm_mode_config_helper_resume(dcss_drv_dev_to_drm(dev));
+   drm_mode_config_helper_resume(ddev);
return 0;
}
 
@@ -278,7 +287,9 @@ int dcss_dev_resume(struct device *dev)
 
dcss_ctxld_resume(dcss->ctxld);
 
-   drm_mode_config_helper_resume(dcss_drv_dev_to_drm(dev));
+   drm_mode_config_helper_resume(ddev);
+
+   drm_bridge_connector_enable_hpd(kms->connector);
 
return 0;
 }
diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
b/drivers/gpu/drm/imx/dcss/dcss-kms.c
index 3ca49d0a3e61..135a62366ab8 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
@@ -5,6 +5,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -74,7 +75,7 @@ static const struct drm_encoder_funcs 
dcss_kms_simple_encoder_funcs = {
.destroy = drm_encoder_cleanup,
 };
 
-static int dcss_kms_setup_encoder(struct dcss_kms_dev *kms)
+static int dcss_kms_bridge_connector_init(struct dcss_kms_dev *kms)
 {
struct drm_device *ddev = >base;
struct drm_encoder *encoder = >encoder;
@@ -103,7 +104,23 @@ static int dcss_kms_setup_encoder(struct dcss_kms_dev *kms)
return ret;
}
 
-   return drm_bridge_attach(encoder, bridge, NULL, 0);
+   ret = drm_bridge_attach(encoder, bridge, NULL,
+   DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+   if (ret < 0) {
+   dev_err(ddev->dev, "Unable to attach bridge %pOF\n",
+   bridge->of_node);
+   return ret;
+   }
+
+   kms->connector = drm_bridge_connector_init(ddev, encoder);
+   if (IS_ERR(kms->connector)) {
+   dev_err(ddev->dev, "Unable to create bridge connector.\n");
+   return PTR_ERR(kms->connector);
+   }
+
+   drm_connector_attach_encoder(kms->connector, encoder);
+
+   return 0;
 }
 
 struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
@@ -131,18 +148,20 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev 
*dcss)
 
drm->irq_enabled = true;
 
-   ret = dcss_crtc_init(crtc, drm);
+   ret = dcss_kms_bridge_connector_init(kms);
if (ret)
goto cleanup_mode_config;
 
-   ret = dcss_kms_setup_encoder(kms);
+   ret = dcss_crtc_init(crtc, drm);
if (ret)
-   goto cleanup_crtc;
+   goto cleanup_mode_config;
 
drm_mode_config_reset(drm);
 
drm_kms_helper_poll_init(drm);
 
+   drm_bridge_connector_enable_hpd(kms->connector);
+
ret = drm_dev_register(drm, 0);
if (ret)
goto cleanup_crtc;
@@ -152,6 +171,7 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
return kms;
 
 cleanup_crtc:
+   drm_bridge_connector_disable_hpd(kms->connector);
drm_kms_helper_poll_fini(drm);
dcss_crtc_deinit(crtc, drm);
 
@@ -167,6 +187,7 @@ void dcss_kms_detach(struct dcss_kms_dev *kms)
struct drm_device *drm = >base;
 
drm_dev_unregister(drm);
+   drm_bridge_connector_disable_hpd(kms->connector);
drm_kms_helper_poll_fini(drm)

[PATCH v7 1/5] drm/imx: compile imx directory by default

[Laurentiu Palcu]

From: Laurentiu Palcu 

Currently the drm/imx/ directory is compiled only if DRM_IMX is set. Adding a
new IMX related IP in the same directory would need DRM_IMX to be set, which 
would
bring in also IPUv3 core driver...

The current patch would allow adding new IPs in the imx/ directory without 
needing
to set DRM_IMX.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Lucas Stach 
---
 drivers/gpu/drm/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 2c0e5a7e5953..c4d12e756c63 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -100,7 +100,7 @@ obj-$(CONFIG_DRM_MSM) += msm/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-$(CONFIG_DRM_STM) += stm/
 obj-$(CONFIG_DRM_STI) += sti/
-obj-$(CONFIG_DRM_IMX) += imx/
+obj-y  += imx/
 obj-$(CONFIG_DRM_INGENIC) += ingenic/
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
 obj-$(CONFIG_DRM_MESON)+= meson/
-- 
2.23.0

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[PATCH v7 0/5] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

From: Laurentiu Palcu 

Hi,

This patchset adds initial DCSS support for iMX8MQ chip. Initial support
includes only graphics plane support (no video planes), no HDR10 capabilities,
no graphics decompression (only linear, tiled and super-tiled buffers allowed).

Support for the rest of the features will be added incrementally, in subsequent
patches.

The patchset was tested with both HDP driver (in the downstream tree) and the 
upstream
MIPI-DSI driver (with a couple of patches on top, to make it work correctly 
with DCSS).

Thanks,
Laurentiu

Changes in v7:
 * Added a patch to initialize the connector using the drm_bridge_connector
   API as Sam suggested. Tested it using NWL_DSI and ADV7535 with
   Guido's patch [1] applied and one fix for ADV [2]. Also, some extra
   patches for ADV and NWL were needed, from our downstream tree, which
   will be upstreamed soon by their author;
 * Rest of the patches are untouched;

[1] https://lists.freedesktop.org/archives/dri-devel/2020-July/273025.html
[2] https://lists.freedesktop.org/archives/dri-devel/2020-July/273132.html

Changes in v6:
 * Addressed Rob's comment and added "additionalProperties: false" at
   the end of the bindings' properties. However, this change surfaced
   an issue with the assigned-clock* properties not being documented in
   the properties section. Added the descriptions and the bindings patch
   will need another review;
 * Added an entry for DCSS driver in the MAINTAINERS file;
 * Removed the component framework patch altogether;

Changes in v5:
 * Rebased to latest;
 * Took out component framework support and made it a separate patch so
   that people can still test with HDP driver, which makes use of it.
   But the idea is to get rid of it once HDP driver's next versions
   will remove component framework as well;
 * Slight improvement to modesetting: avoid cutting off the pixel clock
   if the new mode and the old one are equal. Also, in this case, is
   not necessary to wait for DTG to shut off. This would allow to switch
   from 8b RGB to 12b YUV422, for example, with no interruptions (at least
   from DCSS point of view);
 * Do not fire off CTXLD when going to suspend, unless it still has
   entries that need to be committed to DCSS;
 * Addressed Rob's comments on bindings;

Changes in v4:
 * Addressed Lucas and Philipp's comments:
   * Added DRM_KMS_CMA_HELPER dependency in Kconfig;
   * Removed usage of devm_ functions since I'm already doing all the
 clean-up in the submodules_deinit();
   * Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush();
   * Removed en_completion variable from dcss_crtc since this was
 introduced mainly to avoid vblank timeout warnings which were fixed
 by arming the vblank event in flush() instead of begin();
   * Removed clks_on and irq_enabled flags since all the calls to
 enabling/disabling clocks and interrupts were balanced;
   * Removed the custom atomic_commit callback and used the DRM core
 helper and, in the process, got rid of a workqueue that wasn't
 necessary anymore;
   * Fixed some minor DT binding issues flagged by Philipp;
   * Some other minor changes suggested by Lucas;
 * Removed YUV formats from the supported formats as these cannot work
   without the HDR10 module CSCs and LUTs. Will add them back when I
   will add support for video planes;

Changes in v3:
 * rebased to latest linux-next and made it compile as drmP.h was
   removed;
 * removed the patch adding the VIDEO2_PLL clock. It's already applied;
 * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set();
 * fixed a a spurious hang reported by Lukas Hartmann and encountered
   by me several times;
 * mask DPR and DTG interrupts by default, as they may come enabled from
   U-boot;

Changes in v2:
 * Removed '0x' in node's unit-address both in DT and yaml;
 * Made the address region size lowercase, to be consistent;
 * Removed some left-over references to P010;
 * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence 
compilation
   issues reported by kbuild for other architectures;


Laurentiu Palcu (5):
  drm/imx: compile imx directory by default
  drm/imx: Add initial support for DCSS on iMX8MQ
  drm/imx/dcss: use drm_bridge_connector API
  MAINTAINERS: Add entry for i.MX 8MQ DCSS driver
  dt-bindings: display: imx: add bindings for DCSS

 .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 +++
 MAINTAINERS   |   8 +
 drivers/gpu/drm/Makefile  |   2 +-
 drivers/gpu/drm/imx/Kconfig   |   2 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig  |   9 +
 drivers/gpu/drm/imx/dcss/Makefile |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c|  70 ++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c  | 219 +
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c | 424 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c   | 325 ++

Re: [PATCH v6 4/4] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

Hi Rob,

On Mon, Jul 20, 2020 at 10:49:27AM -0600, Rob Herring wrote:
> On Fri, 17 Jul 2020 17:41:29 +0300, Laurentiu Palcu wrote:
> > From: Laurentiu Palcu 
> > 
> > Add bindings for iMX8MQ Display Controller Subsystem.
> > 
> > Signed-off-by: Laurentiu Palcu 
> > ---
> >  .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 ++
> >  1 file changed, 104 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > 
> 
> 
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
> 
> If a tag was not added on purpose, please state why and what changed.

Well, I kind of did exactly that... in the cover letter. I stated
clearly why this patch needs another look... :/

Thanks,
laurentiu
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[PATCH] drm/bridge/adv7511: set the bridge type properly

[Laurentiu Palcu]

From: Laurentiu Palcu 

After the drm_bridge_connector_init() helper function has been added, the ADV
driver has been changed accordingly. However, the 'type' field of the bridge
structure was left unset, which makes the helper function always return -EINVAL.

Signed-off-by: Laurentiu Palcu 
---
Hi,

I've hit this while trying to use this helper in the new i.MX8MQ DCSS
driver, as suggested by Sam, and I wanted to test it with NWL MIPI_DSI and
ADV since support is already in mainline.

Thanks,
laurentiu


 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index f45cdca9cce5..a0d392c338da 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -1283,6 +1283,7 @@ static int adv7511_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
adv7511->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
| DRM_BRIDGE_OP_HPD;
adv7511->bridge.of_node = dev->of_node;
+   adv7511->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
 
drm_bridge_add(>bridge);
 
-- 
2.23.0

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Re: [PATCH v6 2/4] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

Hi Sam,

On Fri, Jul 17, 2020 at 09:48:49PM +0200, Sam Ravnborg wrote:
> Hi Laurentiu.
> 
> On Fri, Jul 17, 2020 at 05:41:27PM +0300, Laurentiu Palcu wrote:
> > From: Laurentiu Palcu 
> > 
> > This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
> > Some of its capabilities include:
> >  * 4K@60fps;
> >  * HDR10;
> >  * one graphics and 2 video pipelines;
> >  * on-the-fly decompression of compressed video and graphics;
> > 
> > The reference manual can be found here:
> > https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM
> > 
> > The current patch adds only basic functionality: one primary plane for
> > graphics, linear, tiled and super-tiled buffers support (no graphics
> > decompression yet), no HDR10 and no video planes.
> > 
> > Video planes support and HDR10 will be added in subsequent patches once
> > per-plane de-gamma/CSC/gamma support is in.
> > 
> > Signed-off-by: Laurentiu Palcu 
> > Reviewed-by: Lucas Stach 
> > ---
> 
> 
> return drm_bridge_attach(encoder, bridge, NULL, 0);
> 
> 
> The above code-snippet tells that the display-driver rely on the bridge
> to create the connector.
> Could this by any chance be updated to the new way where the display
> driver creates the connector - and thus passing DRM_BRIDGE_ATTACH_NO_CONNECTOR
> as the flags argument?

OK, I can give this a shot and the changes will be part of a separate patch
within this patchset, if that's ok with you. No need to go through
and review the entire driver again for this...

Thanks,
laurentiu

> 
> What bridges would be relevant?
> To check that the reelvant bridges are already ported.
> 
>   Sam
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[PATCH v6 3/4] MAINTAINERS: Add entry for i.MX 8MQ DCSS driver

[Laurentiu Palcu]

From: Laurentiu Palcu 

The driver is part of DRM subsystem and is located in drivers/gpu/drm/imx/dcss.

Signed-off-by: Laurentiu Palcu 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index dad5a62d21a7..200c5985b41f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12276,6 +12276,14 @@ F: drivers/iio/gyro/fxas21002c_core.c
 F: drivers/iio/gyro/fxas21002c_i2c.c
 F: drivers/iio/gyro/fxas21002c_spi.c
 
+NXP i.MX 8MQ DCSS DRIVER
+M: Laurentiu Palcu 
+R: Lucas Stach 
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+F: Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
+F: drivers/gpu/drm/imx/dcss/
+
 NXP SGTL5000 DRIVER
 M: Fabio Estevam 
 L: alsa-de...@alsa-project.org (moderated for non-subscribers)
-- 
2.17.1

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[PATCH v6 0/4] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

From: Laurentiu Palcu 

Hi,

This patchset adds initial DCSS support for iMX8MQ chip. Initial support
includes only graphics plane support (no video planes), no HDR10 capabilities,
no graphics decompression (only linear, tiled and super-tiled buffers allowed).

Support for the rest of the features will be added incrementally, in subsequent
patches.

The patchset was tested with both HDP driver (in the downstream tree) and the 
upstream
MIPI-DSI driver (with a couple of patches on top, to make it work correctly 
with DCSS).

Thanks,
Laurentiu

Changes in v6:
 * Addressed Rob's comment and added "additionalProperties: false" at
   the end of the bindings' properties. However, this change surfaced
   an issue with the assigned-clock* properties not being documented in
   the properties section. Added the descriptions and the bindings patch
   will need another review;
 * Added an entry for DCSS driver in the MAINTAINERS file;
 * Removed the component framework patch altogether;

Changes in v5:
 * Rebased to latest;
 * Took out component framework support and made it a separate patch so
   that people can still test with HDP driver, which makes use of it.
   But the idea is to get rid of it once HDP driver's next versions
   will remove component framework as well;
 * Slight improvement to modesetting: avoid cutting off the pixel clock
   if the new mode and the old one are equal. Also, in this case, is
   not necessary to wait for DTG to shut off. This would allow to switch
   from 8b RGB to 12b YUV422, for example, with no interruptions (at least
   from DCSS point of view);
 * Do not fire off CTXLD when going to suspend, unless it still has
   entries that need to be committed to DCSS;
 * Addressed Rob's comments on bindings;

Changes in v4:
 * Addressed Lucas and Philipp's comments:
   * Added DRM_KMS_CMA_HELPER dependency in Kconfig;
   * Removed usage of devm_ functions since I'm already doing all the
 clean-up in the submodules_deinit();
   * Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush();
   * Removed en_completion variable from dcss_crtc since this was
 introduced mainly to avoid vblank timeout warnings which were fixed
 by arming the vblank event in flush() instead of begin();
   * Removed clks_on and irq_enabled flags since all the calls to
 enabling/disabling clocks and interrupts were balanced;
   * Removed the custom atomic_commit callback and used the DRM core
 helper and, in the process, got rid of a workqueue that wasn't
 necessary anymore;
   * Fixed some minor DT binding issues flagged by Philipp;
   * Some other minor changes suggested by Lucas;
 * Removed YUV formats from the supported formats as these cannot work
   without the HDR10 module CSCs and LUTs. Will add them back when I
   will add support for video planes;

Changes in v3:
 * rebased to latest linux-next and made it compile as drmP.h was
   removed;
 * removed the patch adding the VIDEO2_PLL clock. It's already applied;
 * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set();
 * fixed a a spurious hang reported by Lukas Hartmann and encountered
   by me several times;
 * mask DPR and DTG interrupts by default, as they may come enabled from
   U-boot;

Changes in v2:
 * Removed '0x' in node's unit-address both in DT and yaml;
 * Made the address region size lowercase, to be consistent;
 * Removed some left-over references to P010;
 * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence 
compilation
   issues reported by kbuild for other architectures;


Laurentiu Palcu (4):
  drm/imx: compile imx directory by default
  drm/imx: Add initial support for DCSS on iMX8MQ
  MAINTAINERS: Add entry for i.MX 8MQ DCSS driver
  dt-bindings: display: imx: add bindings for DCSS

 .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 +++
 MAINTAINERS   |   8 +
 drivers/gpu/drm/Makefile  |   2 +-
 drivers/gpu/drm/imx/Kconfig   |   2 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig  |   9 +
 drivers/gpu/drm/imx/dcss/Makefile |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c|  70 ++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c  | 219 +
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c | 424 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c   | 314 +++
 drivers/gpu/drm/imx/dcss/dcss-dev.h   | 177 
 drivers/gpu/drm/imx/dcss/dcss-dpr.c   | 562 
 drivers/gpu/drm/imx/dcss/dcss-drv.c   | 138 +++
 drivers/gpu/drm/imx/dcss/dcss-dtg.c   | 409 +
 drivers/gpu/drm/imx/dcss/dcss-kms.c   | 177 
 drivers/gpu/drm/imx/dcss/dcss-kms.h   |  43 +
 drivers/gpu/drm/imx/dcss/dcss-plane.c | 405 +
 drivers/gpu/drm/imx/dcss/dcss-scaler.c| 826 ++
 drivers/gpu/drm/imx/dcss/dcss-ss.c| 180 
 20 files changed, 407

[PATCH v6 2/4] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

From: Laurentiu Palcu 

This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
Some of its capabilities include:
 * 4K@60fps;
 * HDR10;
 * one graphics and 2 video pipelines;
 * on-the-fly decompression of compressed video and graphics;

The reference manual can be found here:
https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM

The current patch adds only basic functionality: one primary plane for
graphics, linear, tiled and super-tiled buffers support (no graphics
decompression yet), no HDR10 and no video planes.

Video planes support and HDR10 will be added in subsequent patches once
per-plane de-gamma/CSC/gamma support is in.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Lucas Stach 
---
 drivers/gpu/drm/imx/Kconfig|   2 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig   |   9 +
 drivers/gpu/drm/imx/dcss/Makefile  |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  70 +++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 219 +++
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 424 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c| 314 ++
 drivers/gpu/drm/imx/dcss/dcss-dev.h| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-dpr.c| 562 +
 drivers/gpu/drm/imx/dcss/dcss-drv.c| 138 +
 drivers/gpu/drm/imx/dcss/dcss-dtg.c| 409 
 drivers/gpu/drm/imx/dcss/dcss-kms.c| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-kms.h|  43 ++
 drivers/gpu/drm/imx/dcss/dcss-plane.c  | 405 
 drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
 drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++
 17 files changed, 3962 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..6231048aa5aa 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,5 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+source "drivers/gpu/drm/imx/dcss/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..b644deffe948 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
diff --git a/drivers/gpu/drm/imx/dcss/Kconfig b/drivers/gpu/drm/imx/dcss/Kconfig
new file mode 100644
index ..988979bc22cc
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Kconfig
@@ -0,0 +1,9 @@
+config DRM_IMX_DCSS
+   tristate "i.MX8MQ DCSS"
+   select RESET_CONTROLLER
+   select IMX_IRQSTEER
+   select DRM_KMS_CMA_HELPER
+   depends on DRM && ARCH_MXC
+   help
+ Choose this if you have a NXP i.MX8MQ based system and want to use the
+ Display Controller Subsystem. This option enables DCSS support.
diff --git a/drivers/gpu/drm/imx/dcss/Makefile 
b/drivers/gpu/drm/imx/dcss/Makefile
new file mode 100644
index ..8c7c8da42792
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Makefile
@@ -0,0 +1,6 @@
+imx-dcss-objs := dcss-drv.o dcss-dev.o dcss-blkctl.o dcss-ctxld.o dcss-dtg.o \
+dcss-ss.o dcss-dpr.o dcss-scaler.o dcss-kms.o 
dcss-crtc.o \
+dcss-plane.o
+
+obj-$(CONFIG_DRM_IMX_DCSS) += imx-dcss.o
+
diff --git a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c 
b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
new file mode 100644
index ..c9b54bb2692d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP.
+ */
+
+#include 
+#include 
+#include 
+
+#include "dcss-dev.h"
+
+#define DCSS_BLKCTL_RESET_CTRL 0x00
+#define   B_CLK_RESETN BIT(0)
+#define   APB_CLK_RESETN   BIT(1)
+#define   P_CLK_RESETN BIT(2)
+#define   RTR_CLK_RESETN   BIT(4)
+#define DCSS_BLKCTL_CONTROL0   0x10
+#define   HDMI_M

[PATCH v6 4/4] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

From: Laurentiu Palcu 

Add bindings for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu 
---
 .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 ++
 1 file changed, 104 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 
b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
new file mode 100644
index ..68e4635e4874
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: iMX8MQ Display Controller Subsystem (DCSS)
+
+maintainers:
+  - Laurentiu Palcu 
+
+description:
+
+  The DCSS (display controller sub system) is used to source up to three
+  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
+  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
+  image processing capabilities are included to provide a solution capable of
+  driving next generation high dynamic range displays.
+
+properties:
+  compatible:
+const: nxp,imx8mq-dcss
+
+  reg:
+items:
+  - description: DCSS base address and size, up to IRQ steer start
+  - description: DCSS BLKCTL base address and size
+
+  interrupts:
+items:
+  - description: Context loader completion and error interrupt
+  - description: DTG interrupt used to signal context loader trigger time
+  - description: DTG interrupt for Vblank
+
+  interrupt-names:
+items:
+  - const: ctxld
+  - const: ctxld_kick
+  - const: vblank
+
+  clocks:
+items:
+  - description: Display APB clock for all peripheral PIO access interfaces
+  - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
+  - description: RTRAM clock
+  - description: Pixel clock, can be driven either by HDMI phy clock or 
MIPI
+  - description: DTRC clock, needed by video decompressor
+
+  clock-names:
+items:
+  - const: apb
+  - const: axi
+  - const: rtrm
+  - const: pix
+  - const: dtrc
+
+  assigned-clocks:
+items:
+  - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
+  - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
+  - description: Phandle and clock specifier of either 
IMX8MQ_VIDEO2_PLL1_REF_SEL or
+ IMX8MQ_VIDEO_PLL1_REF_SEL
+
+  assigned-clock-parents:
+items:
+  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+  - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+  - description: Phandle and clock specifier of IMX8MQ_CLK_27M
+
+  assigned-clock-rates:
+items:
+  - description: Must be 800 MHz
+  - description: Must be 400 MHz
+
+  port:
+type: object
+description:
+  A port node pointing to the input port of a HDMI/DP or MIPI display 
bridge.
+
+additionalProperties: false
+
+examples:
+  - |
+dcss: display-controller@32e0 {
+compatible = "nxp,imx8mq-dcss";
+reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+interrupts = <6>, <8>, <9>;
+interrupt-names = "ctxld", "ctxld_kick", "vblank";
+interrupt-parent = <>;
+clocks = < 248>, < 247>, < 249>,
+ < 254>,< 122>;
+clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+assigned-clocks = < 107>, < 109>, < 266>;
+assigned-clock-parents = < 78>, < 78>, < 3>;
+assigned-clock-rates = <8>,
+   <4>;
+port {
+dcss_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
-- 
2.17.1

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[PATCH v6 1/4] drm/imx: compile imx directory by default

[Laurentiu Palcu]

From: Laurentiu Palcu 

Currently the drm/imx/ directory is compiled only if DRM_IMX is set. Adding a
new IMX related IP in the same directory would need DRM_IMX to be set, which 
would
bring in also IPUv3 core driver...

The current patch would allow adding new IPs in the imx/ directory without 
needing
to set DRM_IMX.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Lucas Stach 
---
 drivers/gpu/drm/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 2c0e5a7e5953..c4d12e756c63 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -100,7 +100,7 @@ obj-$(CONFIG_DRM_MSM) += msm/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-$(CONFIG_DRM_STM) += stm/
 obj-$(CONFIG_DRM_STI) += sti/
-obj-$(CONFIG_DRM_IMX) += imx/
+obj-y  += imx/
 obj-$(CONFIG_DRM_INGENIC) += ingenic/
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
 obj-$(CONFIG_DRM_MESON)+= meson/
-- 
2.17.1

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Re: [PATCH v5 0/4] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

Hi Lukas and Daniel,

On Fri, Jul 17, 2020 at 11:27:58AM +0200, Daniel Vetter wrote:
> On Fri, Jul 17, 2020 at 11:12:39AM +0200, Lucas Stach wrote:
> > Am Freitag, den 17.07.2020, 10:59 +0200 schrieb Daniel Vetter:
> > > On Fri, Jul 17, 2020 at 10:18 AM Lucas Stach  
> > > wrote:
> > > > Hi Laurentiu,
> > > > 
> > > > Am Donnerstag, den 09.07.2020, 19:47 +0300 schrieb Laurentiu Palcu:
> > > > > From: Laurentiu Palcu 
> > > > > 
> > > > > Hi,
> > > > > 
> > > > > This patchset adds initial DCSS support for iMX8MQ chip. Initial 
> > > > > support
> > > > > includes only graphics plane support (no video planes), no HDR10 
> > > > > capabilities,
> > > > > no graphics decompression (only linear, tiled and super-tiled buffers 
> > > > > allowed).
> > > > > 
> > > > > Support for the rest of the features will be added incrementally, in 
> > > > > subsequent
> > > > > patches.
> > > > > 
> > > > > The patchset was tested with both HDP driver (in the downstream tree) 
> > > > > and the upstream
> > > > > MIPI-DSI driver (with a couple of patches on top, to make it work 
> > > > > correctly with DCSS).
> > > > 
> > > > I think the series (minus 3/5 and minor correction to the DT binding)
> > > > is fine to go in now. So just some formal questions: are you going to
> > > > maintain this driver in upstream? If so we should add a MAINTAINERS
> > > > entry to that effect. I can offer to act as a reviewer in this case.

I can maintain the DCSS driver, sure, and the more reviewers the better.
Thanks for helping out with this. Should I send a v6 then with a patch
for MAINTAINERS?

> > > > 
> > > > How do you intend to merge this? IMO pushing this through drm-misc
> > > > seems like the right thing to do. If you agree I can help you get this
> > > > applied. If you are going to maintain the driver on your own, I think
> > > > you should then apply for commit rights to drm-misc.
> > > 
> > > drm/imx isn't listed yet as under the drm-misc umbrella, maybe we
> > > should put the entire collective of imx drivers under drm-misc? Or
> > > maybe it's just an oversight that the git repo isn't specified in the
> > > MAINTAINERS entry. Also maybe we should add the pengutronix kernel
> > > team alias there too?
> > 
> > drm/imx was exclusively the IPUv3 up until now, which is in fact
> > maintained outside of drm-misc in its own git tree. This has worked
> > quite well in the past so even though IPUv3 doesn't see a lot of churn
> > these days the motivation to change anything to this workflow is quite
> > low. And yes, the git tree is missing from the MAINTAINERS entry.
> > 
> > For the DCSS driver, if it's going to be maintained by NXP, I figured
> > it might be easier for Laurentiu to push things into drm-misc than set
> > up a separate public git tree. But IMHO that's fully up to him to
> > decide.
> 
> /me puts on maintainer hat
> 
> Much prefer drm-misc over random people playing maintainer and fumbling
> it. I think the reasonable options are either in the current imx tree, or
> drm-misc. Standalone tree for these small drivers just doesn't make much
> sense.

I don't have anything against either method, though I have to agree I
like things to be simple. Going through drm-misc sounds simple enough to me. :)
However, since there is going to be more activity in the DRM IMX area in
the future, reviving the drm/imx tree, and push all IMX related stuff
through drm/imx, could make sense as well.

Thanks,
Laurentiu

> -Daniel
> 
> > 
> > Regards,
> > Lucas
> > 
> > > -Daniel
> > > 
> > > 
> > > > Regards,
> > > > Lucas
> > > > 
> > > > > Thanks,
> > > > > Laurentiu
> > > > > 
> > > > > Changes in v5:
> > > > >  * Rebased to latest;
> > > > >  * Took out component framework support and made it a separate patch 
> > > > > so
> > > > >that people can still test with HDP driver, which makes use of it.
> > > > >But the idea is to get rid of it once HDP driver's next versions
> > > > >will remove component framework as well;
> > > > >  * Slight improvement to modesetting: avoid cutting off the pixel 
> > > > > clock
> > > > >if the new

[PATCH v5 2/5] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

From: Laurentiu Palcu 

This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
Some of its capabilities include:
 * 4K@60fps;
 * HDR10;
 * one graphics and 2 video pipelines;
 * on-the-fly decompression of compressed video and graphics;

The reference manual can be found here:
https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM

The current patch adds only basic functionality: one primary plane for
graphics, linear, tiled and super-tiled buffers support (no graphics
decompression yet), no HDR10 and no video planes.

Video planes support and HDR10 will be added in subsequent patches once
per-plane de-gamma/CSC/gamma support is in.

Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/imx/Kconfig|   2 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig   |   9 +
 drivers/gpu/drm/imx/dcss/Makefile  |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  70 +++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 219 +++
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 424 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c| 314 ++
 drivers/gpu/drm/imx/dcss/dcss-dev.h| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-dpr.c| 562 +
 drivers/gpu/drm/imx/dcss/dcss-drv.c| 138 +
 drivers/gpu/drm/imx/dcss/dcss-dtg.c| 409 
 drivers/gpu/drm/imx/dcss/dcss-kms.c| 177 ++
 drivers/gpu/drm/imx/dcss/dcss-kms.h|  43 ++
 drivers/gpu/drm/imx/dcss/dcss-plane.c  | 405 
 drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
 drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++
 17 files changed, 3962 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..6231048aa5aa 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,5 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+source "drivers/gpu/drm/imx/dcss/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..b644deffe948 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
diff --git a/drivers/gpu/drm/imx/dcss/Kconfig b/drivers/gpu/drm/imx/dcss/Kconfig
new file mode 100644
index ..988979bc22cc
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Kconfig
@@ -0,0 +1,9 @@
+config DRM_IMX_DCSS
+   tristate "i.MX8MQ DCSS"
+   select RESET_CONTROLLER
+   select IMX_IRQSTEER
+   select DRM_KMS_CMA_HELPER
+   depends on DRM && ARCH_MXC
+   help
+ Choose this if you have a NXP i.MX8MQ based system and want to use the
+ Display Controller Subsystem. This option enables DCSS support.
diff --git a/drivers/gpu/drm/imx/dcss/Makefile 
b/drivers/gpu/drm/imx/dcss/Makefile
new file mode 100644
index ..8c7c8da42792
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Makefile
@@ -0,0 +1,6 @@
+imx-dcss-objs := dcss-drv.o dcss-dev.o dcss-blkctl.o dcss-ctxld.o dcss-dtg.o \
+dcss-ss.o dcss-dpr.o dcss-scaler.o dcss-kms.o 
dcss-crtc.o \
+dcss-plane.o
+
+obj-$(CONFIG_DRM_IMX_DCSS) += imx-dcss.o
+
diff --git a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c 
b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
new file mode 100644
index ..c9b54bb2692d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP.
+ */
+
+#include 
+#include 
+#include 
+
+#include "dcss-dev.h"
+
+#define DCSS_BLKCTL_RESET_CTRL 0x00
+#define   B_CLK_RESETN BIT(0)
+#define   APB_CLK_RESETN   BIT(1)
+#define   P_CLK_RESETN BIT(2)
+#define   RTR_CLK_RESETN   BIT(4)
+#define DCSS_BLKCTL_CONTROL0   0x10
+#define   HDMI_MIPI_CLK_SELBIT(0)
+#define   D

[PATCH v5 3/5] drm/imx/dcss: add component framework functionality

[Laurentiu Palcu]

From: Laurentiu Palcu 

Component framework is needed by HDP driver.

Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/imx/dcss/dcss-drv.c | 89 ++---
 drivers/gpu/drm/imx/dcss/dcss-kms.c | 14 -
 drivers/gpu/drm/imx/dcss/dcss-kms.h |  4 +-
 3 files changed, 80 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/imx/dcss/dcss-drv.c 
b/drivers/gpu/drm/imx/dcss/dcss-drv.c
index 8dc2f85c514b..09d0ac28e28a 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-drv.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-drv.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "dcss-dev.h"
@@ -14,6 +15,8 @@
 struct dcss_drv {
struct dcss_dev *dcss;
struct dcss_kms_dev *kms;
+
+   bool is_componentized;
 };
 
 struct dcss_dev *dcss_drv_dev_to_dcss(struct device *dev)
@@ -30,30 +33,18 @@ struct drm_device *dcss_drv_dev_to_drm(struct device *dev)
return mdrv ? >kms->base : NULL;
 }
 
-static int dcss_drv_platform_probe(struct platform_device *pdev)
+static int dcss_drv_init(struct device *dev, bool componentized)
 {
-   struct device *dev = >dev;
-   struct device_node *remote;
struct dcss_drv *mdrv;
int err = 0;
-   bool hdmi_output = true;
-
-   if (!dev->of_node)
-   return -ENODEV;
-
-   remote = of_graph_get_remote_node(dev->of_node, 0, 0);
-   if (!remote)
-   return -ENODEV;
-
-   hdmi_output = !of_device_is_compatible(remote, "fsl,imx8mq-nwl-dsi");
-
-   of_node_put(remote);
 
mdrv = kzalloc(sizeof(*mdrv), GFP_KERNEL);
if (!mdrv)
return -ENOMEM;
 
-   mdrv->dcss = dcss_dev_create(dev, hdmi_output);
+   mdrv->is_componentized = componentized;
+
+   mdrv->dcss = dcss_dev_create(dev, componentized);
if (IS_ERR(mdrv->dcss)) {
err = PTR_ERR(mdrv->dcss);
goto err;
@@ -61,7 +52,7 @@ static int dcss_drv_platform_probe(struct platform_device 
*pdev)
 
dev_set_drvdata(dev, mdrv);
 
-   mdrv->kms = dcss_kms_attach(mdrv->dcss);
+   mdrv->kms = dcss_kms_attach(mdrv->dcss, componentized);
if (IS_ERR(mdrv->kms)) {
err = PTR_ERR(mdrv->kms);
goto dcss_shutoff;
@@ -79,19 +70,73 @@ static int dcss_drv_platform_probe(struct platform_device 
*pdev)
return err;
 }
 
-static int dcss_drv_platform_remove(struct platform_device *pdev)
+static void dcss_drv_deinit(struct device *dev, bool componentized)
 {
-   struct dcss_drv *mdrv = dev_get_drvdata(>dev);
+   struct dcss_drv *mdrv = dev_get_drvdata(dev);
 
if (!mdrv)
-   return 0;
+   return;
 
-   dcss_kms_detach(mdrv->kms);
+   dcss_kms_detach(mdrv->kms, componentized);
dcss_dev_destroy(mdrv->dcss);
 
-   dev_set_drvdata(>dev, NULL);
+   dev_set_drvdata(dev, NULL);
 
kfree(mdrv);
+}
+
+static int dcss_drv_bind(struct device *dev)
+{
+   return dcss_drv_init(dev, true);
+}
+
+static void dcss_drv_unbind(struct device *dev)
+{
+   return dcss_drv_deinit(dev, true);
+}
+
+static const struct component_master_ops dcss_master_ops = {
+   .bind   = dcss_drv_bind,
+   .unbind = dcss_drv_unbind,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+   return dev->of_node == data;
+}
+
+static int dcss_drv_platform_probe(struct platform_device *pdev)
+{
+   struct device *dev = >dev;
+   struct component_match *match = NULL;
+   struct device_node *remote;
+
+   if (!dev->of_node)
+   return -ENODEV;
+
+   remote = of_graph_get_remote_node(dev->of_node, 0, 0);
+   if (!remote)
+   return -ENODEV;
+
+   if (of_device_is_compatible(remote, "fsl,imx8mq-nwl-dsi")) {
+   of_node_put(remote);
+   return dcss_drv_init(dev, false);
+   }
+
+   drm_of_component_match_add(dev, , compare_of, remote);
+   of_node_put(remote);
+
+   return component_master_add_with_match(dev, _master_ops, match);
+}
+
+static int dcss_drv_platform_remove(struct platform_device *pdev)
+{
+   struct dcss_drv *mdrv = dev_get_drvdata(>dev);
+
+   if (mdrv->is_componentized)
+   component_master_del(>dev, _master_ops);
+   else
+   dcss_drv_deinit(>dev, false);
 
return 0;
 }
diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c 
b/drivers/gpu/drm/imx/dcss/dcss-kms.c
index 3ca49d0a3e61..bb009f3a878f 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "dcss-dev.h"
 #include "dcss-kms.h"
@@ -106,7 +107,7 @@ static int dcss_kms_setup_encoder(struct dcss_kms_dev *kms)
return drm_bridge_attach(encoder, bridge, NULL, 0);
 }
 
-struct dcss_kms_dev *dcss_kms_atta

[PATCH v5 0/4] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

From: Laurentiu Palcu 

Hi,

This patchset adds initial DCSS support for iMX8MQ chip. Initial support
includes only graphics plane support (no video planes), no HDR10 capabilities,
no graphics decompression (only linear, tiled and super-tiled buffers allowed).

Support for the rest of the features will be added incrementally, in subsequent
patches.

The patchset was tested with both HDP driver (in the downstream tree) and the 
upstream
MIPI-DSI driver (with a couple of patches on top, to make it work correctly 
with DCSS).

Thanks,
Laurentiu

Changes in v5:
 * Rebased to latest;
 * Took out component framework support and made it a separate patch so
   that people can still test with HDP driver, which makes use of it.
   But the idea is to get rid of it once HDP driver's next versions
   will remove component framework as well;
 * Slight improvement to modesetting: avoid cutting off the pixel clock
   if the new mode and the old one are equal. Also, in this case, is
   not necessary to wait for DTG to shut off. This would allow to switch
   from 8b RGB to 12b YUV422, for example, with no interruptions (at least
   from DCSS point of view);
 * Do not fire off CTXLD when going to suspend, unless it still has
   entries that need to be committed to DCSS;
 * Addressed Rob's comments on bindings;

Changes in v4:
 * Addressed Lucas and Philipp's comments:
   * Added DRM_KMS_CMA_HELPER dependency in Kconfig;
   * Removed usage of devm_ functions since I'm already doing all the
 clean-up in the submodules_deinit();
   * Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush();
   * Removed en_completion variable from dcss_crtc since this was
 introduced mainly to avoid vblank timeout warnings which were fixed
 by arming the vblank event in flush() instead of begin();
   * Removed clks_on and irq_enabled flags since all the calls to
 enabling/disabling clocks and interrupts were balanced;
   * Removed the custom atomic_commit callback and used the DRM core
 helper and, in the process, got rid of a workqueue that wasn't
 necessary anymore;
   * Fixed some minor DT binding issues flagged by Philipp;
   * Some other minor changes suggested by Lucas;
 * Removed YUV formats from the supported formats as these cannot work
   without the HDR10 module CSCs and LUTs. Will add them back when I
   will add support for video planes;

Changes in v3:
 * rebased to latest linux-next and made it compile as drmP.h was
   removed;
 * removed the patch adding the VIDEO2_PLL clock. It's already applied;
 * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set();
 * fixed a a spurious hang reported by Lukas Hartmann and encountered
   by me several times;
 * mask DPR and DTG interrupts by default, as they may come enabled from
   U-boot;

Changes in v2:
 * Removed '0x' in node's unit-address both in DT and yaml;
 * Made the address region size lowercase, to be consistent;
 * Removed some left-over references to P010;
 * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence 
compilation
   issues reported by kbuild for other architectures;

Laurentiu Palcu (5):
  drm/imx: compile imx directory by default
  drm/imx: Add initial support for DCSS on iMX8MQ
  drm/imx/dcss: add component framework functionality
  dt-bindings: display: imx: add bindings for DCSS
  arm64: dts: imx8mq: add DCSS node

 .../bindings/display/imx/nxp,imx8mq-dcss.yaml |  84 ++
 arch/arm64/boot/dts/freescale/imx8mq.dtsi |  23 +
 drivers/gpu/drm/Makefile  |   2 +-
 drivers/gpu/drm/imx/Kconfig   |   2 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig  |   9 +
 drivers/gpu/drm/imx/dcss/Makefile |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c|  70 ++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c  | 219 +
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c | 424 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c   | 314 +++
 drivers/gpu/drm/imx/dcss/dcss-dev.h   | 177 
 drivers/gpu/drm/imx/dcss/dcss-dpr.c   | 562 
 drivers/gpu/drm/imx/dcss/dcss-drv.c   | 183 
 drivers/gpu/drm/imx/dcss/dcss-dtg.c   | 409 +
 drivers/gpu/drm/imx/dcss/dcss-kms.c   | 185 
 drivers/gpu/drm/imx/dcss/dcss-kms.h   |  43 +
 drivers/gpu/drm/imx/dcss/dcss-plane.c | 405 +
 drivers/gpu/drm/imx/dcss/dcss-scaler.c| 826 ++
 drivers/gpu/drm/imx/dcss/dcss-ss.c| 180 
 20 files changed, 4123 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
 create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
 create mod

[PATCH v5 5/5] arm64: dts: imx8mq: add DCSS node

[Laurentiu Palcu]

From: Laurentiu Palcu 

This patch adds the node for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu 
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 978f8122c0d2..022720cdf6ed 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1040,6 +1040,29 @@
#size-cells = <1>;
ranges = <0x32c0 0x32c0 0x40>;
 
+   dcss: display-controller@32e0 {
+   compatible = "nxp,imx8mq-dcss";
+   reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+   interrupts = <6>, <8>, <9>;
+   interrupt-names = "ctxld", "ctxld_kick", 
"vblank";
+   interrupt-parent = <>;
+   clocks = < IMX8MQ_CLK_DISP_APB_ROOT>,
+< IMX8MQ_CLK_DISP_AXI_ROOT>,
+< IMX8MQ_CLK_DISP_RTRM_ROOT>,
+< IMX8MQ_VIDEO2_PLL_OUT>,
+< IMX8MQ_CLK_DISP_DTRC>;
+   clock-names = "apb", "axi", "rtrm", "pix", 
"dtrc";
+   assigned-clocks = < IMX8MQ_CLK_DISP_AXI>,
+ < IMX8MQ_CLK_DISP_RTRM>,
+ < 
IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+   assigned-clock-parents = < 
IMX8MQ_SYS1_PLL_800M>,
+< 
IMX8MQ_SYS1_PLL_800M>,
+< IMX8MQ_CLK_27M>;
+   assigned-clock-rates = <8>,
+  <4>;
+   status = "disabled";
+   };
+
irqsteer: interrupt-controller@32e2d000 {
compatible = "fsl,imx8m-irqsteer", 
"fsl,imx-irqsteer";
reg = <0x32e2d000 0x1000>;
-- 
2.23.0

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[PATCH v5 4/5] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

From: Laurentiu Palcu 

Add bindings for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu 
---
 .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 84 +++
 1 file changed, 84 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 
b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
new file mode 100644
index ..a951409cf76d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: iMX8MQ Display Controller Subsystem (DCSS)
+
+maintainers:
+  - Laurentiu Palcu 
+
+description:
+
+  The DCSS (display controller sub system) is used to source up to three
+  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
+  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
+  image processing capabilities are included to provide a solution capable of
+  driving next generation high dynamic range displays.
+
+properties:
+  compatible:
+const: nxp,imx8mq-dcss
+
+  reg:
+items:
+  - description: DCSS base address and size, up to IRQ steer start
+  - description: DCSS BLKCTL base address and size
+
+  interrupts:
+items:
+  - description: Context loader completion and error interrupt
+  - description: DTG interrupt used to signal context loader trigger time
+  - description: DTG interrupt for Vblank
+
+  interrupt-names:
+items:
+  - const: ctxld
+  - const: ctxld_kick
+  - const: vblank
+
+  clocks:
+items:
+  - description: Display APB clock for all peripheral PIO access interfaces
+  - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
+  - description: RTRAM clock
+  - description: Pixel clock, can be driver either by HDMI phy clock or 
MIPI
+  - description: DTRC clock, needed by video decompressor
+
+  clock-names:
+items:
+  - const: apb
+  - const: axi
+  - const: rtrm
+  - const: pix
+  - const: dtrc
+
+  port:
+type: object
+description:
+  A port node pointing to the input port of a HDMI/DP or MIPI display 
bridge.
+
+examples:
+  - |
+dcss: display-controller@32e0 {
+compatible = "nxp,imx8mq-dcss";
+reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+interrupts = <6>, <8>, <9>;
+interrupt-names = "ctxld", "ctxld_kick", "vblank";
+interrupt-parent = <>;
+clocks = < 248>, < 247>, < 249>,
+ < 254>,< 122>;
+clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+assigned-clocks = < 107>, < 109>, < 266>;
+assigned-clock-parents = < 78>, < 78>, < 3>;
+assigned-clock-rates = <8>,
+   <4>;
+port {
+dcss_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
-- 
2.23.0

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[PATCH v5 1/5] drm/imx: compile imx directory by default

[Laurentiu Palcu]

From: Laurentiu Palcu 

Currently the drm/imx/ directory is compiled only if DRM_IMX is set. Adding a
new IMX related IP in the same directory would need DRM_IMX to be set, which 
would
bring in also IPUv3 core driver...

The current patch would allow adding new IPs in the imx/ directory without 
needing
to set DRM_IMX.

Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 2c0e5a7e5953..c4d12e756c63 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -100,7 +100,7 @@ obj-$(CONFIG_DRM_MSM) += msm/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-$(CONFIG_DRM_STM) += stm/
 obj-$(CONFIG_DRM_STI) += sti/
-obj-$(CONFIG_DRM_IMX) += imx/
+obj-y  += imx/
 obj-$(CONFIG_DRM_INGENIC) += ingenic/
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
 obj-$(CONFIG_DRM_MESON)+= meson/
-- 
2.23.0

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Re: [PATCH v4 2/4] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

Hi Guido,

On Fri, May 15, 2020 at 11:27:19AM +0200, Guido Günther wrote:
> Hi Laurentiu,
> On Fri, Mar 06, 2020 at 02:49:26PM +0200, Laurentiu Palcu wrote:
> > From: Laurentiu Palcu 
> > 
> > This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
> > Some of its capabilities include:
> >  * 4K@60fps;
> >  * HDR10;
> >  * one graphics and 2 video pipelines;
> >  * on-the-fly decompression of compressed video and graphics;
> > 
> > The reference manual can be found here:
> > https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM
> > 
> > The current patch adds only basic functionality: one primary plane for
> > graphics, linear, tiled and super-tiled buffers support (no graphics
> > decompression yet), no HDR10 and no video planes.
> > 
> > Video planes support and HDR10 will be added in subsequent patches once
> > per-plane de-gamma/CSC/gamma support is in.
> > 
> > Signed-off-by: Laurentiu Palcu 
> > ---
> >  drivers/gpu/drm/imx/Kconfig|   2 +
> >  drivers/gpu/drm/imx/Makefile   |   1 +
> >  drivers/gpu/drm/imx/dcss/Kconfig   |   9 +
> >  drivers/gpu/drm/imx/dcss/Makefile  |   6 +
> >  drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  73 +++
> >  drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 206 ++
> >  drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 431 +
> >  drivers/gpu/drm/imx/dcss/dcss-dev.c| 277 +
> >  drivers/gpu/drm/imx/dcss/dcss-dev.h| 172 +
> >  drivers/gpu/drm/imx/dcss/dcss-dpr.c| 562 +
> >  drivers/gpu/drm/imx/dcss/dcss-drv.c| 183 ++
> >  drivers/gpu/drm/imx/dcss/dcss-dtg.c| 413 +
> >  drivers/gpu/drm/imx/dcss/dcss-kms.c| 188 ++
> >  drivers/gpu/drm/imx/dcss/dcss-kms.h|  43 ++
> >  drivers/gpu/drm/imx/dcss/dcss-plane.c  | 405 
> >  drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
> >  drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++
> >  17 files changed, 3977 insertions(+)
> >  create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
> >  create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
> >  create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c
> > 
> > diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
> > index 207bf7409dfb..6231048aa5aa 100644
> > --- a/drivers/gpu/drm/imx/Kconfig
> > +++ b/drivers/gpu/drm/imx/Kconfig
> > @@ -39,3 +39,5 @@ config DRM_IMX_HDMI
> > depends on DRM_IMX
> > help
> >   Choose this if you want to use HDMI on i.MX6.
> > +
> > +source "drivers/gpu/drm/imx/dcss/Kconfig"
> > diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
> > index 21cdcc2faabc..b644deffe948 100644
> > --- a/drivers/gpu/drm/imx/Makefile
> > +++ b/drivers/gpu/drm/imx/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
> >  obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
> >  
> >  obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
> > +obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
> > diff --git a/drivers/gpu/drm/imx/dcss/Kconfig 
> > b/drivers/gpu/drm/imx/dcss/Kconfig
> > new file mode 100644
> > index ..988979bc22cc
> > --- /dev/null
> > +++ b/drivers/gpu/drm/imx/dcss/Kconfig
> > @@ -0,0 +1,9 @@
> > +config DRM_IMX_DCSS
> > +   tristate "i.MX8MQ DCSS"
> > +   select RESET_CONTROLLER
> > +   select IMX_IRQSTEER
> > +   select DRM_KMS_CMA_HELPER
> > +   depends on DRM && ARCH_MXC
> > +   help
> > + Choose this if you have a NXP i.MX8MQ based system and want to use the
> > + Display Controller Subsystem. This option enables DCSS support.
> > diff --git a/drivers/gpu/drm/imx/dcss/Makefile 
> > b/drivers/gpu/drm/imx/dcss/Makefile
> > new file mode 100644
> > index .

[PATCH v4 4/4] arm64: dts: imx8mq: add DCSS node

[Laurentiu Palcu]

From: Laurentiu Palcu 

This patch adds the node for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu 
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a1e83922c71..e04d8bbae6e8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1028,6 +1028,29 @@
#size-cells = <1>;
ranges = <0x32c0 0x32c0 0x40>;
 
+   dcss: display-controller@32e0 {
+   compatible = "nxp,imx8mq-dcss";
+   reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+   interrupts = <6>, <8>, <9>;
+   interrupt-names = "ctxld", "ctxld_kick", 
"vblank";
+   interrupt-parent = <>;
+   clocks = < IMX8MQ_CLK_DISP_APB_ROOT>,
+< IMX8MQ_CLK_DISP_AXI_ROOT>,
+< IMX8MQ_CLK_DISP_RTRM_ROOT>,
+< IMX8MQ_VIDEO2_PLL_OUT>,
+< IMX8MQ_CLK_DISP_DTRC>;
+   clock-names = "apb", "axi", "rtrm", "pix", 
"dtrc";
+   assigned-clocks = < IMX8MQ_CLK_DISP_AXI>,
+ < IMX8MQ_CLK_DISP_RTRM>,
+ < 
IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+   assigned-clock-parents = < 
IMX8MQ_SYS1_PLL_800M>,
+< 
IMX8MQ_SYS1_PLL_800M>,
+< IMX8MQ_CLK_27M>;
+   assigned-clock-rates = <8>,
+  <4>;
+   status = "disabled";
+   };
+
irqsteer: interrupt-controller@32e2d000 {
compatible = "fsl,imx8m-irqsteer", 
"fsl,imx-irqsteer";
reg = <0x32e2d000 0x1000>;
-- 
2.17.1

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[PATCH v4 0/4] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

From: Laurentiu Palcu 

Hi,

This patchset adds initial DCSS support for iMX8MQ chip. Initial support
includes only graphics plane support (no video planes), no HDR10 capabilities,
no graphics decompression (only linear, tiled and super-tiled buffers allowed).

Support for the rest of the features will be added incrementally, in subsequent
patches.

The patchset was tested with both HDP driver (not yet upstreamed) and MIPI-DSI
(drivers already on the dri-devel ML).

Thanks,
Laurentiu

Changes in v4:
 * Addressed Lucas and Philipp's comments:
   * Added DRM_KMS_CMA_HELPER dependency in Kconfig;
   * Removed usage of devm_ functions since I'm already doing all the
 clean-up in the submodules_deinit();
   * Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush();
   * Removed en_completion variable from dcss_crtc since this was
 introduced mainly to avoid vblank timeout warnings which were fixed
 by arming the vblank event in flush() instead of begin();
   * Removed clks_on and irq_enabled flags since all the calls to
 enabling/disabling clocks and interrupts were balanced;
   * Removed the custom atomic_commit callback and used the DRM core
 helper and, in the process, got rid of a workqueue that wasn't
 necessary anymore;
   * Fixed some minor DT binding issues flagged by Philipp;
   * Some other minor changes suggested by Lucas;
 * Removed YUV formats from the supported formats as these cannot work
   without the HDR10 module CSCs and LUTs. Will add them back when I
   will add support for video planes;

Changes in v3:
 * rebased to latest linux-next and made it compile as drmP.h was
   removed;
 * removed the patch adding the VIDEO2_PLL clock. It's already applied;
 * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set();
 * fixed a a spurious hang reported by Lukas Hartmann and encountered
   by me several times;
 * mask DPR and DTG interrupts by default, as they may come enabled from
   U-boot;

Changes in v2:
 * Removed '0x' in node's unit-address both in DT and yaml;
 * Made the address region size lowercase, to be consistent;
 * Removed some left-over references to P010;
 * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence 
compilation
   issues reported by kbuild for other architectures;


Laurentiu Palcu (4):
  drm/imx: compile imx directory by default
  drm/imx: Add initial support for DCSS on iMX8MQ
  dt-bindings: display: imx: add bindings for DCSS
  arm64: dts: imx8mq: add DCSS node

 .../bindings/display/imx/nxp,imx8mq-dcss.yaml |  85 ++
 arch/arm64/boot/dts/freescale/imx8mq.dtsi |  23 +
 drivers/gpu/drm/Makefile  |   2 +-
 drivers/gpu/drm/imx/Kconfig   |   2 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig  |   9 +
 drivers/gpu/drm/imx/dcss/Makefile |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c|  73 ++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c  | 206 +
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c | 431 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c   | 277 ++
 drivers/gpu/drm/imx/dcss/dcss-dev.h   | 172 
 drivers/gpu/drm/imx/dcss/dcss-dpr.c   | 562 
 drivers/gpu/drm/imx/dcss/dcss-drv.c   | 183 
 drivers/gpu/drm/imx/dcss/dcss-dtg.c   | 413 +
 drivers/gpu/drm/imx/dcss/dcss-kms.c   | 188 
 drivers/gpu/drm/imx/dcss/dcss-kms.h   |  43 +
 drivers/gpu/drm/imx/dcss/dcss-plane.c | 405 +
 drivers/gpu/drm/imx/dcss/dcss-scaler.c| 826 ++
 drivers/gpu/drm/imx/dcss/dcss-ss.c| 180 
 20 files changed, 4086 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
 create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c

-- 
2.17.1

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[PATCH v4 1/4] drm/imx: compile imx directory by default

[Laurentiu Palcu]

From: Laurentiu Palcu 

Currently the drm/imx/ directory is compiled only if DRM_IMX is set. Adding a
new IMX related IP in the same directory would need DRM_IMX to be set, which 
would
bring in also IPUv3 core driver...

The current patch would allow adding new IPs in the imx/ directory without 
needing
to set DRM_IMX.

Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 7f72ef5e7811..5272ebd5ce8e 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -101,7 +101,7 @@ obj-$(CONFIG_DRM_MSM) += msm/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-$(CONFIG_DRM_STM) += stm/
 obj-$(CONFIG_DRM_STI) += sti/
-obj-$(CONFIG_DRM_IMX) += imx/
+obj-y  += imx/
 obj-$(CONFIG_DRM_INGENIC) += ingenic/
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
 obj-$(CONFIG_DRM_MESON)+= meson/
-- 
2.17.1

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[PATCH v4 3/4] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

From: Laurentiu Palcu 

Add bindings for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu 
---
 .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 85 +++
 1 file changed, 85 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 
b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
new file mode 100644
index ..fde6ec8cb0c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: iMX8MQ Display Controller Subsystem (DCSS)
+
+maintainers:
+  - Laurentiu Palcu 
+
+description:
+
+  The DCSS (display controller sub system) is used to source up to three
+  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
+  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
+  image processing capabilities are included to provide a solution capable of
+  driving next generation high dynamic range displays.
+
+properties:
+  compatible:
+const: nxp,imx8mq-dcss
+
+  reg:
+maxItems: 2
+
+  interrupts:
+maxItems: 3
+items:
+  - description: Context loader completion and error interrupt
+  - description: DTG interrupt used to signal context loader trigger time
+  - description: DTG interrupt for Vblank
+
+  interrupt-names:
+maxItems: 3
+items:
+  - const: ctxld
+  - const: ctxld_kick
+  - const: vblank
+
+  clocks:
+maxItems: 5
+items:
+  - description: Display APB clock for all peripheral PIO access interfaces
+  - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
+  - description: RTRAM clock
+  - description: Pixel clock, can be driver either by HDMI phy clock or 
MIPI
+  - description: DTRC clock, needed by video decompressor
+
+  clock-names:
+items:
+  - const: apb
+  - const: axi
+  - const: rtrm
+  - const: pix
+  - const: dtrc
+
+  port:
+type: object
+description:
+  A port node pointing to the input port of a HDMI/DP or MIPI display 
bridge.
+
+examples:
+  - |
+dcss: display-controller@32e0 {
+compatible = "nxp,imx8mq-dcss";
+reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+interrupts = <6>, <8>, <9>;
+interrupt-names = "ctxld", "ctxld_kick", "vblank";
+interrupt-parent = <>;
+clocks = < 248>, < 247>, < 249>,
+ < 254>,< 122>;
+clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+assigned-clocks = < 107>, < 109>, < 266>;
+assigned-clock-parents = < 78>, < 78>, < 3>;
+assigned-clock-rates = <8>,
+   <4>;
+port {
+dcss_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
-- 
2.17.1

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[PATCH v4 2/4] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

From: Laurentiu Palcu 

This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
Some of its capabilities include:
 * 4K@60fps;
 * HDR10;
 * one graphics and 2 video pipelines;
 * on-the-fly decompression of compressed video and graphics;

The reference manual can be found here:
https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM

The current patch adds only basic functionality: one primary plane for
graphics, linear, tiled and super-tiled buffers support (no graphics
decompression yet), no HDR10 and no video planes.

Video planes support and HDR10 will be added in subsequent patches once
per-plane de-gamma/CSC/gamma support is in.

Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/imx/Kconfig|   2 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig   |   9 +
 drivers/gpu/drm/imx/dcss/Makefile  |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  73 +++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 206 ++
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 431 +
 drivers/gpu/drm/imx/dcss/dcss-dev.c| 277 +
 drivers/gpu/drm/imx/dcss/dcss-dev.h| 172 +
 drivers/gpu/drm/imx/dcss/dcss-dpr.c| 562 +
 drivers/gpu/drm/imx/dcss/dcss-drv.c| 183 ++
 drivers/gpu/drm/imx/dcss/dcss-dtg.c| 413 +
 drivers/gpu/drm/imx/dcss/dcss-kms.c| 188 ++
 drivers/gpu/drm/imx/dcss/dcss-kms.h|  43 ++
 drivers/gpu/drm/imx/dcss/dcss-plane.c  | 405 
 drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
 drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++
 17 files changed, 3977 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..6231048aa5aa 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,5 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+source "drivers/gpu/drm/imx/dcss/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..b644deffe948 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
diff --git a/drivers/gpu/drm/imx/dcss/Kconfig b/drivers/gpu/drm/imx/dcss/Kconfig
new file mode 100644
index ..988979bc22cc
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Kconfig
@@ -0,0 +1,9 @@
+config DRM_IMX_DCSS
+   tristate "i.MX8MQ DCSS"
+   select RESET_CONTROLLER
+   select IMX_IRQSTEER
+   select DRM_KMS_CMA_HELPER
+   depends on DRM && ARCH_MXC
+   help
+ Choose this if you have a NXP i.MX8MQ based system and want to use the
+ Display Controller Subsystem. This option enables DCSS support.
diff --git a/drivers/gpu/drm/imx/dcss/Makefile 
b/drivers/gpu/drm/imx/dcss/Makefile
new file mode 100644
index ..8c7c8da42792
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/Makefile
@@ -0,0 +1,6 @@
+imx-dcss-objs := dcss-drv.o dcss-dev.o dcss-blkctl.o dcss-ctxld.o dcss-dtg.o \
+dcss-ss.o dcss-dpr.o dcss-scaler.o dcss-kms.o 
dcss-crtc.o \
+dcss-plane.o
+
+obj-$(CONFIG_DRM_IMX_DCSS) += imx-dcss.o
+
diff --git a/drivers/gpu/drm/imx/dcss/dcss-blkctl.c 
b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
new file mode 100644
index ..0276917f409f
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcss/dcss-blkctl.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP.
+ */
+
+#include 
+#include 
+#include 
+
+#include "dcss-dev.h"
+
+#define DCSS_BLKCTL_RESET_CTRL 0x00
+#define   B_CLK_RESETN BIT(0)
+#define   APB_CLK_RESETN   BIT(1)
+#define   P_CLK_RESETN BIT(2)
+#define   RTR_CLK_RESETN   BIT(3)
+#define DCSS_BLKCTL_CONTROL0   0x10
+#define   HDMI_MIPI_CLK_SELBIT(0)
+#define   D

Re: [PATCH v3 2/4] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

Hi Philipp,

On Fri, Mar 06, 2020 at 11:20:51AM +0100, Philipp Zabel wrote:
> Hi Laurentiu,
> 
> On Fri, 2020-03-06 at 11:58 +0200, Laurentiu Palcu wrote:
> > On Wed, Feb 26, 2020 at 02:19:11PM +0100, Lucas Stach wrote:
> [...]
> > > > +/* This function will be called from interrupt context. */
> > > > +void dcss_scaler_write_sclctrl(struct dcss_scaler *scl)
> > > > +{
> > > > +   int chnum;
> > > > +
> > > > +   for (chnum = 0; chnum < 3; chnum++) {
> > > > +   struct dcss_scaler_ch *ch = >ch[chnum];
> > > > +
> > > > +   if (ch->scaler_ctrl_chgd) {
> > > > +   dcss_ctxld_write_irqsafe(scl->ctxld, 
> > > > scl->ctx_id,
> > > > +ch->scaler_ctrl,
> > > > +ch->base_ofs +
> > > > +DCSS_SCALER_CTRL);
> > > 
> > > Why is this using the _irqsafe variant without any locking? Won't this
> > > lead to potential internal state corruption? dcss_ctxld_write is using
> > > the _irqsave locking variants, so it fine with being called from IRQ
> > > context.
> > 
> > This is only called from __dcss_ctxld_enable() which is already protected
> > by lock/unlock in dcss_ctxld_kick().
> 
> You could add a lockdep_assert_held() line to the top of this function
> to make it clear this depends on the lock being held.

Thanks for the suggestion. Will add a check.

Thanks,
laurentiu
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Re: [PATCH v3 2/4] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

Hi Lucas,

Thanks for the in-depth review. I will send a new version shortly, with
most of your sugestions implemented. Had to run some regression tests
on the new version though, hence my late reply... :/

There are several answers to your questions in-line. Didn't reply to all
of them though as your suggestions were ok and implemented them directly
in v4.

On Wed, Feb 26, 2020 at 02:19:11PM +0100, Lucas Stach wrote:
> Hi Laurentiu,
> 
> again a day later than promised, but here we go with some more
> in-depth comments. Apologies if I missed something, my metal bandwidth
> was pretty exhausted by the time I made my was to the scaler code. :)
> 
> On Fr, 2019-12-06 at 11:52 +0200, Laurentiu Palcu wrote:
> > This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
> > Some of its capabilities include:
> >  * 4K@60fps;
> >  * HDR10;
> >  * one graphics and 2 video pipelines;
> >  * on-the-fly decompression of compressed video and graphics;
> > 
> > The reference manual can be found here:
> > https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM
> > 
> > The current patch adds only basic functionality: one primary plane for
> > graphics, linear, tiled and super-tiled buffers support (no graphics
> > decompression yet), no HDR10 and no video planes.
> > 
> > Video planes support and HDR10 will be added in subsequent patches once
> > per-plane de-gamma/CSC/gamma support is in.
> > 
> > Signed-off-by: Laurentiu Palcu 
> > ---
>

[...]

> > diff --git a/drivers/gpu/drm/imx/dcss/dcss-crtc.c 
> > b/drivers/gpu/drm/imx/dcss/dcss-crtc.c
> > new file mode 100644
> > index ..567bf07
> > --- /dev/null
> > +++ b/drivers/gpu/drm/imx/dcss/dcss-crtc.c
> > @@ -0,0 +1,224 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2019 NXP.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "dcss-dev.h"
> > +#include "dcss-kms.h"
> > +
> > +static int dcss_enable_vblank(struct drm_crtc *crtc)
> > +{
> > +   struct dcss_crtc *dcss_crtc = container_of(crtc, struct dcss_crtc,
> > +  base);
> > +   struct dcss_dev *dcss = crtc->dev->dev_private;
> > +
> > +   if (dcss_crtc->irq_enabled)
> > +   return 0;
> > +
> > +   dcss_crtc->irq_enabled = true;
> 
> This state should not be necessary. Unless there is a reference
> counting bug somewhere in the driver, the DRM core should never call
> enable_vblank and disable_vblank unbalanced.
> 
> > +
> > +   dcss_dtg_vblank_irq_enable(dcss->dtg, true);
> > +
> > +   dcss_dtg_ctxld_kick_irq_enable(dcss->dtg, true);
> > +
> > +   enable_irq(dcss_crtc->irq);
> > +
> > +   return 0;
> > +}
> > +
> > +static void dcss_disable_vblank(struct drm_crtc *crtc)
> > +{
> > +   struct dcss_crtc *dcss_crtc = container_of(crtc, struct dcss_crtc,
> > +  base);
> > +   struct dcss_dev *dcss = dcss_crtc->base.dev->dev_private;
> > +
> > +   disable_irq_nosync(dcss_crtc->irq);
> > +
> > +   dcss_dtg_vblank_irq_enable(dcss->dtg, false);
> > +
> > +   dcss_dtg_ctxld_kick_irq_enable(dcss->dtg, false);
> > +
> > +   dcss_crtc->irq_enabled = false;
> > +}
> > +
> > +static const struct drm_crtc_funcs dcss_crtc_funcs = {
> > +   .set_config = drm_atomic_helper_set_config,
> > +   .destroy = drm_crtc_cleanup,
> > +   .page_flip = drm_atomic_helper_page_flip,
> > +   .reset = drm_atomic_helper_crtc_reset,
> > +   .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> > +   .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> > +   .enable_vblank = dcss_enable_vblank,
> > +   .disable_vblank = dcss_disable_vblank,
> > +};
> > +
> > +static void dcss_crtc_atomic_begin(struct drm_crtc *crtc,
> > +  struct drm_crtc_state *old_crtc_state)
> > +{
> > +   drm_crtc_vblank_on(crtc);
> > +
> > +   spin_lock_irq(>dev->event_lock);
> > +   if (crtc->state->event) {
> > +   WARN_ON(drm_crtc_vblank_get(crtc));
> > +   drm_crtc_arm_vblank_event(crtc, crtc->state->event);
> 
> Arming of the vblank event should move into atomic flush. Otherwise the
> state update is racing with the vblank IRQ. In practice you probably
> don't hit this issue on a moderately load

Re: [PATCH v3 3/4] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

Hi Lucas,

On Mon, Feb 24, 2020 at 06:21:57PM +0100, Lucas Stach wrote:
> On Fr, 2019-12-06 at 11:52 +0200, Laurentiu Palcu wrote:
> > Add bindings for iMX8MQ Display Controller Subsystem.
> > 
> > Signed-off-by: Laurentiu Palcu 
> > Reviewed-by: Rob Herring 
> > ---
> >  .../bindings/display/imx/nxp,imx8mq-dcss.yaml  | 86 
> > ++
> >  1 file changed, 86 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 
> > b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > new file mode 100644
> > index ..efd2494
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > @@ -0,0 +1,86 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright 2019 NXP
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> > +
> > +title: iMX8MQ Display Controller Subsystem (DCSS)
> > +
> > +maintainers:
> > +  - Laurentiu Palcu 
> > +
> > +description:
> > +
> > +  The DCSS (display controller sub system) is used to source up to three
> > +  display buffers, compose them, and drive a display using HDMI 2.0a(with 
> > HDCP
> > +  2.2) or MIPI-DSI.
> 
> HDMI 2.0a and MIPI_DSI are not really properties of the DCSS, but
> rather the connected bridges. Maybe just drop them here?

I'm a bit confused... Drop what here?

> 
> >  The DCSS is intended to support up to 4kp60 displays. HDR10
> > +  image processing capabilities are included to provide a solution capable 
> > of
> > +  driving next generation high dynamic range displays.
> > +
> > +properties:
> > +  compatible:
> > +const: nxp,imx8mq-dcss
> > +
> > +  reg:
> > +maxItems: 2
> > +
> > +  interrupts:
> > +maxItems: 3
> > +items:
> > +  - description: Context loader completion and error interrupt
> > +  - description: DTG interrupt used to signal context loader trigger 
> > time
> > +  - description: DTG interrupt for Vblank
> > +
> > +  interrupt-names:
> > +maxItems: 3
> > +items:
> > +  - const: ctx_ld
> 
> Can we make this just "ctxld" for a bit more consistency with the name
> below?

Fair enough. Will change.

> 
> > +  - const: ctxld_kick
> > +  - const: vblank
> > +
> > +  clocks:
> > +maxItems: 5
> > +items:
> > +  - description: Display APB clock for all peripheral PIO access 
> > interfaces
> > +  - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
> > +  - description: RTRAM clock
> > +  - description: Pixel clock, can be driver either by HDMI phy clock 
> > or MIPI
> > +  - description: DTRC clock, needed by video decompressor
> > +
> > +  clock-names:
> > +items:
> > +  - const: apb
> > +  - const: axi
> > +  - const: rtrm
> > +  - const: pix
> > +  - const: dtrc
> > +
> > +  port@0:
> > +type: object
> > +description: A port node pointing to a hdmi_in or mipi_in port node.
> 
> "A port node pointing to the input port of a HDMI/DP or MIPI display
> bridge".

Okay, your description's sounds better. I'll add it in the next revision.

Thanks,
laurentiu

> 
> > +
> > +examples:
> > +  - |
> > +dcss: display-controller@32e0 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "nxp,imx8mq-dcss";
> > +reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
> > +interrupts = <6>, <8>, <9>;
> > +interrupt-names = "ctx_ld", "ctxld_kick", "vblank";
> > +interrupt-parent = <>;
> > +clocks = < 248>, < 247>, < 249>,
> > + < 254>,< 122>;
> > +clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
> > +assigned-clocks = < 107>, < 109>, < 266>;
> > +assigned-clock-parents = < 78>, < 78>, < 3>;
> > +assigned-clock-rates = <8>,
> > +   <4>;
> > +port@0 {
> > +dcss_out: endpoint {
> > +remote-endpoint = <_in>;
> > +};
> > +};
> > +};
> > +
> 
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Re: [PATCH v3 2/4] drm/imx: Add initial support for DCSS on iMX8MQ

[Laurentiu Palcu]

Hi Lucas,

Thanks for taking some time to look over this series.

On Mon, Feb 24, 2020 at 06:27:25PM +0100, Lucas Stach wrote:
> Hi Laurentiu,
> 
> just a first drive-by comment, more in-depth review tomorrow.
> 
> On Fr, 2019-12-06 at 11:52 +0200, Laurentiu Palcu wrote:
> > This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
> > Some of its capabilities include:
> >  * 4K@60fps;
> >  * HDR10;
> >  * one graphics and 2 video pipelines;
> >  * on-the-fly decompression of compressed video and graphics;
> > 
> > The reference manual can be found here:
> > https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM
> > 
> > The current patch adds only basic functionality: one primary plane for
> > graphics, linear, tiled and super-tiled buffers support (no graphics
> > decompression yet), no HDR10 and no video planes.
> > 
> > Video planes support and HDR10 will be added in subsequent patches once
> > per-plane de-gamma/CSC/gamma support is in.
> > 
> > Signed-off-by: Laurentiu Palcu 
> > ---
> [...]
> > diff --git a/drivers/gpu/drm/imx/dcss/Kconfig 
> > b/drivers/gpu/drm/imx/dcss/Kconfig
> > new file mode 100644
> > index ..a189dac
> > --- /dev/null
> > +++ b/drivers/gpu/drm/imx/dcss/Kconfig
> > @@ -0,0 +1,8 @@
> > +config DRM_IMX_DCSS
> > +   tristate "i.MX8MQ DCSS"
> > +   select RESET_CONTROLLER
> > +   select IMX_IRQSTEER
> 
> This driver has no build time dependency on the IRQSTEER driver. It
> needs it at runtime, but those dependencies are normally not described
> in Kconfig.
> 
> On the other hand this is missing a "select DRM_KMS_CMA_HELPER".

Oops, I guess I missed this. I'll add it in next revision. Waiting for
your in-depth review first.

Thanks,
laurentiu

> 
> Regards,
> Lucas
> 
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[PATCH v3 0/4] Add support for iMX8MQ Display Controller Subsystem

[Laurentiu Palcu]

Hi,

This patchset adds initial DCSS support for iMX8MQ chip. Initial support
includes only graphics plane support (no video planes), no HDR10 capabilities,
no graphics decompression (only linear, tiled and super-tiled buffers allowed).

Support for the rest of the features will be added incrementally, in subsequent
patches.

The patchset was tested with both HDP driver (not yet upstreamed) and MIPI-DSI
(drivers already on the dri-devel ML).

Thanks,
Laurentiu

Changes in v3:
 * rebased to latest linux-next and made it compile as drmP.h was
   removed;
 * removed the patch adding the VIDEO2_PLL clock. It's already applied;
 * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set();
 * fixed a a spurious hang reported by Lukas Hartmann and encountered
   by me several times;
 * mask DPR and DTG interrupts by default, as they may come enabled from
   U-boot;

Changes in v2:
 * Removed '0x' in node's unit-address both in DT and yaml;
 * Made the address region size lowercase, to be consistent;
 * Removed some left-over references to P010;
 * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence 
compilation
   issues reported by kbuild for other architectures;


Laurentiu Palcu (4):
  drm/imx: compile imx directory by default
  drm/imx: Add initial support for DCSS on iMX8MQ
  dt-bindings: display: imx: add bindings for DCSS
  arm64: dts: imx8mq: add DCSS node

 .../bindings/display/imx/nxp,imx8mq-dcss.yaml  |  86 +++
 arch/arm64/boot/dts/freescale/imx8mq.dtsi  |  25 +
 drivers/gpu/drm/Makefile   |   2 +-
 drivers/gpu/drm/imx/Kconfig|   2 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dcss/Kconfig   |   8 +
 drivers/gpu/drm/imx/dcss/Makefile  |   6 +
 drivers/gpu/drm/imx/dcss/dcss-blkctl.c |  75 ++
 drivers/gpu/drm/imx/dcss/dcss-crtc.c   | 224 ++
 drivers/gpu/drm/imx/dcss/dcss-ctxld.c  | 447 +++
 drivers/gpu/drm/imx/dcss/dcss-dev.c| 286 +++
 drivers/gpu/drm/imx/dcss/dcss-dev.h| 195 +
 drivers/gpu/drm/imx/dcss/dcss-dpr.c| 550 ++
 drivers/gpu/drm/imx/dcss/dcss-drv.c| 181 +
 drivers/gpu/drm/imx/dcss/dcss-dtg.c| 442 +++
 drivers/gpu/drm/imx/dcss/dcss-kms.c| 322 
 drivers/gpu/drm/imx/dcss/dcss-kms.h|  52 ++
 drivers/gpu/drm/imx/dcss/dcss-plane.c  | 418 +++
 drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 +
 drivers/gpu/drm/imx/dcss/dcss-ss.c | 179 +
 20 files changed, 4326 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
 create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcss/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c
 create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c

-- 
2.7.4

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[PATCH v3 3/4] dt-bindings: display: imx: add bindings for DCSS

[Laurentiu Palcu]

Add bindings for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu 
Reviewed-by: Rob Herring 
---
 .../bindings/display/imx/nxp,imx8mq-dcss.yaml  | 86 ++
 1 file changed, 86 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 
b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
new file mode 100644
index ..efd2494
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: iMX8MQ Display Controller Subsystem (DCSS)
+
+maintainers:
+  - Laurentiu Palcu 
+
+description:
+
+  The DCSS (display controller sub system) is used to source up to three
+  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
+  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
+  image processing capabilities are included to provide a solution capable of
+  driving next generation high dynamic range displays.
+
+properties:
+  compatible:
+const: nxp,imx8mq-dcss
+
+  reg:
+maxItems: 2
+
+  interrupts:
+maxItems: 3
+items:
+  - description: Context loader completion and error interrupt
+  - description: DTG interrupt used to signal context loader trigger time
+  - description: DTG interrupt for Vblank
+
+  interrupt-names:
+maxItems: 3
+items:
+  - const: ctx_ld
+  - const: ctxld_kick
+  - const: vblank
+
+  clocks:
+maxItems: 5
+items:
+  - description: Display APB clock for all peripheral PIO access interfaces
+  - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
+  - description: RTRAM clock
+  - description: Pixel clock, can be driver either by HDMI phy clock or 
MIPI
+  - description: DTRC clock, needed by video decompressor
+
+  clock-names:
+items:
+  - const: apb
+  - const: axi
+  - const: rtrm
+  - const: pix
+  - const: dtrc
+
+  port@0:
+type: object
+description: A port node pointing to a hdmi_in or mipi_in port node.
+
+examples:
+  - |
+dcss: display-controller@32e0 {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "nxp,imx8mq-dcss";
+reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+interrupts = <6>, <8>, <9>;
+interrupt-names = "ctx_ld", "ctxld_kick", "vblank";
+interrupt-parent = <>;
+clocks = < 248>, < 247>, < 249>,
+ < 254>,< 122>;
+clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+assigned-clocks = < 107>, < 109>, < 266>;
+assigned-clock-parents = < 78>, < 78>, < 3>;
+assigned-clock-rates = <8>,
+   <4>;
+port@0 {
+dcss_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
-- 
2.7.4

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[PATCH v3 1/4] drm/imx: compile imx directory by default

[Laurentiu Palcu]

Currently the drm/imx/ directory is compiled only if DRM_IMX is set. Adding a
new IMX related IP in the same directory would need DRM_IMX to be set, which 
would
bring in also IPUv3 core driver...

The current patch would allow adding new IPs in the imx/ directory without 
needing
to set DRM_IMX.

Signed-off-by: Laurentiu Palcu 
---
 drivers/gpu/drm/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 9f1c7c4..69155f9 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -100,7 +100,7 @@ obj-$(CONFIG_DRM_MSM) += msm/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-$(CONFIG_DRM_STM) += stm/
 obj-$(CONFIG_DRM_STI) += sti/
-obj-$(CONFIG_DRM_IMX) += imx/
+obj-y  += imx/
 obj-$(CONFIG_DRM_INGENIC) += ingenic/
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
 obj-$(CONFIG_DRM_MESON)+= meson/
-- 
2.7.4

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