3D render image on WC AGP aperture BO and then CPU fetch the image from this
bo, in order to achieve performance, after 3D finished rendering, validate
this bo into cached system memory and then read it from system memory. But I
always get garbage from there.
After check TTM bo validate codes, it
Hi all,
Some DRM ioctls like this: DRM_IOCTL_DEF(DRM_IOCTL_ADD_CTX, drm_addctx,
DRM_AUTH|DRM_ROOT_ONLY),
it means that the drm_addctx must be called with both DRM_auth and root
priviledge. And I have a dount that the DRM_ROOT_ONLY is the superset of
DRM_AUTH according to the code below:
will be appreciated
2009/12/16 Jerome Glisse gli...@freedesktop.org
On Wed, Dec 16, 2009 at 12:12:13AM +0800, Donnie Fang wrote:
Hi Thomas,
I conclude your meaning as below:
a. When CPU join in, it must wait for the sync object to really free the
device address space.
b. When CPU
Hi Thomas,
I have several doubts. please check them as below.
2009/12/15 Thomas Hellstrom tho...@shipmail.org
Jerome Glisse wrote:
Hi Thomas,
Dave find out the root of a strange oops we did encouter.
I spend sometimes today trying to hack ttm around but
in the end my solution is
...@freedesktop.org
On Tue, Dec 15, 2009 at 02:04:01PM +0800, Donnie Fang wrote:
Hi Jerome,
The field busy_placement in struct ttm_placement hasn't been used
yet. what is this field exact usage? Do you mean TTM core can reference
this
field when do bo evict? But i can't find out any clue about
engine is totally independent from each other, so
sync object still needs to be signaled in this situation.
2009/12/15 Thomas Hellström tho...@shipmail.org
Donnie Fang wrote:
Hi Thomas,
I have several doubts. please check them as below.
2009/12/15 Thomas Hellstrom tho...@shipmail.org
dri-devel@lists.sourceforge.netHi all,
after reviewed the radeon fence scheme, there are lots of chances that
it needs create a new fence object, and also there are lots of chances need
to destroy these fence objects.
In my opinion, is it possible to maintain a list for recording some
the same role in terms of pool. Got it.
thanks.
Donnie.
2009/11/19 Jerome Glisse gli...@freedesktop.org
On Thu, 2009-11-19 at 16:29 +0800, Donnie Fang wrote:
Hi all,
after reviewed the radeon fence scheme, there are lots of chances
that it needs create a new fence object, and also
After review TTM code, i found that when BO is in AGP aperture, the cache
attribute for this BO is often to be WC.
So user mode page table will be WC of course. This guarantee that data
won't be cached by CPU and be visible to GPU correctly.
But how about the opposition in this case? How to
Sorry for omitting thomas.
-- Forwarded message --
From: Donnie Fang donnie.f...@gmail.com
Date: 2009/11/2
Subject: how to make sure cache synchronization between GPU and CPU
To: dri-devel@lists.sourceforge.net
After review TTM code, i found that when BO is in AGP aperture
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