Hi Dave,
A few fixes for v5.0.. the opp-level fix and removal of hard-coded irq
name is partially to make things smoother in v5.1 merge window to
avoid dependency on drm vs dt trees, but are otherwise sane changes.
The following changes since commit ba0ede185ef4c74bfecfe1c992be5dbcc5c5ac04:
On Fri, Jan 25, 2019 at 3:26 AM Colin Ian King wrote:
>
> ping?
I've pushed this, and the others you pinged about, to my tree.
Thank you,
Ben.
>
> On 04/09/2018 16:23, Colin King wrote:
> > From: Colin Ian King
> >
> > Don't populate the array vsoff on the stack but instead make it
> > static.
https://bugs.freedesktop.org/show_bug.cgi?id=107978
Alex Deucher changed:
What|Removed |Added
Attachment #143225|application/mbox|text/plain
mime type|
Allwinner MIPI DSI drq has enable mode and set bits.
- for burst mode, drq need to set enable mode bit.
- for non-burst video modes, drq need to set enable mode,
set bits for those front proch greater than 20 and for
rest drq is not used.
This patch simplifies existing drq code by grouping
Burst mode display timings are different from conventional
video mode, for burst mode most of the timings hsa, hbp, hfp,
vblk are 0 and hblk is computed as (mode->hdisplay * Bpp)
This patch add burst mode timings and directly goto alloc buffer.
Reference code taken from BSP (from linux-sunxi/
Instruction loop selection would require before writing
loop number registers, so enable idle, LP11 bits on
loop selection register.
Reference code available in BSP (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
(dsi_dev[sel]->dsi_inst_loop_sel.dwval =
Here is next version changes for Allwinner A64 MIPI-DSI support
This series grouped the changes from previous version A64 MIPI-DSI[1]
along with burst mode[2].
Though the series seems to have more patches, but all patches are ordered
in a way that the review process is as smooth as possible.
Loop N1 instruction delay varies between burst and non-burst
video modes. for burst mode panels it is computed based on the
panel clock along with horizontal sync and porch timings and
the rest it is simply (50 - 1)
Reference code is available in BSP (from linux-sunxi
Some NKM PLLs doesn't work well when their output clock rate is set below
certain rate.
So, add support for minimal rate for relevant PLLs.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 5 +
drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
2 files changed, 6
Most of the Allwinner MIPI DSI controllers are supply with
VCC-DSI pin. which need to supply for some of the boards to
trigger the power.
So, document the supply property so-that the required board
can eable it via device tree.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Sometimes tcon attributes like tcon divider, clock rate etc are needed
in interface drivers like DSI. So for such cases interface driver must
probe the respective tcon and get the attributes.
Since tcon0 probe is already available, via sun4i_get_tcon0 function,
export the same instead of probing
On Thu, Jan 24, 2019 at 09:17:49PM +0100, Sam Ravnborg wrote:
> Hi Sean.
>
> > >
> > > Merge the previous 5 patches from this series, but this now goes boom on
> > > vbox in staging. Needs another prep patch I think.
> >
> > Soo, can we drop vboxvideo yet?
>
> Hans de Goede sent out patches in
On Thu, Jan 24, 2019 at 03:03:20PM +0100, Daniel Vetter wrote:
> On Sat, Jan 19, 2019 at 09:40:14AM +0100, Sam Ravnborg wrote:
> > With the removal of drmP.h from drm_modeset_helper.h
> > the drmP.h are no longer included by any include files
> > in include/drm.
> > The drmP.h file is thus only
https://bugs.freedesktop.org/show_bug.cgi?id=107978
--- Comment #45 from Jerry Zuo ---
Please try the patch and see if that fixes your issue. We will come up with
proper solution later.
--
You are receiving this mail because:
You are the assignee for the
Hi Jagan.
Thanks for being persistent and keep follow-up on this driver.
On Thu, Jan 24, 2019 at 11:58:44PM +0530, Jagan Teki wrote:
> ST7701 designed for small and medium sizes of TFT LCD display, is
> capable of supporting up to 480RGBX864 in resolution. It provides
> several system interfaces
Hi Jagan.
Thanks for this nice patch, a few comments below.
On Fri, Jan 25, 2019 at 12:13:13AM +0530, Jagan Teki wrote:
> Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
>
> Add panel driver for it.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v5:
> - rebase on master
>
Hi Sean.
> >
> > Merge the previous 5 patches from this series, but this now goes boom on
> > vbox in staging. Needs another prep patch I think.
>
> Soo, can we drop vboxvideo yet?
Hans de Goede sent out patches in September to convert it to a proper
atomic driver.
I recall that the feedback
Hi Sean/Hans.
> > Hans de Goede sent out patches in September to convert it to a proper
> > atomic driver.
> > I recall that the feedback was mostly positive and that there was only
> > minor things to left to do. Hans?
I browsed the archieves and I could not find anything that was not
https://bugs.freedesktop.org/show_bug.cgi?id=109445
--- Comment #4 from Bas Nieuwenhuizen ---
since you mentioned your system does not respond to ping or ssh I wonder if it
is actually not a gpu problem, but more generally being under load.
maybe try idle=nomwait? That solved regular lockup
https://bugs.freedesktop.org/show_bug.cgi?id=109445
--- Comment #5 from Bas Nieuwenhuizen ---
to clarify, try idle=nomwait on the kernel commandline.
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ST7701 designed for small and medium sizes of TFT LCD display, is
capable of supporting up to 480RGBX864 in resolution. It provides
several system interfaces like MIPI/RGB/SPI.
Currently added support for Techstar TS8550B which is ST7701 based
480x854, 2-lane MIPI DSI LCD panel.
Driver now
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI LCD panel
with inbuilt ST7701 chip.
The default regulator names in ST7701 chip is renamed in Techstar TS8550B
so, add specific binding names for them.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Changes for v8, v9:
- none
Hi Linus,
Live from LCA pull, some fixes all over the place,
i915:
- GVT workload destruction fix
msm:
- A6XX opp-level fix, build fixes, hard-coded irq removal
amdgpu:
- overclocking fix
- hybrid gfx fix
sun4i:
- fix TMDS clock usage
Dave.
drm-fixes-2019-01-25-1:
drm fixes. msm, sun4i,
Probe tcon0 during dsi_bind, so-that the tcon attributes like
divider value, clock rate can get whenever it need.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 +++
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 1 +
2 files changed, 8 insertions(+)
diff --git
Some boards have VCC-DSI pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
MIPI DSI driver.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 14 ++
For 4-lane, burst mode panels would need to enable 2byte trail_fill
along with filling trail_env in dsi base control register.
Similar reference code avialable in BSP (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
if (panel->lcd_dsi_lane == 4)
{
Minimum PLL used for MIPI is 500MHz, as per manual, but
lowering the min rate by 300MHz can result proper working
nkms divider with the help of desired dclock rate from
panel driver.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 +
1 file
Setting up burst mode display would require to compute
- Horizontal timing edge values to fill burst drq register
- Line, sync values to fill burst line register
Since there is no direct documentation for these computations
the edge and line formulas are taken from BSP code (from linux-sunxi/
Horizontal back porch, sync active and sync end bits are
needed to disable for burst mode panel operations.
So, disable them via dsi base control register.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff
Current driver is calculating hbp maximum value by subtracting
hsync_start with hdisplay which is front porch value, but the
hbp refers to back porch.
Back porch value is calculating by subtracting htotal with
hsync_end as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually
This patch add support for Bananapi S070WV20-CT16 DSI panel to
BPI-M64 board.
DSI panel connected via board DSI port with,
- DLDO1 as VDD supply
- PD6 gpio for reset pin
- PD5 gpio for backlight enable pin
- PD7 gpio for backlight vdd supply
Signed-off-by: Jagan Teki
---
The MIPI DSI PHY controller on Allwinner A64 is similar
on the one on A31.
Add A64 compatible and append A31 compatible as fallback.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff
Current driver is calculating hfp maximum value by subtracting
htotal with hsync_end which is front back value, but the
hpp refers to front porch.
Front porch value is calculating by subtracting hsync_start with
hdisplay as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually
Amarula A64-Relic board by default bound with Techstar TS8550B
MIPI-DSI panel, add support for it.
DSI panel connected via board DSI port with,
- DLDO2 as VCC supply
- DLDO2 as IOVCC supply
- DLDO1 as VCC-DSI supply
- PD24 gpio for reset pin
- PD23 gpio for backlight enable pin
Signed-off-by:
Short transfer write support for DCS and Generic transfer types
share similar way to process command sequence in DSI block so
add generic write 2 param transfer type macro so-that the panels
which are requesting similar transfer type may process properly.
Signed-off-by: Jagan Teki
---
The MIPI DSI controller in Allwinner A64 is similar to A33.
But unlike A33, A64 doesn't have DSI_SCLK gating which eventually
set the mod clock rate for the controller.
So, use the DSI_DPHY gating for the similar purpose of mod clock
so-that the controller can operate properly.
Signed-off-by:
The A64 has a MIPI-DSI block which is similar to A31.
Add dsi, dphy nodes with A31 fallback compatible and finally
connect the dsi node to tcon0 node to make proper DSI pipeline.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 47 +++
1 file
Feiyang FY07024DI26A30-D MIPI_DSI panel is desiged to attach with
DSI connector on pine64 boards, enable the same for pine64 LTS.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DLDO2 as DVDD supply
- DLDO1 as VCC-DSI supply
- PD24 gpio for reset pin
- PH10 gpio for
Hi,
I tested your patch with kms_cursor_crc, and everything worked as
expected! Really nice patch :)
I just have some tiny comments inline.
On 01/24, Mamta Shukla wrote:
> Use the alpha value to blend vaddr_src with vaddr_dst instead
> of overwriting it in blend().
>
> Signed-off-by: Mamta
The pull request you sent on Fri, 25 Jan 2019 07:54:37 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2019-01-25-1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/d73aba1115cf40630cc8b4b7aed049ed8117b458
Thank you!
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https://bugs.freedesktop.org/show_bug.cgi?id=105733
--- Comment #61 from Zheng Luo ---
I experienced similar problems, but mine is much worse. I can't recover from
black screen after reboot/hard reset unless I drain the builtin battery.
However this problem disappears in 5.0rc3 (in contrast to
https://bugs.freedesktop.org/show_bug.cgi?id=109445
Mike Mestnik changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On Thu, Jan 24, 2019 at 04:52:59PM -0800, ndesaulni...@google.com wrote:
> arch/x86/Makefile disables SSE and SSE2 for the whole kernel. The
> AMDGPU drivers modified in this patch re-enable SSE but not SSE2. Turn
> on SSE2 to support emitting double precision floating point instructions
>
The display pipeline has the same structure, resources and connections
on both the A23 and A33. The differences include:
- compatible strings
- extra clock, reset control, and IO region for SAT in the backend
only found on the A33
- missing ch1 clock for the TCON
However, while the A23
Hi everyone,
This series enables the display pipeline on the Allwinner A23 SoC.
A few fixes are included for corner cases when the frontend isn't
enabled.
The A23 display pipeline is very much the same as the A33, except
that the A23 does not have the SAT IP block embedded within the
display
In some cases, such as running a new kernel with an old device tree that
has the frontend disabled, the backend's matching frontend might be
unavailable.
When this happens, the layers should only declare support for formats
that the backend support. This partially reverts commit 1c29d263f624
The NAND controller device node was inserted into the wrong position,
probably due to a rebase or merge, as the file's structure does not
provide enough context for git to accurately match the previous device
node block.
Fixes: d7b843df13ea ("ARM: dts: sun8i: add NAND controller node for
On Thu, Jan 24, 2019 at 05:58:24PM +0100, Daniel Vetter wrote:
> This should not result in any changes.
I'd love to merge https://patchwork.freedesktop.org/series/53951/
instead (which will -- among other things -- switch qxl over to the
generic fbdev emulation and remove the code you are
https://bugs.freedesktop.org/show_bug.cgi?id=107978
--- Comment #46 from Shmerl ---
(In reply to Jerry Zuo from comment #45)
> Please try the patch and see if that fixes your issue. We will come up with
> proper solution later.
I tested the patch, and it didn't fix the issue for me.
--
You
Hi,
On Fri, 25 Jan 2019 01:21:26 + "Li, Weinan Z" wrote:
>
> I am not sure about the problem. The commit id "0cce2823ed37" is just
> for the patch of "drm/i915/gvt: Refine error handling for
> prepare_execlist_workload". Is there any other problems I missed?
Its just that the subject line
Thank Stephen.
I am not sure about the problem. The commit id "0cce2823ed37" is just for the
patch of "drm/i915/gvt: Refine error handling for prepare_execlist_workload".
Is there any other problems I missed?
Regards.
-Weinan
> -Original Message-
> From: Jani Nikula
The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.
Add the 2 LDO enable bits to the gate bits.
Fixes: 5690879d93e8 ("clk: sunxi-ng: Add A23 CCU")
Signed-off-by: Chen-Yu Tsai
---
The A23's display pipeline is similar to the A33. Differences include:
- Display backend supports larger layers, 8192x8192 instead of 2048x2048
- TCON has DMA input
- There is no SAT module packed in the display backend
Add compatible strings for the display pipeline and its components.
Now that the compatible strings for the display pipeline on the A23 have
been added to the bindings, add the corresponding compatibles to the
device nodes already in the A23/A33 shared dtsi.
While the A23 has the TCON ch1 clock defined in the CCU, and the channel
1 registers are available, it
The A23's display pipeline is similar to the A33. Differences include:
- Display backend supports larger layers, 8192x8192 instead of 2048x2048
- TCON has DMA input
- There is no SAT module packed in the display backend
Add support for the display pipeline and its components.
As the
We might want to use the backend pointer from DRM callbacks that get
called within drm_universal_plane_init(), such as the
.format_mod_supported callback.
Move the assignment of the layer's backend pointer to right after the
structure is allocated.
Signed-off-by: Chen-Yu Tsai
---
The display backend does not support BGRX. There is also no trace
of this in the original list of supported formats before the commit
b636d3f97d04 ("drm/sun4i: frontend: Add support for the BGRX input
format"). Nor do the backend configuration helpers handle this format.
Remove BGRX
The Q8 design for A23/A33 tablets have an 18-bit RGB LCD panel connected
to the LCD interface on the SoC, the DC1SW output on the PMIC providing
power for the LCD, and PH7 toggling the reset pin for the panel.
This patch adds a device node for the panel, describing the above, and
enables the
The Q8 tablets follow the A23/A33 tablet reference design, and normally
use a "generic" 800x480 LCD panel. The actual panel may vary between
production runs, and there are no visible markings denoting its model.
This patch uses a panel that has the same dimensions and timings that
are close to
On Thu, Jan 24, 2019 at 07:55:51AM +1300, Kees Cook wrote:
> On Thu, Jan 24, 2019 at 4:44 AM Jani Nikula
> wrote:
> >
> > On Wed, 23 Jan 2019, Edwin Zimmerman wrote:
> > > On Wed, 23 Jan 2019, Jani Nikula wrote:
> > >> On Wed, 23 Jan 2019, Greg KH wrote:
> > >> > On Wed, Jan 23, 2019 at
On Tue, Jan 22, 2019 at 03:25:47PM +, Biju Das wrote:
> The LVDS encoders on RZ/G1N SoC is similar to RZ/G1M. Add support for
> RZ/G1N (R8A7744) SoC to the LVDS encoder driver.
>
> Signed-off-by: Biju Das
Reviewed-by: Simon Horman
> ---
> drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 +
> 1
23.01.2019 12:39, Thierry Reding пишет:
> From: Thierry Reding
>
> Loading the firmware requires an allocation of IOVA space to make sure
> that the VIC's Falcon microcontroller can read the firmware if address
> translation via the SMMU is enabled.
>
> However, the allocation currently happens
This attempts to duplicate the proposed gcc option -finit-local-vars[1]
in an effort to implement the "always initialize local variables" kernel
development goal[2].
Enabling CONFIG_GCC_PLUGIN_STACKINIT should stop all "uninitialized
stack variable" flaws as long as they don't depend on being
On Wed, 23 Jan 2019 at 13:09, Jann Horn wrote:
>
> On Wed, Jan 23, 2019 at 1:04 PM Greg KH wrote:
> > On Wed, Jan 23, 2019 at 03:03:47AM -0800, Kees Cook wrote:
> > > Variables declared in a switch statement before any case statements
> > > cannot be initialized, so move all instances out of the
On Wed, 23 Jan 2019, Jani Nikula wrote:
> On Wed, 23 Jan 2019, Greg KH wrote:
> > On Wed, Jan 23, 2019 at 03:03:47AM -0800, Kees Cook wrote:
> >> Variables declared in a switch statement before any case statements
> >> cannot be initialized, so move all instances out of the switches.
> >> After
On Wed, Jan 23, 2019 at 1:04 PM Greg KH wrote:
> On Wed, Jan 23, 2019 at 03:03:47AM -0800, Kees Cook wrote:
> > Variables declared in a switch statement before any case statements
> > cannot be initialized, so move all instances out of the switches.
> > After this, future always-initialized stack
This adds a new plugin "stackinit" that attempts to perform unconditional
initialization of all stack variables[1]. It has wider effects than
GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y since BYREF_ALL does not consider
non-structures. A notable weakness is that padding bytes in many cases
remain
On Wed, Jan 23, 2019 at 05:23:15PM -0500, jgli...@redhat.com wrote:
> From: Jérôme Glisse
>
> When range of virtual address is updated read only and corresponding
> user ptr object are already read only it is pointless to do anything.
> Optimize this case out.
>
> Signed-off-by: Jérôme Glisse
On Wed, 23 Jan 2019 at 08:15, Christoph Hellwig wrote:
>
> On Tue, Jan 22, 2019 at 10:07:07PM +0100, Ard Biesheuvel wrote:
> > Yes, so much was clear. And the reason this breaks on some arm64
> > systems is because
> > a) non-snooped PCIe TLP attributes may be ignored, and
> > b) non-x86 CPUs do
Hi Dave/Daniel,
Just a small fix for sun4i in drm-misc-fixes. :)
drm-misc-fixes-2019-01-24:
drm-misc-fixes for v5.0-rc4:
- Small refcounting fix to sun4i's HDMI support.
The following changes since commit 49a57857aeea06ca831043acbb0fa5e0f50602fd:
Linux 5.0-rc3 (2019-01-21 13:14:44 +1300)
https://bugs.freedesktop.org/show_bug.cgi?id=109444
Michel Dänzer changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=109445
--- Comment #3 from Michel Dänzer ---
*** Bug 109444 has been marked as a duplicate of this bug. ***
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You are the assignee for the bug.___
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On Wed, Jan 23, 2019 at 06:00:15PM +0100, Sam Ravnborg wrote:
> Hi Daniel.
>
> On Thu, Jan 17, 2019 at 10:03:34PM +0100, Daniel Vetter wrote:
> > Having the probe helper stuff (which pretty much everyone needs) in
> > the drm_crtc_helper.h file (which atomic drivers should never need) is
> >
On Wed, Jan 23, 2019 at 11:21:25PM -0800, Life is hard, and then you die wrote:
> Since the two changes (the change here + the new driver) seem to be
> best submitted through different trees, I'm trying to figure out how
> best to handle this. I suppose I could temporarily change the driver
>
On 2019-01-23 5:52 p.m., Ard Biesheuvel wrote:
> On Wed, 23 Jan 2019 at 17:44, Christoph Hellwig wrote:
>>
>> I think we just want a driver-local check for those combinations
>> where we know this hack actually works, which really just seems
>> to be x86-64 with PAT. Something like the patch
Am 24.01.19 um 10:28 schrieb Ard Biesheuvel:
> On Thu, 24 Jan 2019 at 10:25, Koenig, Christian
> wrote:
>> Am 24.01.19 um 10:13 schrieb Christoph Hellwig:
>>> On Wed, Jan 23, 2019 at 05:52:50PM +0100, Ard Biesheuvel wrote:
But my concern is that it seems likely that non-cache coherent
23.01.2019 18:55, Dmitry Osipenko пишет:
> 23.01.2019 17:04, Thierry Reding пишет:
>> On Wed, Jan 23, 2019 at 04:41:44PM +0300, Dmitry Osipenko wrote:
>>> 23.01.2019 12:39, Thierry Reding пишет:
From: Thierry Reding
On Tegra186 and later, the ARM SMMU provides an input address
On Tue, Jan 22, 2019 at 05:44:28PM +0200, Laurent Pinchart wrote:
> Hi Biju,
>
> Thank you for the patch.
>
> On Tue, Jan 22, 2019 at 03:25:46PM +, Biju Das wrote:
> > Document the RZ/G1N (R8A7744) LVDS bindings.
> >
> > Signed-off-by: Biju Das
>
> Reviewed-by: Laurent Pinchart
>
> and
Variables declared in a switch statement before any case statements
cannot be initialized, so move all instances out of the switches.
After this, future always-initialized stack variables will work
and not throw warnings like this:
fs/fcntl.c: In function ‘send_sigio_to_task’:
fs/fcntl.c:738:13:
On Thu, Dec 20, 2018 at 10:29 PM Jayant Shekhar wrote:
>
> Add interconnect properties such as the source and the destination
> ports for MDSS on SDM845.
>
> Signed-off-by: Jayant Shekhar
Reviewed-by: Evan Green
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dri-devel mailing list
Hi Laurent,
On Thu, Jan 24, 2019 at 12:17:35AM +0200, Laurent Pinchart wrote:
> Hello Dmity,
>
> On Wed, Jan 23, 2019 at 02:03:42PM -0800, Dmitry Torokhov wrote:
> > On Wed, Jan 23, 2019 at 09:45:56AM +0100, Lukas Wunner wrote:
> > > On Tue, Jan 22, 2019 at 06:13:11AM -0800, Ronald Tschalär
On Tue, Jan 22, 2019 at 07:07:51PM +0200, Laurent Pinchart wrote:
> Hi Biju,
>
> Thank you for the patch.
>
> On Tue, Jan 22, 2019 at 03:25:48PM +, Biju Das wrote:
> > Add du node to r8a7744 SoC DT. Boards that want to enable the DU
> > need to specify the output topology.
> >
> >
Hi Laurent,
On Tue, Jan 22, 2019 at 11:10:28PM +0200, Laurent Pinchart wrote:
>
> Thank you for the patch.
>
> On Tue, Jan 22, 2019 at 06:13:11AM -0800, Ronald Tschalär wrote:
> > commit d6abe6df706c66d803e6dd4fe98c1b6b7f125a56 (drm/bridge:
>
> Commits are usually quoted using the short 12
On Thu, Jan 24, 2019 at 8:18 AM Matthew Wilcox wrote:
>
> On Wed, Jan 23, 2019 at 04:17:30PM +0200, Jani Nikula wrote:
> > Can't have:
> >
> > switch (i) {
> > int j;
> > case 0:
> > /* ... */
> > }
> >
> > because it can't be turned into:
> >
> >
23.01.2019 17:04, Thierry Reding пишет:
> On Wed, Jan 23, 2019 at 04:41:44PM +0300, Dmitry Osipenko wrote:
>> 23.01.2019 12:39, Thierry Reding пишет:
>>> From: Thierry Reding
>>>
>>> On Tegra186 and later, the ARM SMMU provides an input address space that
>>> is 48 bits wide. However, memory
Hi Laurent,
On Wed, Jan 23, 2019 at 11:55:52AM +0200, Laurent Pinchart wrote:
> Hi Simon,
>
> On Wed, Jan 23, 2019 at 09:56:57AM +0100, Simon Horman wrote:
> > On Wed, Jan 23, 2019 at 12:54:04AM +0200, Laurent Pinchart wrote:
> > > The LVDS1 encoder must supply a pixel clock to the DU for the
On Wed, Jan 23, 2019 at 09:45:56AM +0100, Lukas Wunner wrote:
> On Tue, Jan 22, 2019 at 06:13:11AM -0800, Ronald Tschalär wrote:
> > commit d6abe6df706c66d803e6dd4fe98c1b6b7f125a56 (drm/bridge:
> > sil_sii8620: do not have a dependency of RC_CORE) added a dependency on
> > INPUT. However, this
23.01.2019 12:39, Thierry Reding пишет:
> From: Thierry Reding
>
> Move initialization of the shared IOMMU domain after the host1x device
> has been initialized. At this point all the Tegra DRM clients have been
> attached to the shared IOMMU domain.
>
> This is important because Tegra186 and
23.01.2019 17:04, Thierry Reding пишет:
> On Wed, Jan 23, 2019 at 04:41:44PM +0300, Dmitry Osipenko wrote:
>> 23.01.2019 12:39, Thierry Reding пишет:
>>> From: Thierry Reding
>>>
>>> On Tegra186 and later, the ARM SMMU provides an input address space that
>>> is 48 bits wide. However, memory
On Wed, 23 Jan 2019 at 17:44, Christoph Hellwig wrote:
>
> I think we just want a driver-local check for those combinations
> where we know this hack actually works, which really just seems
> to be x86-64 with PAT. Something like the patch below, but maybe with
> even more strong warnings to not
> On Jan 23, 2019, at 5:09 AM, Jann Horn wrote:
>
> AFAICS this only applies to switch statements (because they jump to a
> case and don't execute stuff at the start of the block), not blocks
> after if/while/... .
It bothers me that we are going out of our way to deprecate valid C constructs
Use the alpha value to blend vaddr_src with vaddr_dst instead
of overwriting it in blend().
Signed-off-by: Mamta Shukla
---
drivers/gpu/drm/vkms/vkms_crc.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vkms/vkms_crc.c
On Wed, Jan 23, 2019 at 12:54:04AM +0200, Laurent Pinchart wrote:
> The LVDS1 encoder must supply a pixel clock to the DU for the DPAD
> output when the LVDS0 encoder is used. Enable it despite its output not
> being connected.
>
> Signed-off-by: Laurent Pinchart
> ---
> Changes since v1:
>
> -
23.01.2019 12:39, Thierry Reding пишет:
> From: Thierry Reding
>
> Loading the firmware requires an allocation of IOVA space to make sure
> that the VIC's Falcon microcontroller can read the firmware if address
> translation via the SMMU is enabled.
>
> However, the allocation currently happens
Adds test for stack initialization coverage. We have several build options
that control the level of stack variable initialization. This test lets us
visualize which options cover which cases, and provide tests for options
that are currently not available (padding initialization).
All options
23.01.2019 12:39, Thierry Reding пишет:
> From: Thierry Reding
>
> Tegra DRM clients need access to their parent, so store a pointer to it
> upon registration.
>
> Signed-off-by: Thierry Reding
> ---
> drivers/gpu/drm/tegra/drm.c | 2 ++
> drivers/gpu/drm/tegra/drm.h | 1 +
> 2 files changed,
23.01.2019 12:39, Thierry Reding пишет:
> From: Thierry Reding
>
> Move initialization of the shared IOMMU domain after the host1x device
> has been initialized. At this point all the Tegra DRM clients have been
> attached to the shared IOMMU domain.
>
> This is important because Tegra186 and
On Mon, Jan 21, 2019 at 1:36 AM Jani Nikula wrote:
>
> On Fri, 18 Jan 2019, "Kristian H. Kristensen" wrote:
> > Otherwise we get hard to track down "Purging: 123123 bytes" messages in
> > the log.
> >
> > Signed-off-by: Kristian H. Kristensen
> > ---
> > drivers/gpu/drm/msm/msm_gem_shrinker.c
On Thu, Jan 24, 2019 at 12:22:00AM +0200, Laurent Pinchart wrote:
>
> On Wed, Jan 23, 2019 at 02:21:05PM -0800, Dmitry Torokhov wrote:
> > On Thu, Jan 24, 2019 at 12:17:35AM +0200, Laurent Pinchart wrote:
> > > On Wed, Jan 23, 2019 at 02:03:42PM -0800, Dmitry Torokhov wrote:
> > >> On Wed, Jan
On Wed, Jan 23, 2019 at 04:17:30PM +0200, Jani Nikula wrote:
> Can't have:
>
> switch (i) {
> int j;
> case 0:
> /* ... */
> }
>
> because it can't be turned into:
>
> switch (i) {
> int j = 0; /* not valid C */
> case 0:
>
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