Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add gmc_bits for ovl private data
> GMC register was set RDMA ultra and pre-ultra threshold.
> 10bit GMC register define is different with other SOC, gmc_thrshd_l not
> used.
https://bugs.freedesktop.org/show_bug.cgi?id=109294
--- Comment #7 from Tvrtko Ursulin ---
Patch tested on CI: https://patchwork.freedesktop.org/series/59284/
Seems to have improved the coverage:
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2838/
* igt@prime_vgem@basic-fence-flip:
-
On 4/1/19 4:44 PM, Maxime Ripard wrote:
> Hi Nicolas,
>
> On Fri, Mar 22, 2019 at 03:55:19PM -0400, Nicolas Dufresne wrote:
>> Le mardi 19 mars 2019 à 22:57 +0100, Maxime Ripard a écrit :
>>> V4L2 uses different fourcc's than DRM, and has a different set of formats.
>>> For now, let's add the
https://bugs.freedesktop.org/show_bug.cgi?id=109345
--- Comment #10 from Allan Cairns ---
Created attachment 143935
--> https://bugs.freedesktop.org/attachment.cgi?id=143935=edit
AmigaOne DRM Issues
Third time lucky?
--
You are receiving this mail because:
You are the assignee for the
https://bugs.freedesktop.org/show_bug.cgi?id=109955
--- Comment #4 from Mauro Gaspari ---
Issue still happens despite kernel updates and mesa updates on openSUSE
Tumbleweed. Same happens on Kubuntu with oibaf ppa, and on Arch.
It seems this bug affects many people on linux using AMDGPUS, and
https://bugs.freedesktop.org/show_bug.cgi?id=102322
--- Comment #78 from Mauro Gaspari ---
Hi, I am affected by similar issues too using AMDGPU drivers on linux, and I
have opened another bug, before finding this.
You can have a look at my findings and the workarounds I am applying. So far I
had
On Wednesday, 2019-04-10 21:49:33 -0400, Rob Clark wrote:
> On Tue, Apr 9, 2019 at 8:27 AM Eric Engestrom
> wrote:
> > > > diff --git a/include/drm/msm_drm.h b/include/drm/msm_drm.h
> > > > index c06d0a5..91a16b3 100644
> > > > --- a/include/drm/msm_drm.h
> > > > +++ b/include/drm/msm_drm.h
> >
On Thu, Apr 11, 2019 at 01:25:39AM +0200, Clément Péron wrote:
> Add the mali gpu node to the H6 device-tree.
>
> Signed-off-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80
> 1 file changed, 80 insertions(+)
>
> diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=109345
--- Comment #11 from Allan Cairns ---
Alex
Hopefully these are what you are after. I was told to use less with
dmseg so not sure if that caused the problem.
Allan
--
You are receiving this mail because:
You are the assignee for the
On Thu, Apr 11, 2019 at 01:25:38AM +0200, Clément Péron wrote:
> This add the H6 mali compatible in the dt-bindings to later support
> specific implementation.
>
> Signed-off-by: Clément Péron
> ---
> .../devicetree/bindings/gpu/arm,mali-midgard.txt | 8 +++-
> 1 file changed, 7
On 4/11/19 9:12 AM, Hans Verkuil wrote:
> Hi Maxime,
>
> Some comments below...
>
> On 3/19/19 10:57 PM, Maxime Ripard wrote:
>> V4L2 uses different fourcc's than DRM, and has a different set of formats.
>> For now, let's add the v4l2 fourcc's for the already existing formats.
>>
>>
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add commponent OVL0_2L
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
>
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> the format of "mtk_ddp_sout_sel"was not flexible, after we add more
> mediatek SOC support, that will be redundant
It looks like this patch is part of patch 'add mmsys private data for
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add component DITHER
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32
> +
>
Hi Maxime,
Some comments below...
On 3/19/19 10:57 PM, Maxime Ripard wrote:
> V4L2 uses different fourcc's than DRM, and has a different set of formats.
> For now, let's add the v4l2 fourcc's for the already existing formats.
>
> Signed-off-by: Maxime Ripard
> ---
>
https://bugs.freedesktop.org/show_bug.cgi?id=102670
Arek Hiler changed:
What|Removed |Added
i915 platform|BXT, GLK, HSW, I915G, KBL, |ALL
|SKL, SNB
On Thu, Apr 11, 2019 at 12:57:14PM +0200, Clément Péron wrote:
> Some SoCs adds a bus clock gate to the Mali Midgard GPU.
>
> Add the binding for the bus clock.
>
> Signed-off-by: Icenowy Zheng
> Signed-off-by: Clément Péron
I'm not quite sure what you did there. If Icenowy is the author and
https://bugs.freedesktop.org/show_bug.cgi?id=110376
Martin Peres changed:
What|Removed |Added
Assignee|dri-devel@lists.freedesktop |elong...@gmail.com
Hi Dave,
The following changes since commit 509869a2fec36ecb2b841180915995f41d5a0219:
drm/tegra: vic: Fix implicit function declaration warning (2019-03-22
14:08:55 +0100)
are available in the Git repository at:
git://anongit.freedesktop.org/tegra/linux tags/drm/tegra/for-5.1-rc5
for you
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add layer_nr for ovl private data
> ovl_2l almost same with with ovl hardware, except the
> layer number for ovl_2l is 2 and ovl is 4.
> this patch is a preparation for
On 11.04.2019 10:23, Ben Dooks wrote:
> On 2019-04-10 23:47, Stefan Agner wrote:
>> In case the IOMMU API is not available compiling host1x fails with
>> the following error:
>> In file included from drivers/gpu/host1x/hw/host1x06.c:27:
>> drivers/gpu/host1x/hw/channel_hw.c: In function
>>
https://bugs.freedesktop.org/show_bug.cgi?id=110229
Andre Klapper changed:
What|Removed |Added
Status|REOPENED|NEEDINFO
--- Comment #27 from Andre
On 3/22/19 8:55 PM, Nicolas Dufresne wrote:
> Le mardi 19 mars 2019 à 22:57 +0100, Maxime Ripard a écrit :
>> V4L2 uses different fourcc's than DRM, and has a different set of formats.
>> For now, let's add the v4l2 fourcc's for the already existing formats.
>
> Hopefully I get the fixup right
From: Neil Armstrong
The Amlogic ARM Mali Midgard requires reset controls to power on and
software reset the GPU, adds these as optional in the bindings.
Signed-off-by: Neil Armstrong
Reviewed-by: Rob Herring
Signed-off-by: Kevin Hilman
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt
On (04/10/19 13:17), Alastair D'Silva wrote:
> With the wider display format, it can become hard to identify how many
> bytes into the line you are looking at.
>
> The patch adds new flags to hex_dump_to_buffer() and print_hex_dump() to
> print vertical lines to separate every N groups of bytes.
Hi,
The Allwinner H6 has a Mali-T720 MP2. The drivers are
out-of-tree so this serie only introduce the dt-bindings.
The first patch is from Neil Amstrong and has been already
merged in linux-amlogic. It is required for this serie.
The second patch is from Icenowy Zheng where I changed the
order
On Thu, Apr 11, 2019 at 09:56:15AM +0200, Clément Péron wrote:
> Hi,
>
> On Thu, 11 Apr 2019 at 09:28, Maxime Ripard wrote:
> >
> > On Thu, Apr 11, 2019 at 01:25:39AM +0200, Clément Péron wrote:
> > > Add the mali gpu node to the H6 device-tree.
> > >
> > > Signed-off-by: Clément Péron
> > > ---
https://bugs.freedesktop.org/show_bug.cgi?id=110229
Laurent changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Resolution|NOTOURBUG
https://bugs.freedesktop.org/show_bug.cgi?id=110376
--- Comment #2 from CI Bug Log ---
A CI Bug Log filter associated to this bug has been updated:
{- KBL: igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic - dmesg-warn
- *ERROR* Failed to enable hdcp (-110) -}
{+ all machines: all
Enable and add supply to the Mali GPU node on the
Pine H64 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
The locks (timeline->lock and rq->lock) need to be taken with disabled
interrupts. This is done in __retire_engine_request() by disabling the
interrupts independently of the locks itself.
While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla
it does not on RT. Also, it is not
Enable and add supply to the Mali GPU node on the
Orange Pi 3 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
Replace the indirection through struct stack_trace by using the storage
array based interfaces.
The original code in all printing functions is really wrong. It allocates a
storage array on stack which is unused because depot_fetch_stack() does not
store anything in it. It overwrites the entries
Hi,
On 10/04/2019 16:27, Thierry Reding wrote:
On Wed, Apr 10, 2019 at 03:23:27PM +0100, Ian Jackson wrote:
From: Wei Liu
Empirically, on stretch armhf:
drivers/gpu/host1x/cdma.c: In function `host1x_pushbuffer_init':
drivers/gpu/host1x/cdma.c:94:48: error: passing argument 3 of
Hi,
On Thu, 11 Apr 2019 at 09:28, Maxime Ripard wrote:
>
> On Thu, Apr 11, 2019 at 01:25:39AM +0200, Clément Péron wrote:
> > Add the mali gpu node to the H6 device-tree.
> >
> > Signed-off-by: Clément Péron
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80
> >
From: Wei Liu
Empirically, on stretch armhf:
drivers/gpu/host1x/cdma.c: In function `host1x_pushbuffer_init':
drivers/gpu/host1x/cdma.c:94:48: error: passing argument 3 of `dma_alloc_wc'
from incompatible pointer type [-Werror=incompatible-pointer-types]
pb->mapped =
Some SoCs adds a bus clock gate to the Mali Midgard GPU.
Add the binding for the bus clock.
Signed-off-by: Icenowy Zheng
Signed-off-by: Clément Péron
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git
No architecture terminates the stack trace with ULONG_MAX anymore. Remove
the cruft.
Signed-off-by: Thomas Gleixner
Cc: intel-...@lists.freedesktop.org
Cc: Joonas Lahtinen
Cc: Maarten Lankhorst
Cc: dri-devel@lists.freedesktop.org
Cc: David Airlie
Cc: Jani Nikula
Cc: Daniel Vetter
Cc:
From: Alastair D'Silva
> Sent: 10 April 2019 04:17
> With the wider display format, it can become hard to identify how many
> bytes into the line you are looking at.
>
> The patch adds new flags to hex_dump_to_buffer() and print_hex_dump() to
> print vertical lines to separate every N groups of
Hi Yannick
On 4/3/19 10:16 AM, Yannick Fertré wrote:
The DSI controller needs a new property that powers its physical layer.
Binding has been updated to documented this property.
Device tree of stm32mp157c soc.
Move reg18 & reg11 to stm32mp157c device tree file.
Remove property phy-dsi-supply
Julien Grall writes ("Re: [OSSTEST PATCH 21/62] ts-kernel-build: disable
host1x, which doesn't build"):
> Ian are we using a different config between Jessie and Stretch?
Not very [1], but we *are* using a different compiler (since we just
use the one from the distro).
[1] There are some changes
On Wednesday, 10 April 2019 at 11:08, Hans de Goede wrote:
> On 10-04-19 11:00, Patrik Jakobsson wrote:
> > On Wed, Apr 10, 2019 at 9:27 AM Hans de Goede wrote:
> > > On 09-04-19 21:31, Dominik 'Rathann' Mierzejewski wrote:
> > > > On Tuesday, 09 April 2019 at 16:44, Hans de Goede wrote:
> > > >
On our RK3399-Q7 EVK base board we have the option to connect an arbitrary
monitor via DP cable. The actual monitor is therefore not known in advance.
This means, we don't have any panel information besides the EDID
data from the device itself.
The functionality for a 'simple-panel' has been
> -Original Message-
> From: David Laight
> Sent: Wednesday, 10 April 2019 6:45 PM
> To: 'Alastair D'Silva' ; alast...@d-silva.org
> Cc: Jani Nikula ; Joonas Lahtinen
> ; Rodrigo Vivi ;
> David Airlie ; Daniel Vetter ; Karsten Keil
> ; Jassi Brar ; Tom Lendacky
> ; David S. Miller ;
>
On 09/04/2019 17:15, Rob Herring wrote:
> On Tue, Apr 9, 2019 at 10:56 AM Tomeu Vizoso
> wrote:
>>
>> On Mon, 8 Apr 2019 at 23:04, Rob Herring wrote:
>>>
>>> On Fri, Apr 5, 2019 at 7:30 AM Steven Price wrote:
On 01/04/2019 08:47, Rob Herring wrote:
> This adds the initial driver
On 08/04/2019 22:04, Rob Herring wrote:
> On Fri, Apr 5, 2019 at 7:30 AM Steven Price wrote:
>>
>> On 01/04/2019 08:47, Rob Herring wrote:
>>> This adds the initial driver for panfrost which supports Arm Mali
>>> Midgard and Bifrost family of GPUs. Currently, only the T860 and
>>> T760 Midgard
On Wednesday, 10 April 2019 at 13:33, Patrik Jakobsson wrote:
> On Wed, Apr 10, 2019 at 1:18 PM Dominik 'Rathann' Mierzejewski
> wrote:
> >
> > On Wednesday, 10 April 2019 at 11:08, Hans de Goede wrote:
> > > On 10-04-19 11:00, Patrik Jakobsson wrote:
> > > > On Wed, Apr 10, 2019 at 9:27 AM Hans
The documentation for simple-panel lists "cptt,claa101wb01" as
compatible string. However, the kernel contains no driver, which
recognizes this string. Therefore this patch replaces the compatible
string with "simple-panel".
Signed-off-by: Christoph Muellner
---
Hi Heiko,
> On 10.04.2019, at 16:50, Heiko Stübner wrote:
>
> Hi Christoph,
>
> Am Mittwoch, 10. April 2019, 16:10:44 CEST schrieb Christoph Muellner:
>> On our RK3399-Q7 EVK base board we have the option to connect an arbitrary
>> monitor via DP cable. The actual monitor is therefore not
Enable and add supply to the Mali GPU node on the
Orange Pi One Plus and Lite2 boards.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
Enable and add supply to the Mali GPU node on the
Beelink GS1 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
This add the H6 mali compatible in the dt-bindings to later support
specific implementation.
Signed-off-by: Clément Péron
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index
Fixing the DMA mapping sg segment warning, which shows "DMA-API: mapping
sg segment longer than device claims to support [len=921600] [max=65536]".
Fixed by setting the max segment size at Komeda driver.
This patch depends on:
- https://patchwork.freedesktop.org/series/54448/
-
Creates plane alpha and blend mode properties attached to plane.
This patch depends on:
- https://patchwork.freedesktop.org/series/54448/
- https://patchwork.freedesktop.org/series/54449/
- https://patchwork.freedesktop.org/series/54450/
Changes since v1:
- Adds patch denpendency in the comment
https://bugs.freedesktop.org/show_bug.cgi?id=108990
--- Comment #2 from CI Bug Log ---
The CI Bug Log issue associated to this bug has been archived.
New failures matching the above filters will not be associated to this bug
anymore.
--
You are receiving this mail because:
You are the
https://bugs.freedesktop.org/show_bug.cgi?id=108990
Martin Peres changed:
What|Removed |Added
Resolution|--- |DUPLICATE
Status|NEW
Hi,
On Thu, Apr 11, 2019 at 12:19:44PM +0200, meg...@megous.com wrote:
> From: Ondrej Jirman
>
> H6 SoC has a "pio group withstand voltage mode" register (datasheet
> description), that needs to be used to select either 1.8V or 3.3V I/O mode,
> based on what voltage is powering the respective
On Thu, Apr 11, 2019 at 12:57:12PM +0200, Clément Péron wrote:
> Hi,
>
> The Allwinner H6 has a Mali-T720 MP2. The drivers are
> out-of-tree so this series only introduce the dt-bindings.
>
> The first patch is from Neil Amstrong and has been already
> merged in linux-amlogic. It is required for
https://bugs.freedesktop.org/show_bug.cgi?id=110229
Laurent changed:
What|Removed |Added
Summary|Textures binded to |glMemoryBarrier doesn't
On 11.4.2019 11.30, Thierry Reding wrote:
On Thu, Apr 11, 2019 at 09:23:13AM +0100, Ben Dooks wrote:
On 2019-04-10 23:47, Stefan Agner wrote:
In case the IOMMU API is not available compiling host1x fails with
the following error:
In file included from drivers/gpu/host1x/hw/host1x06.c:27:
https://bugs.freedesktop.org/show_bug.cgi?id=110229
--- Comment #26 from Laurent ---
Hi! Is still someone here ?
I've found the function which doesn't work, it's glMemoryBarrier.
glCheck(glMemoryBarrier( GL_SHADER_STORAGE_BARRIER_BIT ));
It doesn't wait after the first shader have written all
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add ddp write register common api
> this is preparation patch for ovl/ovl_2l direct link
> usecase.
> in that case, we need this funtion to set one bit of ovl_2l
> register
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add function to background color input select for ovl/ovl_2l
> direct link
> for ovl/ovl_2l direct link usecase, we need set background color
> input select for these
On Thu, Apr 11, 2019 at 12:19:47PM +0200, meg...@megous.com wrote:
> From: Ondrej Jirman
>
> Orange Pi 3 board requires enabling DDC I2C bus via some GPIO connected
> transistors, before the bus can be used.
>
> Model this as a power supply for DDC bus on the HDMI connector connected
> to the
>>
>> >-Original Message-
>> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On
>> >Behalf Of Ville Syrjälä
>> >Sent: Monday, April 8, 2019 9:38 PM
>> >To: Shankar, Uma
>> >Cc: dcasta...@chromium.org; intel-...@lists.freedesktop.org; dri-
>>
On Thu, Apr 11, 2019 at 09:23:13AM +0100, Ben Dooks wrote:
>
>
> On 2019-04-10 23:47, Stefan Agner wrote:
> > In case the IOMMU API is not available compiling host1x fails with
> > the following error:
> > In file included from drivers/gpu/host1x/hw/host1x06.c:27:
> >
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add support for mediatek SOC MT8183
> 1.ovl_2l share driver with ovl
> 2.rdma1 share drive with rdma0, but fifo size is different
> 3.add mt8183 mutex private data, and mmsys
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add mmsys private data for ddp path config
> all these register offset and value will be different in future SOC
> add these define into mmsys private data
> u32
Den 07.04.2019 18.52, skrev Noralf Trønnes:
> It is generic code and having it in the helper will let other drivers
> benefit from it.
>
> One change was necessary assuming this to be true:
> INTEL_INFO(dev_priv)->num_pipes == dev->mode_config.num_crtc
>
> Suggested-by: Daniel Vetter
> Cc:
Den 10.04.2019 15.03, skrev Neil Armstrong:
> On 10/04/2019 14:43, Noralf Trønnes wrote:
>> Due to copy/paste error, the fbdev format was changed to 32bpp = XRGB
>> which is an emulated format for the RGB565 drivers. Revert to to using the
>> fallback which is
https://bugs.freedesktop.org/show_bug.cgi?id=109692
--- Comment #37 from Andrey Grodzovsky ---
(In reply to mikhail.v.gavrilov from comment #36)
> Created attachment 143928 [details]
> Demonstration how message "drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to
> initialize parser -125!" get a
https://bugs.freedesktop.org/show_bug.cgi?id=109692
--- Comment #38 from Michel Dänzer ---
(In reply to Andrey Grodzovsky from comment #37)
> Those messages are actually expected for this particular use case, i might
> consider switching them to info.
I'd argue they should be debug, so they
On Thu, Apr 11, 2019 at 02:31:48PM +0300, Dmitry Osipenko wrote:
> 11.04.2019 13:06, Mikko Perttunen пишет:
> > On 11.4.2019 11.30, Thierry Reding wrote:
> >> On Thu, Apr 11, 2019 at 09:23:13AM +0100, Ben Dooks wrote:
> >>>
> >>>
> >>> On 2019-04-10 23:47, Stefan Agner wrote:
> In case the
On Wed, Apr 10, 2019 at 04:41:57PM -0700, Ira Weiny wrote:
> On Tue, Mar 26, 2019 at 12:47:46PM -0400, Jerome Glisse wrote:
> > From: Jérôme Glisse
> >
> > CPU page table update can happens for many reasons, not only as a result
> > of a syscall (munmap(), mprotect(), mremap(), madvise(), ...)
> On Wed, Apr 10, 2019 at 04:41:57PM -0700, Ira Weiny wrote:
> > On Tue, Mar 26, 2019 at 12:47:46PM -0400, Jerome Glisse wrote:
> > > From: Jérôme Glisse
> > >
> > > CPU page table update can happens for many reasons, not only as a
> > > result of a syscall (munmap(), mprotect(), mremap(),
Patch '5edb0c9b Fix deadlock with display during hanged ring recovery'
was accidentaly removed during one of DALs code merges.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff
From: Christian König
We now destroy finished jobs from the worker thread to make sure that
we never destroy a job currently in timeout processing.
By this we avoid holding lock around ring mirror list in drm_sched_stop
which should solve a deadlock reported by a user.
v2: Remove unused
Also reject TDRs if another one already running.
v2:
Stop all schedulers across device and entire XGMI hive before
force signaling HW fences.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 125 -
1 file changed, 88 insertions(+),
For later driver's reference to see if the fence is signaled.
v2: Move parent fence put to resubmit jobs.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/scheduler/sched_main.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=110405
Bug ID: 110405
Summary: No successful install of amdgpu 18.30 on Ubuntu
18.04.02 LTS
Product: DRI
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux
https://bugs.freedesktop.org/show_bug.cgi?id=110405
Michel Dänzer changed:
What|Removed |Added
Component|DRM/AMDgpu |DRM/AMDgpu-pro
--
You are receiving
The command line parser is pretty tough to get right and very error prone,
so let's add a selftest to try to catch any regression.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/selftests/Makefile | 2 +-
drivers/gpu/drm/selftests/drm_cmdline_selftests.h | 49 +-
On Mon, Apr 01, 2019 at 08:11:00PM +0100, Robin Murphy wrote:
> With the diff below squashed in to address my outstanding style nits,
>
> Acked-by: Robin Murphy
>
> I don't foresee any conflicting io-pgtable changes to prevent this going via
> DRM, but I'll leave the final say up to Joerg.
No
From: Maxime Ripard
Rewrite the command line parser in order to get away from the state machine
parsing the video mode lines.
Hopefully, this will allow to extend it more easily to support named modes
and / or properties set directly on the command line.
Signed-off-by: Maxime Ripard
---
Den 11.04.2019 06.49, skrev Gerd Hoffmann:
> Oops, the __iomem annotation was added to the header file only.
> Add it to the implementation (and documentation) too.
>
> Fixes: 5c5373b51bec ("drm: switch drm_fb_xrgb_to_rgb888_dstclip to accept
> __iomem dst")
> Signed-off-by: Gerd Hoffmann
https://bugs.freedesktop.org/show_bug.cgi?id=110229
Laurent changed:
What|Removed |Added
CC||laurentduroi...@gmail.com
--- Comment #28
https://bugs.freedesktop.org/show_bug.cgi?id=110229
Laurent changed:
What|Removed |Added
Status|NEEDINFO|RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=110229
--- Comment #29 from Laurent ---
Created attachment 143939
--> https://bugs.freedesktop.org/attachment.cgi?id=143939=edit
The main function.
--
You are receiving this mail because:
You are the assignee for the
https://bugs.freedesktop.org/show_bug.cgi?id=109692
--- Comment #39 from mikhail.v.gavri...@gmail.com ---
(In reply to Michel Dänzer from comment #38)
>
> I'd argue they should be debug, so they don't spam dmesg by default.
Let this messages stay in kernel log (dmesg), but I don't want see they
https://bugs.freedesktop.org/show_bug.cgi?id=110229
--- Comment #31 from Laurent ---
Okey, I've found a temporary solution : putting instructions in the second
fragment shader to slow down the shader execution code and it works...
const std::string fragmentShader2 =
R"(
On Thu, Apr 11, 2019 at 05:42:56PM +0200, Jernej Škrabec wrote:
> Dne četrtek, 11. april 2019 ob 17:27:52 CEST je Maxime Ripard napisal(a):
> > On Thu, Apr 11, 2019 at 05:23:25PM +0200, Jernej Škrabec wrote:
> > > Dne četrtek, 11. april 2019 ob 17:20:04 CEST je Clément Péron napisal(a):
> > > >
On Thu, Apr 11, 2019 at 10:27 AM Maxime Ripard
wrote:
>
> On Thu, Apr 11, 2019 at 05:23:25PM +0200, Jernej Škrabec wrote:
> > Dne četrtek, 11. april 2019 ob 17:20:04 CEST je Clément Péron napisal(a):
> > > Hi,
> > >
> > > On Thu, 11 Apr 2019 at 17:05, Jernej Škrabec
> > wrote:
> > > > Dne
Hi Dave, Daniel,
Here is a new drm-misc-fixes PR.
thanks!
maxime
drm-misc-fixes-2019-04-11:
- core: Make atomic_enable and disable optional for CRTC
- dw-hdmi: Lower max frequency for the Allwinner H6, SCDC configuration
improvements for older controller versions
- omap: a fix
On Thu, Apr 11, 2019 at 05:23:25PM +0200, Jernej Škrabec wrote:
> Dne četrtek, 11. april 2019 ob 17:20:04 CEST je Clément Péron napisal(a):
> > Hi,
> >
> > On Thu, 11 Apr 2019 at 17:05, Jernej Škrabec
> wrote:
> > > Dne četrtek, 11. april 2019 ob 12:57:16 CEST je Clément Péron napisal(a):
> > > >
On 03/30/2019 03:26 AM, YueHaibing wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/video/fbdev/pvr2fb.c: In function 'pvr2fb_init':
> drivers/video/fbdev/pvr2fb.c:1074:6: warning:
> variable 'size' set but not used [-Wunused-but-set-variable]
>
> It's not used since commit
Hi,
The proprietary stack for the RaspberryPi allows for a number of video
parameters widely used by their users, but yet don't have any equivalents
in the mainline kernel.
Those options are detailed here:
https://www.raspberrypi.org/documentation/configuration/config-txt/video.md
While not all
From: Maxime Ripard
The drm subsystem also uses the video= kernel parameter, and in the
documentation refers to the fbdev documentation for that parameter.
However, that documentation also says that instead of giving the mode using
its resolution we can also give a name. However, DRM doesn't
Rotations and reflections setup are needed in some scenarios to initialise
properly the initial framebuffer. Some drivers already had a bunch of
quirks to deal with this, such as either a private kernel command line
parameter (omapdss) or on the device tree (various panels).
In order to
Properly configuring the overscan properties might be needed for the
initial setup of the framebuffer for display that still have overscan.
Let's allow for more properties on the kernel command line to setup each
margin.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/drm_fb_helper.c | 47
1 - 100 of 141 matches
Mail list logo
